Patent Application
20060128040
The present invention relates to a semiconductor packaging technology, and more particularly, to a bond positioning method for a wire-bonding process and a substrate for the bond positioning method.
Along with advent of the so-called micro-profit era, the issue of how to improve the yield for each process of semiconductor production so as to avoid expenditure for defective products has been always one of the important factors influencing the profit of semiconductor industry. It is the same for those engaged in producing semiconductor packages.
Generally, the fabrication method for the above-mentioned semiconductor packages include the steps of performing a die-bonding process and a wire-bonding process on a surface of a chip carrier such as a substrate, so as to establish an electrical connection between a chip and the substrate, and then performing an encapsulation process and optionally a cutting process, thereby forming a semiconductor package. In the mass-automation manufacturing process employed, the semiconductor packages are usually produced in a batch type method, wherein a plurality of the above-described substrates are integrally arranged in matrix on a substrate strip, and the substrate strip is then transmitted by a carrier to various automation packaging apparatus in sequence, such as die bonding apparatus, wire bonding apparatus and the like, so as to be subjected to a die-bonding operation, wire-bonding operation, encapsulation operation and cutting operation, to thereby form a plurality of semiconductor packages.
To subsequently solder and electrically connect the semiconductor package to an external device with solder balls, or to effectively connect the chip thereof to the substrate, it is necessary to form a plurality of conductive traces, which are, for example, made of copper, on a surface of the substrate, allowing electrical connection portions for signal transmission, such as fingers, solder ball pads and the like, to be exposed from a solder mask layer on the surface of the substrate. A metal layer such as Ni/Au layer is electroplated on a surface of each of the electrical connection portions, so as to allow the chip or the substrate to be effectively electrically coupled to other conductive elements, such as gold wires, solder bumps, or solder balls, as well as to avoid oxidization of the electrical connection portions caused by the outside environment.
A relevant die bonding process and wire-bonding process will now be further described in detail with a conventional BGA (Ball Grid Array) semiconductor package as an example. As shown in
Since the fiducial mark 19 is also formed from a part of the conductive traces of the substrate 1, relative positions between the fiducial mark and the die pad 11 as well as the electrical connection portions 15, 151 and 153 are definitely not changed. Therefore, once the fiducial mark 19 is recognized by the image capturing unit of the die bonding apparatus and the coordinate data is determined, coordinates for the die bonding process are determined, and coordinates for the subsequent wire-bonding process are also determined with respect to data for the chip 17, whereby a first bonding point and a second bonding point of each of the bonding wires 173 can be accurately bonded onto the bond pad 171 of the chip 17 and the electrical connection portion 15 respectively.
However, there is generally a deviation of ±75 μm for the position of each of the openings (including the openings 133 corresponding to the locations of the electrical connection portions, and the opening 131 corresponding to the location of the fiducial mark) in the solder mask layer 13 on the surface of the substrate 1. Since the size of the fiducial mark 19 is usually much bigger than such a tolerance of position deviation, the position of the central portion of the fiducial mark 19 can be easily recognized even when the opening 131 deviates considerably. However, for the electrical connection portions 15, 151 and 153, the position deviation of the corresponding openings thereof would result in various bonding failures such as detachment, bending, or cracking of the bonding wires. The electrical connection portions 15, 151 and 153 are generally classified into ground ring, power ring and finger according to the functionality thereof. Since there is no difference between the wire-bonding processes for those different portions, only the wire-bonding process for the electrical connection portion 15 representing the ground ring will be described in the following.
As shown in
On the other hand, as shown in
Disclosures in U.S. Pat. No. 6,468,813 and U.S. Pat. No. 6,668,449 are both related to an approach in which the forgoing fiducial mark is provided on the substrate to be used for determining coordinate data in the die bonding process along with details of the chip that is positioned in the die bonding process in order to perform the wire-bonding process so as to prevent the positions of the first bonding point and the second bonding point from being deviated. However, this approach does not address the bonding failure which is caused by the position deviation of the solder mask layer.
U.S. Pat. No. 6,468,813 discloses a method for automatically detecting product quality and skipping a defective product during the wire-bonding process. In the method, a reject eye provided above a chip mounting area is used to automatically determine whether a skipping procedure should be executed or not. However, in such a method, a product is only judged as a defective one if a position deviation of a solder mask layer has been observed, without any attempt to adjust for such deviation to improve the product yield. Moreover, this method is only suitable for skipping a defective product in which the position deviation of the opening of the solder mask layer has such a large deviation that the reject eye only sees the opening of the solder mask layer. For the case that an opening of the solder mask layer in a product has a position deviation that doesn't completely occupy the view of the reject eye, the forgoing bonding failure of the second bonding point may be caused since the product is not judged as a defective one and the wire-bonding process is still performed without any compensation. Thus, the yield of the wire-bonding process may be decreased, resulting in expenditure on the defective products and increasing the overall fabrication cost.
Hence, there has an urgent need in the art to develop semiconductor packaging technology for solving the forgoing drawbacks, in which the second bonding point can be re-positioned to compensate for any position deviation of the opening of the solder mask layer during the wire-bonding process, to thereby avoid the problems of defective bonding wires such as bending, cracking, or detachment of the bonding wires caused by the undesirable contact between the bonding wires and the solder mask layer in the conventional wire bonding process, thus increasing the product yield in the wire-bonding process, thereby saving cost on the defective products and decreasing the overall fabrication cost.
In view of the forgoing and other drawbacks, an objective of the present invention is to provide a bond positioning method for a wire-bonding process and a substrate for the bond positioning method to re-define the positioning of a bonding point of a bonding wire according to a deviation of a solder mask layer.
Another objective of the present invention is to provide a bond positioning method for a wire-bonding process and a substrate for the bond positioning method for preventing a bonding wire from contact with any edges of the solder mask layer.
Still another objective of the present invention is to provide a bond positioning method for a wire-bonding process and a substrate for the bond positioning method for avoiding bonding failure caused by position deviation of the solder mask layer.
Still another objective of the present invention is to provide a bond positioning method for a wire-bonding process and a substrate for the bond positioning method for improving the product yield of the wire-bonding process, so as to save cost on defective products and reduce the overall fabrication cost.
For attaining the above and other objectives, the present invention provides a bond positioning method for a wire-bonding process that redefines the positioning of a second bonding point of a bonding wire bonded to a substrate which has been provided with a solder mask layer and a chip on a surface thereof, the method comprising the steps of: forming at least one solder mask mark in the solder mask layer on the substrate in advance; determining deviation of the solder mask layer with the solder mask layer mark serving as a reference point; and performing coordinate compensation according to the deviation so as to re-define positioning of the second bonding point of the bonding wire.
Preferably, a predetermined xy-coordinate pair of the solder mask mark serves as a data point, and an xy-coordinate pair of the solder mask mark serves as a reference point, while the distance between the data point and the reference point or a vector from the data point to the reference point is taken as the deviation of the solder mask layer, wherein the data point is the predetermined xy-coordinate pair of the central point of the solder mask mark, and the reference point is the xy-coordinate pair of the central point of the solder mask mark.
The present invention also provides a substrate for the above-described method, the substrate at least comprising: a plurality of conductive traces and a plurality of electrical connection portions formed on a surface of the substrate; a solder mask layer for covering the plurality of conductive traces and exposing the plurality of electrical connection portions; a chip mounting area for mounting a chip thereon; and a solder mask mark formed in the solder mask layer for serving as a reference point for determining deviation of the solder mask layer and performing coordinate compensation according to the deviation so as to re-define positioning of a second bonding point of a bonding wire.
The solder mask mark is an opening formed in the solder mask layer wherein a metal pad formed on the substrate is exposed through the opening. The metal pad is preferably formed of a part of the conductive traces on the surface of the substrate. The metal pad is formed with a pattern with which a central point of the metal pad can be calculated, wherein the pattern is preferably selected from a group consisting of a cross, square, rectangle, circle, ellipse, diamond, equiangular triangle, and equiangular polygon. Moreover, an electroplating layer may be optionally provided on a surface of the metal pad, wherein the electroplating layer is preferably comprised of a metal of one of gold, palladium and silver, or a metallic material selected from the group consisting of nickel-gold, nickel-palladium and nickel-silver alloy. Furthermore, the size of the opening may be smaller than that of the metal pad, while the shape of the opening is a pattern with which a central point of the opening can be calculated, wherein the pattern is preferably selected from the group consisting of a cross, square, rectangle, circle, ellipse, diamond, equiangular triangle, and equiangular polygon.
A substrate mark for positioning the substrate is also provided on the substrate. Preferably, the substrate mark is a metal pad formed on the substrate, and a corresponding opening in formed in the solder mask layer to expose the metal pad. Preferably, the size of the metal pad is smaller than that of the opening. Moreover, the metal pad is preferably formed of a part of the conductive traces. Furthermore, an electroplating layer may be provided on a surface of the metal pad, wherein the electroplating layer is preferably comprised of a metal of one of gold, palladium and silver, or a metallic material selected from the group consisted of nickel-gold, nickel-palladium and nickel-silver alloy.
Alternatively, a substrate mark superimposed with the solder mask mark for positioning the substrate may be provided on the substrate. Preferably, the substrate mark is formed of a hollow part of a metal pad, while the solder mask mark is an opening formed in the solder mask layer to allow the metal pad to be exposed through the opening, wherein the size of the opening is smaller than that of the metal pad, and the size of the hollow part is smaller than that of the opening. The hollow part and/or the opening may be formed with a pattern with which a central point of the hollow part and/or the opening can be calculated, wherein the pattern is preferably selected from the group consisting of a cross, square, rectangle, circle, ellipse, diamond, equiangular triangle, and equiangular polygon. The metal pad may be formed of a part of the conductive traces on the surface of the substrate. Moreover, an electroplating layer may be provided on a surface of the metal pad, wherein the electroplating layer is preferably comprised of a metal of one of gold, palladium and silver, or a metallic material selected from the group consisting of nickel-gold, nickel-palladium and nickel-silver alloy.
In addition, the substrate is a Ball Grid Array substrate. The second bonding point of each of the bonding wires is arranged at a corresponding electrical connection portion of the substrate, while the electrical connection portion is one of the ground ring, power ring, and finger.
In the bond positioning method for the wire-bonding process, at least one solder mask mark is formed in advance in the solder mask layer on the substrate, such that, during the wire-bonding process, this solder mask mark serves as a reference point for determining deviation of the solder mask layer and performing coordinate compensation according to the deviation so as to re-define positioning of the second bonding point of the bonding wire. This can overcome the problems of defective bonding wires such as bending, cracking, or detachment of the bonding wires caused by undesirable contact between the bonding wires and the solder mask layer in the conventional wire-bonding process since the positioning of the second bonding point is re-defined according to the deviation of the solder mask layer, thereby improving the product yield of the wire-bonding process, saving cost on defective products, and reducing the overall fabrication cost.
The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
The present invention will be described in detail with specific embodiments. However, the embodiments are illustrative in nature and are not intended to limit the scope or the spirit of the present invention. In particular, though a ball grid array substrate is illustrated in the description and the accompanying drawings to facilitate understanding of the present invention, the bond positioning method for a wire-bonding process and the substrate for the method provided in the present invention can be applied in various semiconductor packages with a substrate used as chip carrier.
Referring to
In order to allow the die bonding apparatus to perform the die bonding process with high positioning accuracy, at least one substrate mark 221 is formed in advance on the upper surface of the substrate 2. The substrate mark 221 is a metal pad with, for example, a cross shape, and is also formed of a part of the conductive traces 22 with an electroplating layer such as a Ni/Au layer plated thereon. An opening 231 corresponding to the substrate mark 221 is formed in the solder mask layer 23 so as to allow the substrate mark 221 to be exposed through the opening 231 and recognized by an image capturing unit of the die bonding apparatus for determining coordinate data. The size of the substrate mark 221, which is for example a cross-shaped metal pad, is smaller than that of the opening 231, such that the central point of the substrate mark 221 can still be recognized even when the solder mask layer 23 is deviated (within ±75 μm).
Moreover, at least one solder mask mark 232 is also provided in advance in the solder mask layer 23. In the present embodiment, the solder mask mark 232 is, for example, a cross-shaped opening formed in the solder mask layer 23. A metal pad 223 formed on the substrate 2 is exposed through the opening, wherein the metal pad is also a part of the conductive traces 22 with an electroplating layer such as a Ni/Au layer plated thereon. The size of the solder mask mark 232, which is cross-shaped for example, is smaller than that of the metal pad 223, such that the central point of the solder mask mark 232 can still be recognized by a significant color difference between the solder mask layer 23 and the metal pad 223 even when the solder mask layer 23 is deviated (within ±75 μm). Generally, the color of the solder mask layer 23 is dark green, and the color of the metal pad 223 is golden.
Since the substrate mark 221 is formed of a part of the conductive traces 22 of the substrate 2, the relative positions between the substrate mark 221 and the die pad 21 as well as the electrical connection portions 25, 251 and 253 are definitely not changed. Therefore, once the substrate mark 221 is recognized by the image capturing unit of the die bonding apparatus and the coordinate data is determined, an xy-coordinate pair for the die bonding process is determined, and an xy-coordinate pair for the subsequent wire-bonding process is also determined with respect to data for the chip 27, whereby a first bonding point and a second bonding point for each of the bonding wires 273 can be accurately bonded onto the bond pad 271 of the chip 27 and the electrical connection portion 25 respectively.
However, when there is a position deviation (within ±75 μm) of the solder mask layer 23 occurring with respect to the substrate 2, positions of each of the openings, which correspond to the electrical connection portions and the marks respectively, are deviated correspondingly. For the electrical connection portions 25, 251 and 253, the position deviation of the corresponding openings thereof would result in various bonding failures such as detachment, bending, or cracking of the bonding wires. The electrical connection portions 25, 251 and 253 are generally classified into ground ring, power ring and finger according to functionality. Since there is no difference between the wire-bonding processes for those different portions, only the wire-bonding process for the electrical connection portion 25, which represents the ground ring will be described as follows.
As shown in
On the other hand, as shown in
While the actual xy-coordinate pair of the solder mask mark 232 is recognized as described-above, the xy-coordinate pair of the central point of the solder mask mark 232, such as a cross-shaped opening, is used as the actual xy-coordinate pair. The same applies for the substrate mark 221.
Furthermore, though the present embodiment is exemplified by a case in which the distance between the data point and the reference point is calculated and utilized as the deviation of the solder mask layer 23, the present invention is not limited to the use of such a one-dimensional deviation. A vector from the data point to the reference point may be calculated and utilized as the deviation of the solder mask layer 23, and thus a two-dimensional vector compensation of the coordinate can be performed according to this vector deviation.
Referring to
Referring to
The solder mask marks in the forgoing embodiments are all formed with patterns in which a central point can be calculated. Therefore, it should be noted that the pattern of the solder mask mark and the substrate mark is not limited to the above-depicted cross shape, square shape or circular shape, and other pattern such as a rectangle, ellipse, diamond, equiangular triangle, and equiangular polygon may also be adopted as long as the central point of the pattern is available.
Referring to
As shown in
The size of the solder mask mark 2351 (i.e. the cross-shaped opening) is smaller than that of the metal pad 225, and the size of substrate mark 2251 (i.e. the cross-shaped hollow part) is smaller than that of the solder mask mark 2351. In determining the actual coordinates of the solder mask mark 2351, the coordinates of the central point of the solder mask mark 2351 can be obtained by calculating the intersection of the cross-shaped opening thereof. In determining the actual coordinates of the substrate mark 2251, the coordinates of the central point of the substrate mark 2251 can be obtained by calculating the intersection of the cross-shaped hollow part thereof.
As an example,
In the present embodiment, an integrated mark configuration in which the solder mask mark 2351 is superimposed with the substrate mark 2251 is illustrated, wherein such configuration facilitates the image capturing unit provided in the die bonding apparatus or the wire bonding apparatus to recognize the marks quickly from one position, without the necessity to be moved between multiple positions, thereby increasing the recognition speed. Herein, the calculation of the deviation and the re-definition of the positioning of the second bonding point of the bonding wire will not be described again since they have been explicitly described in the first embodiment.
Referring to
Referring to
As described above, in the bond positioning method for the wire-bonding process, at least one solder mask mark is formed in advance in the solder mask layer on the substrate, such that, during the wire-bonding process, this solder mask mark serves as a reference point for determining deviation of the solder mask layer and performing coordinate compensation according to the deviation so as to re-define positioning of the second bonding point of the bonding wire. This can overcome the problems of defective bonding wires such as bending, cracking, or detachment of the bonding wires caused by the undesirable contact between the bonding wires and the solder mask layer in the conventional wire-bonding process since the positioning of the second bonding point is re-defined according to the deviation of the solder mask layer, thereby improving the product yield of the wire-bonding process, saving cost on defective products and reducing the overall fabrication cost. Therefore, the bond positioning method for the wire-bonding process and the substrate for the bond positioning method proposed in the present invention can overcome various drawbacks of the conventional technology, bring significant improvement with high industry applicability.
It should be apparent to those skilled in the art that the above description is only illustrative of specific embodiments and examples of the present invention. The present invention should therefore cover various modifications and variations made to the herein-described structure and operations of the present invention, provided they fall within the scope of the present invention as defined in the following appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 93138689 | Dec 2004 | TW | national |
