This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2018-002897, filed on Jan. 11, 2018, the entire contents of which are incorporated herein by reference.
The disclosures discussed herein relate to a compound semiconductor device and a fabrication method.
Application of nitride semiconductors to semiconductor devices with high withstand voltage and high power has been studied utilizing characteristics such as high saturated electron velocity and wide band gap. For semiconductor devices using nitride semiconductors, there have been many reports on field effect transistors, particularly high electron mobility transistors (HEMTs).
For example, in GaN-based HEMTs (GaN-HEMT), an InAlN-HEMT using GaN as a channel layer and InAlN as a barrier layer attracts attention. InAlN is known to lattice match with GaN in an In composition range of 17% to 18%. In this composition range, InAlN has a very high spontaneous polarization so as to implement two-dimensional electron gas (2DEG) with higher concentration than conventional AlGaN-HEMT. Therefore, InAlN/GaN-HEMT has attracted attention as a next generation high power device.
Patent Document 1: Japanese Laid-open Patent Publication No. 2016-225578
Patent Document 2: Japanese Laid-open Patent Publication No. 2016-162889
Patent Document 3: Japanese Laid-open Patent Publication No. 2010-267658
Patent Document 4: International Publication Pamphlet No. WO 2013/125126
According to an aspect of an embodiment, a compound semiconductor device includes:
According to another aspect of an embodiment, a method for fabricating a compound semiconductor device includes:
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.
In a compound semiconductor device using InAlN, the surface flatness of InAlN is typically poor, which leads to an increase in sheet resistance and a large internal leakage current due to a strong internal electric field.
Thus, it is desirable to provide a compound semiconductor device capable of reducing leakage current while reducing sheet resistance, and also provide a fabrication method thereof.
In a first embodiment, a nitride semiconductor InAlGaN-HEMT is disclosed as a compound semiconductor device.
First, as illustrated in
In the InAlGaN-HEMT, two-dimensional electron gas (2DEG) is generated as carriers in the channel layer 2b in the vicinity of an interface between the channel layer 2b and the barrier layer 2d (to be precise, the spacer layer 2c). The 2DEG is generated based on the difference in polarization between a compound semiconductor (GaN in this case) of the channel layer 2b and a compound semiconductor (InAlGaN in this case) of the barrier layer 2d.
Specifically, the following compound semiconductors are grown on the SiC substrate 1 by, for example, a metal organic vapor phase epitaxy (MOVPE) method. Instead of the MOVPE method, a molecular beam epitaxy (MBE) method, or the like may be used.
On the SiC substrate 1, AlN is grown to a thickness of approximately 100 nm, i-GaN (intentionally undoped-GaN) is grown to a thickness of approximately 3 μm, AlGaN is grown to a thickness of approximately 2 nm, and InAlGaN is grown to a thickness of approximately 8 nm, in the sequential order. Thus, the nucleation layer 2a, the channel layer 2b, the spacer layer 2c, and the barrier layer 2d are formed. Note that in order to improve the high frequency characteristic, it is necessary to shorten the distance from the gate electrode to 2DEG. However, it is also necessary to ensure a sufficient carrier concentration (2DEG concentration). In view of the above requirements, it is desirable to set a total thickness of the spacer layer 2c and the barrier layer 2d to approximately 4 nm or more and approximately 10 nm or less.
The spacer layer 2c is made of Aly1Ga1-y1N with the Al composition set to y1, where y1 is set to 0.20<y1≤0.70, and more preferably is set to 0.22≤y1≤0.60. The barrier layer 2d is made of Inx2Aly2Ga1-x2-y2N with an In composition of x2 and an Al composition of y2, where x2 and y2 are set to 0≤x2≤0.15 and 0.20≤y2<0.70, and more preferably are set to 0.005≤x≤2≤0.15 and 0.22≤y2≤0.60. y1 and y2 satisfy a relationship of y1>y2.
As a growth condition of AlN, a mixed gas of trimethylaluminum (TMAl) gas and ammonia (NH3) gas is used as a source gas. As a growth condition of GaN, a mixed gas of trimethyl gallium (TMGa) gas and NH3 gas is used as a source gas. As a growth condition of AlGaN, a mixed gas of TMAl gas, TMGa gas, and NH3 gas is used as a source gas. As a growth condition of InAlGaN, a mixed gas of trimethylindium (TMIn) gas, TMAl gas, TMGa gas, and NH3 gas is used as a source gas. Depending on a compound semiconductor layer to grow, the presence or absence of supply and flow rate of TMIn gas acting as an In source, TMAl gas acting as Al source, and TMGa gas acting as a Ga source are appropriately set to adjust In composition, Al composition, and Ga composition. The flow rate of the NH3 gas used as a common source is set to approximately 100 ccm to 30 LM. Further, the growth pressure is set to approximately 1 kPa to 100 kPa, and the growth temperature is set to approximately 700° C. to 1200° C.
Subsequently, an element isolation structure (not illustrated) is formed. Specifically, for example, argon (Ar) is implanted into an element isolation region of the compound semiconductor multilayer structure 2. The element isolation structure is thus formed in surface layer portions of the compound semiconductor multilayer structure 2 and the SiC substrate 1. An active region is defined by the element isolation structure on the compound semiconductor multilayer structure 2. Note that the element isolation may be performed by, for example, an STI (Shallow Trench Isolation) method instead of the above implantation method. In this case, a chlorine-based etching gas is used for dry etching of the compound semiconductor multilayer structure 2, for example.
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Specifically, first, a resist mask for forming a gate electrode is formed. In this example, an eaves structure double layered resist suitable for the vapor deposition method and the lift-off method is used. This resist is applied on the passivation film 5 to form an opening exposing a portion of the opening 5a of the passivation film 5. Thus, a resist mask having the opening is formed.
Using this resist mask, Ni/Au is deposited, for example, as an electrode material on the resist mask including the resist mask applied to the inside of the opening exposing a portion of the opening 5a of the passivation film 5, for example, by vapor deposition. The thickness of Ni is approximately 30 nm and the thickness of Au is approximately 400 nm. The resist mask and the Ni/Au deposited on the resist mask are removed by the lift-off method. As described above, the gate electrode 6 is formed on the passivation film 5 so as to embed the inside of the opening 5a with part of the electrode material.
Thereafter, an InAlGaN-HEMT according to the first embodiment is formed through various steps, such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 3, the drain electrode 4 and the gate electrode 6, formation of an upper passivation film, formation of connection electrodes exposed on the outermost surface, and the like.
The following illustrates effects of the InAlGaN-HEMT according to the first embodiment.
In the first embodiment, as described above, the spacer layer 2c (Aly1Ga1-y1N) satisfies 0.20<y1≤0.70, and more preferably satisfies 0.22≤y1≤0.60. The barrier layer 2d (Inx2Aly2Ga1-x2-y2N) satisfies 0≤x2≤0.15 and 0.20≤y2<0.70, and more preferably satisfies 0.005≤x2≤0.15 and 0.22≤y2≤0.60. y1 and y2 satisfy a relationship of y1>y2.
In the spacer layer of AlGaN, when the Al composition is high, sheet resistance increases due to surface roughness or the like.
According to
Thus, in the InAlGaN-HEMT, the sheet resistance may be sufficiently reduced by defining the upper limit of the Al composition of the AlGaN spacer layer and the lower limit of the Al composition of the InAlGaN barrier layer. However, while the sheet resistance is improved, the gate leakage current being large becomes obvious.
With respect to
In the InAlGaN-HEMT, the In composition of the barrier layer of InAlGaN is preferably in a range of approximately 0(%) to 15(%) in consideration of the lattice matching with the GaN of the channel layer.
As described above, in the first embodiment, the Al composition y1 of the spacer layer 2c (Aly1Ga1-y1N), the In composition x2, and the Al composition y2 of the barrier layer 2d (Inx2Aly2Ga1-x2-y2N) are defined as follows:
0.20<y1≤0.70
0≤x2≤0.15
0.20≤y2<0.70
y1>y2
According to the definitions described above, it is possible to reduce the leakage current while reducing the sheet resistance.
Note that with respect to the Al composition y1 of the spacer layer 2c and the Al composition y2 of the barrier layer 2d, it is preferable to set y1 to 0.22≤y1≤0.60 and set y2 to 0.22≤y2≤0.60, in order to further reduce the sheet resistance as seen from
In a second embodiment, as disclosed in the first embodiment, a nitride semiconductor InAlGaN-HEMT is disclosed as a compound semiconductor device; however, a composition of a compound semiconductor multilayer structure in the second embodiment differs from that of the compound semiconductor multilayer structure in the first embodiment.
First, as illustrated in
The compound semiconductor multilayer structure 2 has a nucleation layer 2a of AlN, a channel layer 2b of GaN, a spacer layer 2c of AlGaN, a barrier layer 2d of InAlGaN, and a cap layer 2e of GaN.
On the SiC substrate 1, AlN is grown to a thickness of approximately 100 nm, i-GaN is grown to a thickness of approximately 3 μm, AlGaN is grown to a thickness of approximately 2 nm, InAlGaN is grown to a thickness of approximately 6 nm, and GaN is grown to a thickness of approximately 2 nm, in an sequential order. Thus, the nucleation layer 2a, the channel layer 2b, the spacer layer 2c, the barrier layer 2d, and the cap layer 2e are formed. Note that in order to improve the high frequency characteristic, it is necessary to shorten the distance from the gate electrode to 2DEG. However, it is also necessary to ensure a sufficient carrier concentration (2DEG concentration). In view of these requirements, it is desirable to set a total thickness of the spacer layer 2c, the barrier layer 2d, and the cap layer 2e to approximately 4 nm or more and approximately 10 nm or less.
The spacer layer 2c is made of Aly1Ga1-y1N with the Al composition set to y1, where y1 is set to 0.20<y1≤0.70, and more preferably is set to 0.22≤y1≤0.60. The barrier layer 2d is made of Inx2Aly2Ga1-x2-y2N with an In composition of x2 and an Al composition of y2, where x2 and y2 are set to 0≤x2≤0.15 and 0.20≤y2<0.70, and more preferably are set to 0.005≤x2≤0.15 and 0.22≤y2≤0.60.
y1 and y2 satisfy a relationship of y1>y2.
Subsequently, as illustrated in
Specifically, after forming the element isolation structure in the element isolation region of the compound semiconductor multilayer structure 2, the electrode recesses 2A and 2B are formed at the formation positions (electrode formation positions) of the source and drain electrodes on the surface of the compound semiconductor multilayer structure 2. A resist is applied to the surface of the compound semiconductor multilayer structure 2. The resist is processed by lithography to form openings exposing the surface of the compound semiconductor multilayer structure 2 corresponding to electrode formation positions in the resist. Thus, a resist mask having the openings is formed.
Using this resist mask, the electrode formation positions of the cap layer 2e are removed by dry etching until the surface of the barrier layer 2d is exposed. Thus, the electrode recesses 2A and 2B exposing the electrode formation positions on the surface of the barrier layer 2d are formed. As etching conditions, an inert gas such as Ar and a chlorine-based gas such as Cl2 may be used as an etching gas, a flow rate of Cl2 may be 30 sccm, a pressure may be 2 Pa, and an RF input power may be 20 W, for example. Note that the electrode recesses 2A and 2B may be formed by etching up to anywhere in the middle of the cap layer 2e or may be formed by etching up to the barrier layer 2d and beyond. The resist mask is removed by asking or the like.
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Using this resist mask, Ni/Au is deposited, for example, as an electrode material on the resist mask including the resist mask applied to the inside of the opening exposing a portion of the opening 5a of the passivation film 5, for example, by vapor deposition. The thickness of Ni is approximately 30 nm and the thickness of Au is approximately 400 nm. The resist mask and the Ni/Au deposited on the resist mask are removed by the lift-off method. As described above, the gate electrode 6 is formed on the passivation film 5 so as to embed the inside of the opening 5a with part of the electrode material.
Thereafter, an InAlGaN-HEMT according to the third embodiment is formed through various steps, such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 3, the drain electrode 4 and the gate electrode 6, formation of an upper passivation film, formation of connection electrodes exposed on the outermost surface, and the like.
In a third embodiment, as disclosed in the first embodiment, a nitride semiconductor InAlGaN-HEMT is disclosed as a compound semiconductor device; however, a composition of a compound semiconductor multilayer structure in the third embodiment differs from that of the compound semiconductor multilayer structure in the first embodiment.
As illustrated in
First, a compound semiconductor multilayer structure 2 is formed, in a manner similar to the first embodiment. The compound semiconductor multilayer structure 2 has a nucleation layer 2a of AlN, a channel layer 2b of GaN, a spacer layer 2c of AlGaN, and a barrier layer 2d of InAlGaN.
The spacer layer 2c is made of Aly1Ga1-y1N with the Al composition of y1, where y1 is set to 0.20<y1≤0.70, and more preferably is set to 0.22≤y1≤0.60. The barrier layer 2d is made of Inx2Aly2Ga1-x2-y2N with an In composition of x2 and an Al composition of y2, where x2 and y2 are set to 0≤x2≤0.15 and 0.20≤y2<0.70, and more preferably are set to 0.005≤x2≤0.15 and 0.22≤y2≤0.60. y1 and y2 satisfy a relationship of y1>y2.
Next, as an insulating material, for example, SiO2 is deposited on the compound semiconductor multilayer structure 2 by, for example, a plasma CVD method. Thus, a surface protective film 11 is formed. Deposition of SiO2 may be conducted by, for example, an ALD method or a sputtering method instead of the plasma CVD method. Instead of depositing SiO2, a nitride or oxynitride of Si may be used for deposition. Besides the above, an oxide, nitride, or oxynitride of Al, Hf, Zr, Ti, Ta or W may be used for deposition, or any of these may be appropriately selected and deposited in multiple layers to forma surface protective film.
Next, a resist is applied to the surface of the compound semiconductor multilayer structure 2. The resist is processed by lithography to form openings exposing the surface of the compound semiconductor multilayer structure 2 corresponding to electrode formation positions in the resist. The resist mask having the openings is thus formed. The compound semiconductor multilayer structure 2 is dry-etched using this resist mask to remove portions of the surface protective film 11, the barrier layer 2d, the spacer layer 2c, and the channel layer 2b. As an etching gas, an inert gas such as Ar and a chlorine-based gas such as Cl2 are used. The regrowth recesses 2C and 2D of the compound semiconductor multilayer structure 2 are thus formed.
Subsequently, as illustrated in
Subsequently, as illustrated in
Using this resist mask, Ta/Al is, for example, deposited as an electrode material on the resist mask including the resist mask applied to the inside of the openings by vapor deposition. The thickness of Ta is approximately 20 nm and the thickness of Al is approximately 200 nm. The resist mask and the Ta/Al deposited on the resist mask are removed by the lift-off method. Thereafter, the SiC substrate 1 is heated, for example, under a nitrogen atmosphere at a temperature range of approximately 400° C. to 1000° C., for example, at a temperature of approximately 550° C., and the remaining Ta/Al is brought into ohmic contact with the contact layers 12 and 13. Heat treatment may be unnecessary insofar as ohmic contact between Ta/Al and the contact layers 12 and 13 is obtained. Thus, the source electrode 3 and the drain electrode 4 are formed on the contact layers 12 and 13.
Subsequently, as illustrated in
Subsequently, as illustrated in
Next, a resist mask for forming a gate electrode is formed. In this example, an eaves structure double layered resist suitable for the vapor deposition method and the lift-off method is used. This resist is applied on the passivation film 5 to form an opening exposing a portion of the opening 5a of the passivation film 5. Thus, a resist mask having the opening is formed.
Using this resist mask, Ni/Au is deposited, for example, as an electrode material on the resist mask including the resist mask applied to the inside of the opening exposing a portion of the opening 5a of the passivation film 5, for example, by vapor deposition. The thickness of Ni is approximately 30 nm and the thickness of Au is approximately 400 nm. The resist mask and the Ni/Au deposited on the resist mask are removed by the lift-off method. As described above, the gate electrode 6 is formed on the passivation film 5 so as to embed the inside of the opening 5a with part of the electrode material.
Thereafter, an InAlGaN-HEMT according to the third embodiment is formed through various steps, such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 3, the drain electrode 4 and the gate electrode 6, formation of an upper passivation film, formation of connection electrodes exposed on the outermost surface, and the like.
In the third embodiment, an InAlGaN-HEMT is provided with a spacer layer 2c of AlGaN and a barrier layer 2d of InAlGaN that are formed by appropriately adjusting an Al composition and an In composition, so as to reduce gate leakage current while reducing sheet resistance.
The InAlGaN-HEMT according to the first to third embodiments described above is applied to a so-called discrete package. In this discrete package, the above-described chip of InAlGaN-HEMT is mounted. Hereinafter, a discrete package of an InAlGaN-HEMT chip (hereinafter referred to as HEMT chip) according to the first to third embodiments will be exemplified.
In order to fabricate a discrete package, first, the HEMT chip 20 is fixed to a lead frame 32 using a die attach agent 31 such as solder. A drain lead 32a is integrally formed with the lead frame 32, and a gate lead 32b and a source lead 32c are arranged separately from the lead frame 32.
Subsequently, the drain pad 21 and the drain lead 32a, the gate pad 22 and the gate lead 32b, and the source pad 23 and the source lead 32c are electrically connected by bonding using an Al wire 33. Thereafter, using the mold resin 34, the HEMT chip 20 is resin-sealed by a transfer molding method, and the lead frame 32 is cut off. Thus, a discrete package is formed.
In a fourth embodiment, a PFC (Power Factor Correction) circuit including one type of InAlGaN-HEMT selected from the first to third embodiments is disclosed.
The PFC circuit 40 includes a switch element (transistor) 41, a diode 42, a choke coil 43, capacitors 44 and 45, a diode bridge 46, and an alternating current power supply (AC) 47. One type of InAlGaN-HEMT selected from the first to third embodiments is applied to the switch element 41.
In the PFC circuit 40, a drain electrode of the switch element 41, an anode terminal of the diode 42, and one terminal of the choke coil 43 are connected. A source electrode of the switch element 41 is connected to one terminal of the capacitor 44 and one terminal of the capacitor 45. The other terminal of the capacitor 44 is connected to the other terminal of the choke coil 43. The other terminal of the capacitor 45 is connected to a cathode terminal of the diode 42. The AC 47 is connected between both terminals of the capacitor 44 via the diode bridge 46. A DC power supply (DC) is connected between both terminals of the capacitor 45.
In the fourth embodiment, an InAlGaN-HEMT is provided with a spacer layer 2c of AlGaN and a barrier layer 2d of InAlGaN that are formed by appropriately adjusting an Al composition and an In composition, such that the InAlGaN-HEMT capable of reducing gate leakage current while reducing sheet resistance is applied to the PFC circuit 40. As a result, a highly reliable PFC circuit 40 is provided.
In a fifth embodiment, a power supply including one type of InAlGaN-HEMT selected from the first to third embodiments is disclosed.
The power supply device according to the fifth embodiment is configured to include a high voltage primary circuit 51, a low voltage secondary circuit 52, and a transformer 53 disposed between the primary circuit 51 and the secondary circuit 52. The primary circuit 51 has the PFC circuit 40 according to the fourth embodiment and an inverter circuit, for example, a full bridge inverter circuit 50, connected to both terminals of the capacitor 45 of the PFC circuit 40. The full bridge inverter circuit 50 includes multiple (four in this case) switch elements 54a, 54b, 54c, and 54d. The secondary circuit 52 includes multiple (three in this case) switch elements 55a, 55b, and 55c.
In the fifth embodiment, as with the switch element 41 of the PFC circuit 40 constituting the primary circuit 51, the switch elements 54a, 54b, 54c, and 54d of the full bridge inverter circuit 50 are one type of InAlGaN-HEMT selected from the first to third embodiments. In contrast, the switch elements 55a, 55b, and 55c of the secondary circuit 52 are ordinary silicon-based MIS-FETs.
In the fifth embodiment, an InAlGaN-HEMT is provided with a spacer layer 2c of AlGaN and a barrier layer 2d of InAlGaN that are formed by appropriately adjusting an Al composition and an In composition, such that the InAlGaN-HEMT capable of reducing gate leakage current while reducing sheet resistance is applied to the primary circuit 51 acting as a high voltage circuit. As a result, a highly reliable and powerful power supply device is provided.
In a sixth embodiment, a high-frequency amplifier including one type of InAlGaN-HEMT selected from the first to third embodiments is disclosed.
The high-frequency amplifier according to the present embodiment includes a digital predistortion circuit 61, mixers 62a and 62b, and a power amplifier 63. The digital predistortion circuit 61 is configured to compensate for nonlinear distortion of an input signal. The mixer 62a mixes an input signal whose nonlinear distortion is compensated with an AC signal. The power amplifier 63 is configured to amplify the input signal mixed with the AC signal and to include one type of InAlGaN-HEMT selected from the first to third embodiments. In
In the sixth embodiment, an InAlGaN-HEMT is provided with a spacer layer 2c of AlGaN and a barrier layer 2d of InAlGaN that are formed by appropriately adjusting an Al composition and an In composition, such that the InAlGaN-HEMT capable of reducing gate leakage current while reducing sheet resistance is applied to a high-frequency amplifier. As a result, a highly reliable high-frequency amplifier with high withstand voltage is provided.
According to an aspect of an embodiment, a power supply device includes
In the power supply device, the high-voltage circuit includes a PFC circuit, and the transistor is a first switch element provided in the PFC circuit.
In the power supply device, the high-voltage circuit further includes an inverter circuit connected to the PFC circuit, and the transistor is a second switch element provided in the inverter circuit.
According to an aspect of the embodiments, a compound semiconductor device capable of reducing a leakage current while reducing sheet resistance is provided.
All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Number | Date | Country | Kind |
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2018-002897 | Jan 2018 | JP | national |
Number | Name | Date | Kind |
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20100289029 | Ichimura et al. | Nov 2010 | A1 |
20130075751 | Imanishi | Mar 2013 | A1 |
20140361337 | Sugiyama et al. | Dec 2014 | A1 |
20150303291 | Makiyama | Oct 2015 | A1 |
20160359032 | Kotani et al. | Dec 2016 | A1 |
Number | Date | Country |
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2010-267658 | Nov 2010 | JP |
WO2013125126 | Aug 2013 | JP |
2016-162889 | Sep 2016 | JP |
2016-225578 | Dec 2016 | JP |
Number | Date | Country | |
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20190214494 A1 | Jul 2019 | US |