Patent Grant
10141435
The invention relates to a semiconductor electronic device primarily used for high-power and/or high-frequency electric/electronic circuit. More specifically, the invention relates to transistors formed of group III nitride semiconductor.
(Note: This patent application refers several publications and patents as indicated with numbers within brackets, e.g., [x]. A list of these publications and patents can be found in the section entitled “References.”)
Gallium nitride (GaN) and its related group III nitride alloys are the key semiconductor material for various electronic devices such as power switching transistors. Despite the fact that the maximum performance of GaN theoretically predicted with Baliga's Figure of Merit (BFOM) exceeds that of silicon carbide (SiC) by approximately 5-fold, the lack of low-cost and low-defect GaN substrates impedes development of GaN-based power switching transistors having their full potential. Currently, the majority of GaN-based devices are fabricated using a group III nitride film grown heteroepitaxially on a heterogeneous substrate, such as silicon, SiC and sapphire. However, heteroepitaxial growth of group III nitride results in highly defected or even cracked films. Typical defects in group III nitride heteroepitaxial films are threading dislocations at the level of 109 cm−2 along the growth direction. Because threading dislocations and/or cracks propagate vertically through a substrate, these defects can become current leakage paths when high-voltage is applied vertically (i.e. along the substrate's growth direction, typically described as the substrate's thickness).
Therefore, at this moment, GaN-based electronic devices are practically limited to horizontal devices such as high-electron mobility transistors (HEMT), which utilize current flow along the lateral direction near a substrate's major surface. Since the electric current passes through a thin film in such horizontal devices, a horizontal device requires a large major-surface area to realize high-current (i.e. high-power) devices. In addition, all contacts are located on one side of the device, which causes device size to be larger than a vertical configuration. Due to these limitations, it is quite challenging to attain high-power devices in horizontal configuration of group III nitride semiconductors.
To overcome the issues in horizontal group III nitride devices, people have started to develop vertical type electronic devices using GaN substrates. Vertical high-power switching devices require normally-off operation, low-series resistance, high-breakdown voltage, fast switching speed, high efficiency and low cost. However, people have not demonstrated viable vertical high-power transistors using group III-nitride semiconductors due to many technical challenges such as difficulties in obtaining low-cost, low-defect substrates, growing high-purity drift layers with accurate control of carrier concentration, and/or fabricating high-quality buried portion of group III-nitride crystals for controlling current paths. To achieve commercially viable high-power vertical devices with group III-nitride semiconductors, a selection of substrate, design of device structures and a selection of fabrication method must be carefully considered.
The present invention provides a vertical-type electronic device having a group III nitride substrate. The present invention also provides various methods of forming an electronic device.
In one embodiment, a vertical-type electronic device has a GaN substrate or other substrate such as silicon having high-electron concentration (e.g. higher than about 5×1018 cm−3) and low dislocation density (e.g. less than 5×105 cm−2). This vertical electronic device in which the source and drain are typically but not exclusively on opposite sides of the substrate has low series resistance and high reliability compared to the typical horizontal electronic device. The drift layer of the device may be fabricated to have an electron concentration of e.g. less than about 5×1016 cm−3. Also, the concentration of carbon in the drift layer is optionally reduced through selection of fabrication method and conditions as explained in more detail below.
To inject electrons into the drift layer so that the device can turn on, p-type contact pads and optionally n-type contact pads are attached to the same side of the drift layer. The p-type contact pads and n-type contact pads are not attached together directly.
The vertical-type electronic device can be configured as a power diode by forming p-type and backside contacts but not n-type contact pads.
The vertical-type electronic device can be configured as a transistor by forming p-type, n-type, and backside contacts on the group III nitride substrate. The backside contact is the drain of the transistor or transistors, the Ohmic contacts on the n-type contact pads are each a source for their respective transistors, and the Ohmic contacts on the p-type contact pads are each a gate for their respective transistors.
The electron concentration in the drift layer is designed to be low enough to prevent current flow from drain to source under zero bias between the source and drain, which achieves normally-off operation. Under forward bias between the source and gate, holes are injected from the p-type contact pads (gate) to the drift layer and electrons are injected from the n-type contact pads (source) to the drift layer. The injected electrons drift toward the drain so that the current flows from drain to source. To optimize the performance of the device, the configuration of the contact pads, carrier concentrations of each layer/portion, alloy compositions of each layer/portion and impurity concentrations of each layer/portion are carefully designed as described more fully below.
In still further examples, the invention provides a vertical electronic device comprising an n-type contact pad, a p-type contact pad, a drift layer having a thickness, a drain, and a substrate. The drift layer is positioned between the n-type contact pad and the drain so that an electrical current flows from the n-type contact pad through the thickness of the drift layer and to the drain. The n-type contact pad is adjacent to the p-type contact pad, and the n-type contact pad and the p-type contact pad are positioned sufficiently closely to one another on the substrate so that a depletion region in the drift layer created by the p-type contact pad prevents current flow from the n-type contact pad on the drift layer to the drain when no voltage is applied between the n-type contact pad and the p-type contact pad. This configuration prevents current leakage in a normally-off transistor designed to handle high power switching.
Any of the electronic devices above can be configured with the drain on the opposite side of the substrate from the n-type contact pad, the p-type contact pad, and the drift layer or on the same side of the substrate as the n-type contact pad, the p-type contact pad, and the drift layer.
The p-type contact pad in any device above may have a bandgap that is larger than a bandgap of the drift layer.
Examples of what are disclosed include the following:
(1) An electronic device having a substrate, a drift layer, and a p-type contact pad, where the substrate has (a) a dislocation density less than 5×105 cm−2 and (b) an electron concentration higher than 5×1018 cm−3; the drift layer has an electron concentration lower than 5×1016 cm−3; and the p-type contact pad has a hole concentration higher than 1×1017 cm−3. This electronic device may have the p-type contact pad and an n-type contact pad positioned sufficiently close to one another on the substrate so that a depletion region in the drift layer created by the p-type contact pad prevents current flow from the n-type contact pad on the drift layer to the Ohmic contact when no voltage is applied between the n-type contact pad and the p-type contact pad. The p-type contact pad of this electronic device may, alternatively to the positioning of the p-type and n-type contact pads or additionally to it, have a bandgap that is larger than a bandgap of the drift layer. A substrate of Ga1-x1-y1Alx1Iny1N (0≤x1≤1, 0≤y1≤1) (particularly GaN) or other substrate such as sapphire or silicon may be used in the device.
(2) An electronic device as in (1) above, where the p-type contact pad has a hydrogen concentration less than one hundredth of a hydrogen concentration of the substrate.
(3) An electronic device having (a) a semi-insulating substrate of Ga1-x1-y1Alx1Iny1N (0≤x1≤1, 0≤y1≤1) (e.g. with resistivity of at least 1 kΩ cm) having a dislocation density less than 5×105 cm−2; (b) a drain layer of Ga1-x5-y5Alx5Iny5N (0≤x5≤1, 0≤y5≤1) and a drift layer of Ga1-x2-y2Alx2Iny2N (0≤x2≤1, 0≤y2≤1) on the same side of the substrate; (c) a p-type contact pad of Ga1-x3-y3Alx3Iny3N (0≤x3≤1, 0≤y3≤1) in electrical contact with the drift layer; (d) an Ohmic contact in electrical contact with the p-type contact pad; and (e) an n-type contact pad of Ga1-x4-y4Alx4Iny4N (0≤x4≤1, 0≤y4≤1) in electrical contact with the drift layer and spaced apart from the p-type contact pad.
(4) A method of fabricating an electronic device that comprises;
The first or lower drift layer of any device or method herein may be e.g. Ga1-x2-y2Alx2Iny2N (0≤x2≤1, 0≤y2≤1), and the second drift layer may be Ga1-x6-y6Alx6Iny6N (0≤x6≤1, 0≤y6≤1). x2 and x6 may be the same value or may be different, and y2 and y6 may be the same value or may be different.
These devices and methods and others are readily perceived by those in the field from the disclosure herein.
Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
In the figures each number represents the following:
1. Homoepitaxial substrate
2. Backside contact
3. Drift layer
3
a. A depletion region created inside the drift layer
4. p-type contact pads
5. Ohmic contact to the p-type contact pads
6. n-type contact pads
7. Ohmic contact to the n-type contact pads
10. A region for drift layer
10
a. A depletion region created inside the drift layer by the p-type contact pad
11. A region for p-type contact pads
12. A region for n-type contact pads
13. The arrow indicates a distance between the p-type contact pad and the n-type contact pad.
10. A region for drift layer
11. A region for p-type contact pads
12. A region for n-type contact pads
13. The arrow indicates a distance between the p-type contact pad and the n-type contact pad.
In the figure each number represents the following:
1. Homoepitaxial substrate
2. Backside contact
3. Drift layer
3
b. Etched holes created in the drift layer
4. p-type contact pads
5. Ohmic contact to the p-type contact pads
6. n-type contact pads
7. Ohmic contact to the n-type contact pads
8. A mask to create etched holes in the drift layer
9. A mask to create n-type contact pads.
In the figure each number represents the following:
1. Homoepitaxial substrate
2. Backside contact
3. Drift layer
3
b. Etched holes created in the drift layer
3
c. Regrown drift layer
4. p-type contact pads
5. Ohmic contact to the p-type contact pads
6. n-type contact pads
7. Ohmic contact to the n-type contact pads
8. A mask to create etched holes in the drift layer
9. A mask to create n-type contact pads.
In the figures each number represents the following:
1. Homoepitaxial substrate
3. Drift layer
3
a. A depletion region created inside the drift layer
4. p-type contact pads
5. Ohmic contact to the p-type contact pads
6. n-type contact pads
7. Ohmic contact to the n-type contact pads
10. Drain layer
11. Ohmic contact to drain layer.
In the figure each number represents the following:
1. Homoepitaxial substrate
3. Drift layer
3
b. Etched holes created in the drift layer
3
c. Regrown drift layer
4. p-type contact pads
5. Ohmic contact to the p-type contact pads
6. n-type contact pads
7. Ohmic contact to the n-type contact pads
8. A mask to create etched holes in the drift layer
9. A mask to create n-type contact pads.
10. Drain layer
11. Ohmic contact to drain layer.
To realize a GaN-based electronic device with a vertical configuration, a homoepitaxial substrate 1, such as GaN, AlN or generally Ga1-x1-y1Alx1Iny1N (0≤x1≤1, 0≤y1≤1) may be used. The substrate preferably has a dislocation density less than 5×105 cm−2. Among many choices, highly conductive n-type GaN substrates are the best choice to minimize series resistance (i.e. on-resistance). Preferably the substrate has an electron concentration greater than 5×1018 cm−3 and more preferably greater than about 2×1019 cm−3. The substrate may or may not contain sodium or other element that is used as a mineralizer in ammonothermal growth.
Currently, majority of commercially available GaN substrates are produced by a method called hydride vapor phase epitaxy (HVPE). HVPE is a vapor phase method, which has a difficulty in reducing defect density less than 5×105 cm−2. Furthermore, the manufacturing process involves removal of the substrate after growing a thick (more than 0.1 mm) GaN layer, which is quite labor intensive and low yield. In addition, obtaining higher electron concentration than about 2×1019 cm−3 is not commonly available possibly due to limited incorporation of silicon into GaN. Therefore, although a vertical device in the current invention can be fabricated using HVPE-made GaN substrates, it is more preferable to use GaN produced by another method.
To obtain low-cost, low-defect, highly conductive GaN substrates of which density of dislocations and/or grain boundaries is less than about 5×105 cm−2, a new method called ammonothermal growth has been developed [refs. 1-6]. The ammonothermal method is one of the bulk growth methods of group III nitride crystals using supercritical ammonia.
Growth rate of crystals in supercritical ammonia is typically low. To grow bulk GaN crystals at a practically useful speed for producing substrates, a chemical additive called a mineralizer is added to the supercritical ammonia. A mineralizer is typically an element or a compound of group I elements or group VII elements, such as potassium, sodium, lithium, potassium amide, sodium amide, lithium amide, ammonium fluoride, ammonium chloride, ammonium bromide, ammonium iodide and gallium iodide. Sometimes more than two kinds of mineralizers are mixed to attain a good growth condition.
Although most of the mineralizers are interchangeable, sodium is the most favorable mineralizer in terms of growth rate, purity and handling. By ammonothermal growth using sodium, GaN substrates having dislocation density less than about 5×105 cm−2 can be produced. Low defect of GaN substrate is beneficial to attaining high breakdown voltage.
GaN substrates grown by ammonothermal growth contain high concentration of oxygen which attains electron concentration of the substrate higher than about 5×1018 cm−3 or more preferably about 2×1019 cm−3. This feature is desired to minimize series resistance. For the above-mentioned reasons, the vertical electronic devices of the current invention preferably use GaN substrates produced by the ammonothermal method. Optionally the substrate can be an alloy of group III nitride expressed as Ga1-x1-y1Alx1Iny1N (0≤x1≤1, 0≤y1≤1).
The homoepitaxial substrate 1 may be formed by growing one or more bulk crystals of Ga1-x1-y1Alx1Iny1N (0≤x1≤1, 0≤y1≤1) using the ammonothermal method. The crystals may be grown under acidic, basic, or neutral conditions in a high-pressure reactor as known in the art or as described in any of the generally-related patent applications listed above.
An electron donor such as oxygen and/or hydrogen is incorporated into the bulk crystal during ammonothermal growth by introducing enough oxygen and/or hydrogen into the growth chamber of the high-pressure reactor as nutrient, mineralizer, seed, ammonia, and any other desired materials are placed in the reactor. Oxygen and hydrogen can be introduced into the chamber from air by evacuating the reactor of ambient air after loading the raw materials but leaving a sufficient amount of air in the reactor to provide the desired level of oxygen and moisture in the chamber.
Oxygen and hydrogen can also or alternatively be introduced into the reactor chamber in the form of an oxide or hydride of e.g. an element used in the mineralizer. For instance, sodium and/or potassium may be used as the mineralizer, and often the sodium and/or potassium added to the reactor has an amount that has oxidized or moistened. The mineralizer may be oxidized sufficiently in e.g. an oxygen-containing environment prior to and/or during insertion into the reactor so that the mineralizer provides a sufficient amount of oxygen/hydrogen and provides the specified level of oxygen/hydrogen concentration in the bulk crystal.
The amount of oxygen and/or hydrogen added to the reactor by any of the methods above is sufficient to provide a substrate with an oxygen and/or hydrogen concentration that is preferably greater than about 5×1018 cm−3 and more preferably greater than about 2×1019 cm−3.
Although the majority of conventional group III nitride electronic devices are fabricated using metalorganic chemical vapor deposition (MOCVD), a drift layer grown by MOCVD tends to show lower breakdown voltage than the theoretical value. We have considered the possible reasons for this problem and have reasoned that carbon impurity in the drift layer during device fabrication could cause the decrease of the breakdown voltage.
In MOCVD, metalorganic precursors such as trimethylgallium contain a high amount of carbon, which is incorporated in the grown film. Therefore, the drift layer 3 of the group III nitride electronic device in the current invention is preferably formed using a growth method which does not utilize a carbon-containing source or precursor so that the drift layer contains little, if any, carbon. The growth method is preferably HVPE. Other methods such as molecular beam epitaxy (MBE) can be used.
The drift layer 3 may be formed by HVPE on the first side of the wafer so that the impurity level and the electron concentration in the drift layer 3 are low. The first side of the homoepitaxial substrate 1 is preferably Ga polar c-plane. However, since the drift layer is typically thick (typically 5 to 15 microns), using the on-axis c-plane substrate often creates a rough surface (possibly due to three-dimensional growth). To avoid potential three-dimensional growth and achieve a smooth surface after the drift layer growth, the electronic device of the current invention preferably uses a substrate having a Ga-polar c-plane major surface with intentional miscut between 0.2 and 0.6 degree along m-direction of the crystal. The drift layer may be formed of Ga1-x2-y2Alx2Iny2N (0≤x2≤1, 0≤y2≤1).
The growth conditions of the drift layer can be adjusted so that no dislocations are newly generated at the interface between the substrate and the drift layer. The adjustments may include one or more of adjusting growth temperature, temperature ramping profile, and timing of introducing reaction gas or source, as known by a person of ordinary skill.
The dislocation density of the Ga1-x2-y2Alx2Iny2N (0≤x2≤1, 0≤y2≤1) drift layer can therefore be near or at the same level of that of the substrate (i.e. preferably less than about 5×105 cm−2).
In addition, HVPE can provide the drift layer with a lower impurity concentration than that of the ammonothermal substrate. Therefore, the electron concentration of the drift layer 3 can preferably be lower than about 5×1016 cm−3 or more preferably lower than about 1×1016 cm−3.
The carbon concentration of the drift layer is preferably less than about 1×1016 cm−3. The high structural quality and high purity nature of the drift layer enables faster electron mobility (i.e. lower series resistance) and higher breakdown voltage.
The above-mentioned combination of the layer structure and the corresponding preferred fabrication methods (i.e. ammonothermal method for the substrates and HVPE method for the drift layer) for the structure are derived from the design concept of the electronic power devices in the current invention. However, these conditions are a part of other design factors.
To realize high-performance high-power devices with normally-off operation, low-series resistance, high-breakdown voltage, fast switching speed, high efficiency and low cost, the device preferably also incorporates the following components.
A contact 2 (preferably Ohmic) can be created on the backside of the substrate (i.e. opposite side to the drift layer, as illustrated in
At least one p-type contact pad of Ga1-x3-y3Alx3Iny3N (0≤x3≤1, 0≤y3≤1) (feature 4 of
In conventional vertical type electronic devices of group III nitride, p-type contact pads are typically formed by selective etching of the drift layer followed by selective MOCVD growth using a silicon dioxide mask. However, the fabricated electronic devices in the conventional methods tend to show high level of leakage current as well as low breakdown voltage under reverse bias.
We considered the possible reasons for this problem and reasoned that high concentration of hydrogen in the p-type contact pads is a possible cause. Since MOCVD growth uses ammonia as well as hydrogen carrier gases, the group III nitride film grown by MOCVD contains high level of hydrogen (higher than 1×1017 cm−3). Also, ammonia and/or hydrogen in MOCVD environment may etch the silicon dioxide mask to emit Si and/or O into the growth environment, which in turn will be incorporated into the p-type contact pads.
Therefore, in one embodiment of the current invention, the p-type contact pads of Ga1-x3-y3Alx3Iny3N (0≤x3≤1, 0≤y3≤1) 4 are formed by a method which does not use ammonia or hydrogen as a carrier gas so that the p-type contact pads contain little hydrogen. As a result, the hydrogen concentration of the p-type contact pads 4 is preferably less than one hundredth of that in the substrate and less than one tenth of that in the drift layer. The low hydrogen feature of the p-type contact pads may consequently help avoid leakage current and breakdown of the transistor.
Another possible reason for the low breakdown voltage is that MOCVD regrowth process using a silicon dioxide mask causes incorporation of Si and/or O into the p-type contact pads probably due to high growth temperature (approximately 1050° C.). Therefore in one embodiment of the current invention, the p-type contact pads of Ga1-x3-y3Alx3Iny3N (0≤x3≤1, 0≤y3≤1) 4 are formed at or below 800° C. to avoid incorporating Si and/or O into the pads. With low temperature deposition, the silicon concentration in the p-type contact pads are preferably suppressed at or below 1×1018 cm−3.
The p-type contact pads may be formed using e.g. pulsed laser deposition (PLD) or molecular beam epitaxy (MBE). PLD provides high selectivity against a mask used to define features (e.g. silicon dioxide mask), and PLD also provides high coverage on the etched trenches.
Additionally, the hole concentration in the p-type contact pads can be higher than about 1×1017 cm−3 without p-type activation annealing in the present method. PLD or MBE can consequently be used in the preferred method without the step of annealing p-type material to provide a desired hole concentration.
p-type contact pads having both low hydrogen concentration and high hole concentration help provide an electronic device with high breakdown voltage and high efficiency.
The impurity to obtain p-type conduction may preferably be Mg although Be can also be used. The Mg may be supplied separately during deposition process or may be pre-mixed in the group III source.
Similarly, the n-type contact pads of Ga1-x4-y4Alx4Iny4N (0≤x4≤1, 0≤y4≤1) 6 may be formed by PLD or MBE. The impurity to obtain n-type conduction may preferably be Ge although Si can also be used. The germanium concentration of the n-type contact pads 6 is preferably more than about 1×1018 cm−3 and hydrogen concentration of the n-type contact pad is preferably less than about 7×1016 cm−3. The electron concentration of the n-type contact pads 6 is preferably higher than about 1×1018 cm−3. With these parameters, electrons are efficiently injected to the drift layer under transistor operation.
If the electronic device has p-type contact pads 4 as depicted in
Alternatively, the device structure in
The n-type contact pads are surrounded by the p-type contact pads when viewing the device from above the top surface as in e.g.
In either case, the separation width is preferably set narrow enough so that the depletion regions created by the p-type contact pad entirely cover the area under the n-type contact pads. This feature is preferable when making normally-off devices.
Both p-type contact pads 4 and n-type contact pads 6 are on the same side of the drift layer. The p-type contact pads 4 and n-type contact pads 6 may therefore be separate and do not directly touch one another.
The p-type contact pads 4 and n-type contact pads 6 may also be separated from one another vertically, as illustrated in
One highly preferable feature of the electronic device of the current invention is that the bandgap of the p-type contact pads 4 may be larger than the bandgap of the drift layer 3. When the forward bias is applied between the p-type contact pads 4 (gate) and the n-type contact pads 6 (source), electrons are injected from the n-type contact pads 6 to the drift layer 3 and holes are injected from the p-type pad 4 to the drift layer 3. The electronic device may have two distinct properties by setting the bandgap of the p-type contact pads 4 larger than the bandgap of the drift layer 3: (1) the electrons in the drift layer cannot be injected into the p-type contact pads 4, and (2) the hole injection current from the p-type contact pad 4 to the drift layer 3 may become more than about 10,000 times higher than the electron injection current from the drift layer 3.
For example, when the bandgap of the p-type contact pads 4 is larger than the bandgap of the drift layer 3 by approximately 0.3 eV, the hole injection current from the p-type contact pad 4 to the drift layer 3 may become more than about 100,000 times higher than the electron injection current from the drift layer 3 to the p-type contact pad 4. If the bandgap difference is 0.25 eV, the hole injection current from the p-type contact pad 4 to the drift layer 3 may become more than about 15,000 times higher than the electron injection current from the drift layer 3 to the p-type contact pad 4. This produces highly-efficient transistors.
The bandgap of the drift layer and pad can be easily controlled by adjusting alloy compositions of the group III nitride. For example, the GaN may be used for the substrate 2, the drift layer 3, and n-type contact pads 6 and Ga0.89Al0.11N may be used for the p-type contact pads 4. In this case, the difference in the bandgap between the p-type contact pad and the drift layer becomes about 0.3 eV. Alternatively Ga0.91Al0.09N may be used for p-type contact. In this case the difference in the bandgap between the p-type contact pad and the drift layer becomes about 0.25 eV. The relationship between the bandgap and alloy composition are well known to the person of the ordinary skill. Consequently, the person of ordinary skill can provide other devices with a desired difference in bandgap using the guidance above and their background knowledge and experience.
An Ohmic contact to the p-type contact pads 5 and an Ohmic contact to the n-type contact pads 7 can each be formed by a conventional metallization method similar to the metallization method used to form backside Ohmic contact 2. The Ohmic contact 5 to the p-type contact pads may be Ni/Au, and the Ohmic contact 7 to the n-type contact pads 6 can be Ti/Al.
Then, a drift layer 3 of Ga1-x2-y2Alx2Iny2N (0≤x2≤1, 0≤y2≤1) is grown on the Ga polar surface of the substrate 1 preferably by HVPE (
To make trenches on the surface of the drift layer, a mask 8 (
After this trench formation, p-type contact pads of Ga1-x3-y3Alx3Iny3N (0≤x3≤1, 0≤y3≤1) (feature 4 of
If dry etching is used to form trenches, the etching reaction chamber is preferably connected to the deposition chamber of the p-type contact pads so that the devices can be transferred without exposing them to the air.
The amount of Al, Ga, and In may be adjusted so that the bandgap of the p-type contact pads becomes larger than that of the drift layer. In the PLD, the group III sources (i.e. Al, Ga, In) can be mixed together or can be separate. Also, Mg or Be can be mixed to the group III sources or can be separate. After the formation process of the p-type contact pads, the masks 8 are removed from the surface (
To form n-type contact pads, another mask 9 (
Finally,
The following examples supplement the discussion above and are provided to illustrate certain specific embodiments of the invention. The examples therefore provide the person with ordinary skill with guidance on how to carry out the invention described above.
A bulk crystal of GaN was grown with the basic ammonothermal method in a pressure reactor having internal volume of 127 cc using polycrystalline GaN (15 g) as a nutrient, supercritical ammonia (53% fill to the reactor volume) as a solvent, and sodium (5 mol % to ammonia) as a mineralizer. The growth temperature was between 500 to 600° C., and growth extended to 181 days. A bulk crystal of GaN was grown on a c-plane GaN seed crystal. The bulk crystal was approximately 10 mm2 thick. Then the crystal was sliced into wafers using a multiple wire saw. Nine wafers approximately 1 mm thick each were sliced out of one bulk GaN crystal. These wafers were ground to make c-plane miscut to be about 0.4°. Then, they were lapped with diamond slurry and polished using CMP. The defect density of one of these wafers was characterized with X-ray topography. The dislocation density was about 4×104 cm−2. The electron concentration was about 2.5×1019 cm−3 due to incorporation of oxygen and/or hydrogen introduced into the reactor from air retained in the reactor as it was prepared for growth, from oxygen and/or hydrogen deliberately added to the reactor, and/or from oxygen and/or hydrogen that accompanied mineralizer.
Using GaN wafers prepared by the ammonothermal growth in the Example 2, GaN drift layers were grown by HVPE. In each run, one wafer of approximately 10 mm×10 mm (L×W) in size was used. Inside the HVPE reactor, hydrogen chloride gas was passed over heated Ga and then mixed with ammonia prior to encountering the heated wafer. The temperature of the Ga was in the range of 800 to 1000° C., and the temperature of the wafer was in the range of 900 to 1150° C. In this example, GaN having a thickness of about 10 microns was grown on the Ga-polar surface of ammonothermal c-plane GaN wafers. The growth rate was in the range of 50 to 400 microns per hour. Using Ti/Al for the backside cathode contact and Ni/Au for the front side anode contact, I-V characteristics of the drift layer were measured. The I-V characteristics did not show conductance of current for both forward and reverse bias direction. Measuring C-V characteristic showed carrier concentration was less than about 1×1016 cm−3. The carbon concentration in the layer evaluated by secondary mass spectroscopy (SIMS) was about 6×1015 cm−3.
Transistors may be formed using the GaN drift layer fabricated on the substrate of Example 2. First, a SiO2 layer of about 2 microns is deposited with plasma CVD using SiH4 gas and oxygen gas. Using a conventional photolithography technique, a mask pattern is created and the drift layer is etched to make trenches by ICP plasma etching using Cl2 gas. The trench width is about 10 microns and trench depth is about 1 microns. Without exposing the etched wafer to air, the wafer is transferred to PLD chamber to form p-type contact pads. Using the same patterned SiO2 mask, AlGaN p-type contact pads with Mg doping are deposited by PLD at 600° C. using premixed Ga, Al and Mg melt. The thickness of the p-type contact pads is about 1 microns, and the lateral separations between p-type contact pads are about 2 microns. The width of the pad is about 10 microns. The Mg concentration is about 1×1020 cm−3 and hole concentration is about 1×1017 cm−3. Since hydrogen is minimized in the reaction ambient, the hydrogen concentration in the p-type contact pad is below the detection limit of SIMS (less than 7×1016 cm−3). The aluminum mole fraction in AlGaN is about 11%, which makes the bandgap of the AlGaN p-type contact pads larger than that of the GaN drift layer by about 0.3 eV. The hole injection current from the p-type contact pads to the drift layer is calculated to be about 100,000 times higher than the electron injection current from the drift layer to the p-type contact pads.
Then another layer of SiO2 mask is deposited and patterned to form n-type contact pads. Since the photolithography process is conducted outside of vacuum system, the substrate is exposed to air. After patterning of the SiO2 mask, the substrate is loaded to a plasma cleaning chamber, and the top surface of the drift layer is cleaned by etching a small amount from the layer's top. The removed thickness is less than about 5 nm in this example. Then, the substrate is transferred to the PLD deposition system to form n-type contact pads of GaN using premixed Ga and Ge. The n-type contact pads are formed right in the middle of the p-type contact pads. The pad width is about 1 microns and the thickness is about 0.5 microns. The Ge concentration is about 5×1019 cm−3 and the electron concentration is about 1×1019 cm−3. Using the same mask, Ti/Al Ohmic contacts are formed on top of the n-type contact pads.
Finally, Ni/Au p-type contact pads are formed using lift-off process of photo resist and backside Ti/Al contact is formed.
The transistor withstands source-drain voltage of about 1500 V, and the series resistance under forward bias between source and gate is about 1 mΩ cm.
Transistors may be formed using the GaN substrates in Example 1. The carrier concentration of the GaN substrate is 2×1019 cm−3. A first drift layer of undoped GaN having a thickness of 10 microns is fabricated on the substrate by MOCVD followed by successive growth of a p-GaN layer having a thickness of 0.5 microns by MOCVD in the same epitaxial deposition device (
Then, parts of the p-GaN is etched down to the drift layer using a conventional photolithography and dry etching such as reactive ion etching (RIE) to form p-type contact pads (
The lateral size of the etched region is about 2 microns. Since the depletion region extends to 1.4 microns, the depletion region in the regrown undoped GaN completely fill the space, preventing current flow under zero bias condition between the p-type contact pad and the n-type contact pad. This enables normally-off operation of the transistor.
A transistor may be formed using a semi-insulating GaN substrate.
After depositing the p-GaN layer 4, mask 8 is formed using conventional photolithography, and regions 3b of the p-GaN are etched down to the drift layer using conventional dry etching such as reactive ion etching (RIE) to form p-type contact pads 4 of
The lateral size of the etched region is about 2 microns. Since the depletion region extends to 1.4 microns, the depletion region in the regrown undoped GaN completely fills the space beneath the n-type contact pads and, in this case, the p-type contact pads as well, preventing current flow under zero bias condition between the p-type contact pad and the n-type contact pad. This enables normally-off operation of the transistor.
The following is therefore disclosed by way of example and not by way of limitation in view of the discussion above:
Although the preferred embodiment describes GaN substrates, the substrate can be group III nitride alloys of various composition, such as AlN, AlGaN, InN, InGaN, or GaAlInN. The scope of the invention includes these substrates.
Although the preferred embodiment describes Ga-face c-plane GaN, other orientations such as N-face c-plane, a-face, m-face, and various semipolar surface can also be used. In addition, the surface can be slightly miscut (off-sliced) from these orientations. The scope of the invention includes these orientations and miscut. In particular, usage of N-face c-plane GaN, nonpolar a-face and m-face, semipolar planes may modulate the energy band structure of the electronic devices, and thus could control the turn-on voltage.
Although the preferred embodiment describes HVPE or MOCVD as a vapor phase epitaxy, other methods such as MBE, reactive sputtering, and ion-beam deposition can be used for growing the active layer and/or the transition layer in this invention.
Although the preferred embodiment uses Ni/Au for p-type Ohmic contact and Ti/Al for n-type Ohmic contact, other materials such as In, ZnO, and W can be used.
The foregoing description of the preferred embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
The following references are incorporated by reference herein:
Each of the references above is incorporated by reference in its entirety as if put forth in full herein, and particularly with respect to description of methods of making using ammonothermal methods and using these gallium nitride substrates.
This application claims priority to U.S. Pat. App. 62/438,900 filed on Dec. 23, 2016 and entitled “ELECTRONIC DEVICE USING GROUP III NITRIDE SEMICONDUCTOR AND ITS FABRICATION METHOD”, inventors Tadao Hashimoto and Daisuke Ueda. This application is related to the following patent applications: PCT Patent Application Serial No. PCT/US2017/058775, by Tadao Hashimoto and Daisuke Ueda, entitled “ELECTRONIC DEVICE USING GROUP III NITRIDE SEMICONDUCTOR AND ITS FABRICATION METHOD”, filed on Oct. 27, 2017; PCT Utility Patent Application Serial No. US2005/024239, filed on Jul. 8, 2005, by Kenji Fujito, Tadao Hashimoto and Shuji Nakamura, entitled “METHOD FOR GROWING GROUP III-NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA USING AN AUTOCLAVE,”; U.S. Utility patent application Ser. No. 11/784,339, filed on Apr. 6, 2007, by Tadao Hashimoto, Makoto Saito, and Shuji Nakamura, entitled “METHOD FOR GROWING LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA AND LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS,”, which application claims the benefit under 35 U.S.C. Section 119(e) of U.S. Provisional Patent Application Ser. No. 60/790,310, filed on Apr. 7, 2006, by Tadao Hashimoto, Makoto Saito, and Shuji Nakamura, entitled “A METHOD FOR GROWING LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA AND LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS,”; U.S. Utility Patent Application Ser. No. 60/973,662, filed on Sep. 19, 2007, by Tadao Hashimoto and Shuji Nakamura, entitled “GALLIUM NITRIDE BULK CRYSTALS AND THEIR GROWTH METHOD,” and issued as U.S. Pat. Nos. 8,253,221 and 9,243,344; U.S. Utility patent application Ser. No. 11/977,661, filed on Oct. 25, 2007, by Tadao Hashimoto, entitled “METHOD FOR GROWING GROUP III-NITRIDE CRYSTALS IN A MIXTURE OF SUPERCRITICAL AMMONIA AND NITROGEN, AND GROUP III-NITRIDE CRYSTALS GROWN THEREBY,” and issued as U.S. Pat. No. 7,803,344; Allowed U.S. Utility patent application Ser. No. 12/392,960, filed on Feb. 25, 2009, by Tadao Hashimoto, Edward Letts, Masanori Ikari, entitled “METHOD FOR PRODUCING GROUP III-NITRIDE WAFERS AND GROUP III-NITRIDE WAFERS,”; U.S. Utility patent application Ser. No. 12/455,760, filed on Jun. 4, 2009, by Edward Letts, Tadao Hashimoto, Masanori Ikari, entitled “METHODS FOR PRODUCING IMPROVED CRYSTALLINITY GROUP III-NITRIDE CRYSTALS FROM INITIAL GROUP III-NITRIDE SEED BY AMMONOTHERMAL GROWTH,” and issued as U.S. Pat. No. 8,728,234; U.S. Utility patent application Ser. No. 12/455,683, filed on Jun. 4, 2009, by Tadao Hashimoto, Edward Letts, Masanori Ikari, entitled “HIGH-PRESSURE VESSEL FOR GROWING GROUP III NITRIDE CRYSTALS AND METHOD OF GROWING GROUP III NITRIDE CRYSTALS USING HIGH-PRESSURE VESSEL AND GROUP III NITRIDE CRYSTAL,” and issued as U.S. Pat. No. 8,236,237; U.S. Utility patent application Ser. No. 12/455,181, filed on Jun. 12, 2009, by Tadao Hashimoto, Masanori Ikari, Edward Letts, entitled “METHOD FOR TESTING III-NITRIDE WAFERS AND III-NITRIDE WAFERS WITH TEST DATA,” and issued as U.S. Pat. Nos. 8,357,243, 8,585,822, and 8,557,043; U.S. Utility patent application Ser. No. 12/580,849, filed on Oct. 16, 2009, by Tadao Hashimoto, Masanori Ikari, Edward Letts, entitled “REACTOR DESIGN FOR GROWING GROUP III NITRIDE CRYSTALS AND METHOD OF GROWING GROUP III NITRIDE CRYSTALS,”; U.S. Utility patent application Ser. No. 13/781,509, filed on Feb. 28, 2013, by Tadao Hashimoto, entitled “COMPOSITE SUBSTRATE OF GALLIUM NITRIDE AND METAL OXIDE,” and issued as U.S. Pat. Nos. 9,224,817 and 9,431,488; U.S. Utility patent application Ser. No. 13/781,543, filed on Feb. 28, 2013, by Tadao Hashimoto, Edward Letts, Sierra Hoff entitled “A BISMUTH-DOPED SEMI-INSULATING GROUP III NITRIDE WAFER,” and issued as U.S. Pat. Nos. 9,255,342 and 9,435,051; U.S. Utility patent application Ser. No. 13/833,443, filed on Mar. 15, 2013, by Tadao Hashimoto, Edward Letts, Sierra Hoff entitled “METHOD OF GROWING GROUP III NITRIDE CRYSTALS,” and issued as U.S. Pat. No. 9,518,340; U.S. Utility patent application Ser. No. 13/834,015, filed on Mar. 15, 2013, by Tadao Hashimoto, Edward Letts, Sierra Hoff entitled “METHOD OF GROWING GROUP III NITRIDE CRYSTALS,” and issued as U.S. Pat. No. 9,202,872; U.S. Utility patent application Ser. No. 13/834,871, filed on Mar. 15, 2013, by Tadao Hashimoto, Edward Letts, Sierra Hoff entitled “GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD,” and issued as U.S. Pat. No. 9,543,393; U.S. Utility patent application Ser. No. 13/835,636, filed on Mar. 15, 2013, by Tadao Hashimoto, Edward Letts, Sierra Hoff entitled “GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD,” and issued as U.S. Pat. No. 8,921,231; U.S. Utility patent application Ser. No. 13/798,530, filed on Mar. 13, 2013, by Tadao Hashimoto, entitled “GROUP III NITRIDE WAFERS AND FABRICATION METHOD AND TESTING METHOD,”; U.S. Utility patent application Ser. No. 14/329,730, filed on Jul. 23, 2014, by Tadao Hashimoto, entitled “ELECTRONIC DEVICE USING GROUP III NITRIDE SEMICONDUCTOR AND ITS FABRICATION METHOD,” and issued as U.S. Pat. Nos. 9,466,481, 9,685,327, 9,305,772, and 9,349,592; and all of the above patents and applications are incorporated by reference herein in their entirety as if put forth in full below.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6440823 | Vaudo | Aug 2002 | B1 |
| 6533874 | Vaudo | Mar 2003 | B1 |
| 6613143 | Melnik | Sep 2003 | B1 |
| 6656615 | Dwilinski et al. | Dec 2003 | B2 |
| 7078731 | D'Evelyn et al. | Jul 2006 | B2 |
| 7132730 | Dwilinski et al. | Nov 2006 | B2 |
| 7160388 | Dwilinski et al. | Jan 2007 | B2 |
| 7655090 | Marchand | Feb 2010 | B2 |
| 8795431 | Imai et al. | Aug 2014 | B2 |
| 9255342 | Hashimoto et al. | Feb 2016 | B2 |
| 9577143 | Shapovalov | Feb 2017 | B1 |
| 20070234946 | Hashimoto et al. | Oct 2007 | A1 |
| 20090092815 | Dmitriev | Apr 2009 | A1 |
| 20130032811 | Kizilyalli et al. | Feb 2013 | A1 |
| 20130126888 | Kizilyalli et al. | May 2013 | A1 |
| 20130161705 | Disney et al. | Jun 2013 | A1 |
| 20140054604 | Ritenour et al. | Feb 2014 | A1 |
| 20140191242 | Nie et al. | Jul 2014 | A1 |
| 20150060876 | Xing et al. | Mar 2015 | A1 |
| 20170125574 | Chowdhury | May 2017 | A1 |
| 20180182873 | Hashimoto et al. | Jun 2018 | A1 |
| 20180182881 | Hashimoto et al. | Jun 2018 | A1 |
| 20180182882 | Hashimoto et al. | Jun 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| WO2007008198 | Jan 2007 | WO |
| WO2007117689 | Oct 2007 | WO |
| WO2015200885 | Dec 2015 | WO |
| WO2018118220 | Jun 2018 | WO |
| Entry |
|---|
| Masami tachikawa et al., “Film thickness dependence of dislocation density reduction in GaAs-on-Si substates”, Applied Physics Letters, vol. 56 (5), Jan. 29, 1990, pp. 484-486. |
| U.S. Appl. No. 15/796,705 Office Action dated Apr. 6, 2018. |
| U.S. Appl. No. 15/796,708 Office Action dated Apr. 9, 2018. |
| PCT/US2017/058775 International Search Report and Written Opinion dated May 17, 2018, pp. 27. |
| U.S. Appl. No. 15/796,708 Amendment dated Jun. 28, 2018. |
| U.S. Appl. No. 15/796,705 Amendment dated Jun. 29, 2018. |
| U.S. Appl. No. 15/796,705 Notice of Allowability dated Sep. 26, 2018. |
| U.S. Appl. No. 15/796,708 Notice of Allowability dated Sep. 26, 2018. |
| Number | Date | Country | |
|---|---|---|---|
| 20180182872 A1 | Jun 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62438900 | Dec 2016 | US |
