Patent Grant
8462516
The present invention relates broadly to an interconnect structure, to an interconnect structure for interconnecting first and second components, to an interconnect structure for interconnecting a multiple component stack and a substrate, and to a method of fabricating an interconnect structure.
Bonded wires, solder bumps and metal pillars are common microstructures formed on micro devices which are usually fabricated on silicon wafers. Wire bonding is the earliest technique for interconnecting electronic devices. Thermosonic wire bonding is a commonly used technique. Conventional wire bonding allows Input/Output (I/O) pad bonding only on a chip perimeter near edges of a chip. Low profile and flexible long loop wire can be bonded across multiple chips and substrates. However, the trade-off in long wire interconnection is its high impedance and parasitic inductance and capacitance. Wire bonding is usually not suitable for high frequency and RF applications. Further, wire bonding over an active portion of a silicon chip may damage the delicate circuitry beneath it. This restriction limits the design for optimal power distribution and chip size shrinkage.
Flip-chip technology is an important development for the microelectronic industry. An optimized flip-chip device provides improvement in cost, reliability and performance over a wire-bonded device. The flip-chip device also has better electrical performance and lower impedance, inductance and capacitance. Aided by a self-alignment characteristic of solder, flip-chip packaging using solder bump has excellent yield. An area array interconnection format on flip-chip allows large number of I/Os to be distributed across the chip surface. This improves pitch spacing and power distribution. With no additional packaging material over the bare chip, the flip-chip has the smallest possible size. As the flip-chip array pitch decreases, the interconnect solder bump diameter on the flip-chip may decrease correspondingly.
One disadvantage for reducing a solder bump size is the increase in the volume ratio of the IMC to bulk solder in an interconnecting joint. A higher percentage of the IMC in the solder joint is undesirable as the IMC is brittle and the fatigue life of the solder joint can be reduced. Another disadvantage is the increase in current density as the solder bump size decreases. As current density increases, electromigration will become a reliability concern in package interconnection.
Unlike solder bump, copper (Cu) pillar does not collapse during reflow soldering. Pillars can be packed closer together, increasing the interconnection density. If plating is done directly on the chip metal pads, intermetallic compound (IMC) formation on the chip interface is avoided. The concern of solder diffusion and interaction with the thin films on the chip is also eliminated. In addition, failure is unlikely to happen on the chip interface since Cu mechanical properties are much better than solder. The pillar structure can also be engineered such that stress concentration and shear strain on solder is reduced.
a and 2b show a schematic drawing of a conventional pillar interconnect design 200 with a larger and a smaller pillar diameter respectively. A key issue of the conventional pillar interconnect design 200 is that the solder volume 204 and its wetting surface 206 vary as the diameter of the pillar 202 changes. The pillar 202 with a smaller diameter, as shown in
Hence, there is a need to provide an alternative interconnect structure, and method which seek to address at least one of the above-mentioned problems.
In accordance with a first aspect of the present invention, there is provided an interconnect structure comprising: a base portion formed on a mounting surface of a first component; a pillar portion extending from the base portion and substantially perpendicularly to the mounting surface; and a head portion formed on the pillar portion and having larger lateral dimensions than the pillar portion; wherein the base portion and the pillar portion are integrally formed of a homogeneous material.
The base portion may have larger lateral dimensions than the pillar portion.
The base portion, the pillar portion and the head portion may be integrally formed of the homogeneous material.
The interconnect structure may further comprise an intermediate layer formed between the head portion and the pillar portion, the intermediate layer comprising materials other than the homogenous material.
The intermediate layer may comprise TiW and Cu, Ti and Cu, or Cr and Cu.
The base portion may be formed on a contact layer formed on the mounting surface of the first component.
The contact layer may comprise TiW and Cu, Ti and Cu, or Cr and Cu
The homogenous material may comprise a metal or a conducting material suitable for electroplating.
The metal may comprise one or more of a group consisting of Cu, Ni, and Au.
The pillar portion and the head portion may have a same cross sectional shape.
The pillar portion and the head portion may have a different cross sectional shape.
The pillar portion and the base portion may have a same cross sectional shape.
The pillar portion and the base portion may have a different cross sectional shape.
The head portion and the base portion may have a same cross sectional shape.
The head portion and the base portion may have a different cross sectional shape.
The head portion may have a surface disposed for facing a second component to which the first component is to be mounted.
The surface may be convex.
The surface may be planar.
A dielectric or passivation layer may be deposited on the first component and such that the pillar portion and the base portion are either encapsulated or remain exposed.
At least one of the base portion, the pillar portion and the head portion may be uniformly coated or selectively coated with one or more selected from a group consisting of a wetting layer, a diffusion barrier layer and a oxidation resistant layer.
In accordance with a second aspect of the present invention, there is provided an interconnect structure for interconnecting first and second components, the interconnect structure comprising: a base portion formed on a mounting surface of the first component; a pillar portion extending from the base portion and substantially perpendicularly to the mounting surface; and a head portion formed on the pillar portion and having larger lateral dimensions than the pillar portion; a contact pad formed on a mounting surface of the second component; and a connection for connecting the head portion of the interconnect structure to the contact pad; wherein the base portion and the pillar portion are integrally formed of a homogeneous material.
The connection for connecting the head portion of the interconnect structure to the contact pad may comprise one or more of a group consisting of solder, adhesive bonding, surface activated bonding, compression bonding and diffusion bonding.
A solder bump may be formed between facing surfaces of the head portion and the contact pad respectively.
The head portion and the contact pad may be substantially encapsulated by solder.
In accordance with a third aspect of the present invention, there is provided an interconnect structure for interconnecting a multiple component stack and a substrate, the interconnect structure comprising: a first base portion formed on a first mounting surface of a first component of the stack; a first pillar portion extending from the first base portion and substantially perpendicularly to the first mounting surface; and a second head portion formed on the second pillar portion and having larger lateral dimensions than the second pillar portion; a second base portion formed on a second mounting surface of a second component of the stack; a second pillar portion extending from the second base portion and substantially perpendicularly to the second mounting surface; and a second head portion formed on the second pillar portion and having larger lateral dimensions than the second pillar portion; a first and a second contact pad formed on a mounting surface of the substrate; and a connection for connecting the head portions to the respective contact pads respectively; wherein the base portions and the pillar portions are integrally formed of a homogeneous material pillar and the first pillar portion is higher than the second pillar portion.
The interconnect structure may further comprise a spacer disposed between the first and second components of the stack.
The connection for connecting the head portion of the interconnect structure to the contact pad may comprise one or more of a group consisting of solder, adhesive bonding, surface activated bonding, compression bonding and diffusion bonding.
In accordance with a fourth aspect of the present invention, there is provided a method of fabricating an interconnect structure, the method comprising: forming a base portion on a mounting surface of a first component; forming a pillar portion, the pillar portion extending from the base portion and substantially perpendicularly to the mounting surface; and forming a head portion on the pillar portion, the head portion having larger lateral dimensions than the pillar portion; and integrally forming the base portion and the pillar portion with a homogeneous material.
The method may further comprise forming the pillar portion and the head portion using different masks in a photolithography process.
The step of forming the pillar portion and the head portion may comprise an imprinting process
A mould for the imprinting process may be patterned and may comprise polymer, composite or metal materials.
The method may further comprise forming an intermediate layer between the head portion and the pillar portion.
Embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:
a and 2b show a schematic drawing of a conventional pillar interconnect design with a larger and a smaller pillar diameter respectively.
a shows a schematic drawing of an assembly of a micro device chip and a substrate, which are connected by a pin-head interconnect structure and a solder bump, according to an example embodiment.
b shows a schematic drawing of the assembly with a pin-head interconnect structure having a smaller diameter as compared to that shown in
a shows a schematic drawing of the pin-head interconnect of
b and 4c show schematic drawings of variations of the pin-head interconnect of
d shows a schematic drawing of a variation of the pin-head interconnect of
e to 4g show top sectional views of the pin-head interconnect having different designs of horizontal portions.
a to 5j show a process flow for fabricating a pin-head interconnect using photolithography-plating, according to an example embodiment.
a to 6g show a continuation of a process for fabricating the pin-head interconnect using photolithography-plating from
a to 7g show an alternative continuation of a process for fabricating the pin-head interconnect using photolithography-plating from
a to 8j shows a process flow for fabrication of a pin-head interconnect using low cost imprinting-plating process, according to an example embodiment.
a show a schematic drawing of pin-head interconnects connected to a micro device.
b show a schematic drawing of planarized pin-head interconnects connected to the micro device.
a to 10c show schematic drawings of one micro device interconnected to a substrate using different interconnect structures embodying the present invention.
a and 11b show schematic drawings of two micro devices interconnected to the substrate using different interconnect structures embodying the present invention.
The embodiments described herein provide an interconnect structure to overcome the inherent weaknesses in solder bump interconnection. The embodiments also provide an improved interconnect structure to overcome the current limitations that metal interconnects and solder bumps have in micro devices packaging or integration.
a shows a schematic drawing of an assembly 300 of a micro device chip 302 and a substrate 304, which are connected by a pin-head interconnect structure 306 and a solder bump 308. A base material of the micro device chip 302 can be, for example but not limited to, semiconductor materials such as silicon, ceramic, glass or polymer materials, or the like. The base material of the micro device chip 302 can be passivated with dielectric materials, metallized, patterned and circuited with channels, metal traces and pads, The pin-head interconnect 306 comprises a substantially vertical pillar portion 310 and a substantially horizontal head portion 312. The head portion 312 is disposed at one end of the pillar portion 310. The other end of the pillar portion 310 of the pin-head interconnect 306, i.e. the end opposite that having the head portion 312, is in contact with a micro device chip 302. The solder bump 308 is deposited between the head portion 312 and a metal pad 314 of a substrate 304. The pillar portion 310 and the head portion 312 of the pin-head interconnect 306 are made of a homogeneous metal. One example of the homogeneous metal is copper. It is preferred that the solder bump 308 is lead-free. The substrate 304 can be made of any polymer, composite or inorganic materials such as polyimide, glass-epoxy, ceramic or silicon etc. It will be appreciated by a person skilled in the art that other materials can be used for the micro device chip 302, the pin-head interconnect 306, the solder bump 308 and the substrate 304 in other embodiments.
b shows a schematic drawing of the assembly 300 with a pillar portion 310 of a pin-head interconnect 306 having a smaller width 316 as compared to that of
a shows a schematic drawing of the pin-head interconnect 302 of
In the embodiments of
c shows a schematic drawing of a variation of the pin-head interconnect 302 of
e shows a top sectional view of the pin-head interconnect 302 having a substantially round pillar portion 306 and a substantially round base portion 402 and a substantially round head portion 308.
In the embodiments of
Two example methods, namely photolithography-plating and imprinting-plating, that can be used for manufacturing pin-head interconnects will now be described.
The process of forming the copper layer 510 illustrated in
d shows a schematic diagram of a second photoresist (PR2) layer 512 deposited on the PR1 layer 506 with an opening 514 formed. The opening 514 is formed in the PR2 layer 512 with conventional photolithography processes. A copper layer 516 is deposited in the opening 514 by e.g. electroplating, as shown in
In other embodiments, it is possible to end the process of manufacturing the pin-head interconnect at
Alternatively, after the copper layer 516 is deposited in the gap 514 as shown in
With reference to
c shows that a pin-head interconnect 608 made of Cu with a planarized copper layer 606 after planarization.
In other embodiments, it is possible to end the process of manufacturing the pin-head interconnect at
With reference to
In other embodiments, it is possible to end the process of manufacturing the pin-head interconnect at
a to 8j shows a process flow for fabrication a pin-head interconnect using low cost imprinting-plating process.
The process of forming the copper layer 810 illustrated in
d shows a schematic diagram of a second polymer resist (PR2) layer 812 deposited on the PR1 layer 806. An imprinting mould 814 is used to form a cavity 816 in the PR2 layer 812, as shown in
g shows that a pin-head interconnect 820 made of Cu is formed. The PR1 layer 806 and the PR2 layer 812 are removed.
In other embodiments, it is possible to end the process of manufacturing the pin-head interconnect at
In the above described photolithography-plating and imprinting-plating processes, the formation of the pin-head interconnect can be viewed as the formation of a modified chip interconnect structure. Further, parts including the base portion, the pillar portion and the head portion of the interconnect structures can be uniformly or selectively treated or coated to enhance their wetting, diffusion and oxidation resistant behaviour. Nickel, for example, is commonly used as a diffusion barrier layer and gold as an oxidation resistant layer. These metals can be deposited on the interconnect structures by sputtering or electroplating processes. The pin-head interconnect structures can be advantageously fabricated at the wafer level. The micro devices can be assembled on a substrate with or without underfill encapsulation.
Further, copper is used to form the base portions and the pillar portions of the pin-head interconnects described above. In other embodiments, nickel or gold can be used for forming the base portion and the pillar portion. In such embodiments, the adhesion and seed layer may comprise nickel or gold.
In the above described photolithography-plating and imprinting-plating processes, the pin-head interconnects are first formed on the silicon chip and substrates are then brought into contact with the pin-head interconnects. In other embodiments, the pin-head interconnects can be first formed on the substrates and the silicon chips are then brought into contact with the pin-head interconnects.
a show a schematic drawing of pin-head interconnects 902 connected to a micro device 904. The micro device 904 can be any devices with electronic, optic, fluidic or micro-electro-mechanical functions or a combination of these functions. The pin-head interconnects 902 comprise a base portion 906, a pillar portion 908 and a head portion 910. The base portion 906 and the head portion 910 are disposed at respective ends of the pillar portion 908. A passivation layer 914 of the micro device 904 can be of photoimageable or non-photoimageable material.
In this embodiment, the base portion 906 and the head portion 910 have larger lateral dimensions than the pillar portion 906. The head portion 910 has larger lateral dimensions than the base portion 906. The base portion 906, the pillar portion 908 and the head portion 910 have different cross-sectional areas. The base portion 906 surface is substantially planar and the head portion 910 has a curved surface.
b show a schematic drawing of another example of pin-head interconnects 902 of
a, 10b and 10c show schematic drawings of one micro device 904 interconnected to a substrate 10. In
The pin-head interconnects can be used for joining, interconnecting or supporting micro devices 904 for purposes of packaging and integration.
With the pin-head interconnect design in the example embodiments, the Cu pin-head interconnect can advantageously be plated directly on a Cu metallized chip pad. Hence, UBM is no longer necessary on a chip pad. Designing and optimizing the interconnect reliability on the substrate side is less complex because the concern of thin film materials and active device interaction exist only on the chip side.
High current, coupled with the need to reduce the package size, lead to high heat generation within the package. The ability to design and structure Cu interconnect for specific locations on the same chip can advantageously enhance thermal performance significantly. As a chip size gets smaller and denser, high temperature and current density promote electromigration is a growing concern. Since the melting point of Cu is 1083° C., which is much higher in comparison to the melting point of most leaded or lead-free solder materials, the atomic diffusion of a Cu pin-head interconnect is advantageously much slower than most solder materials. Hence, electromigration is advantageously reduced in the Cu pin-head interconnect.
It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive.
For example, it will be appreciated that in different embodiments, the base of the pillar structure is formed on a surface of the substrate, for connection of the pillar head to the chip. More generally, the interconnect structure can be applied between mounting surfaces of two components or elements to be interconnected, or between multi component stacks and a substrate, in different embodiments.
Furthermore, the homogenous material for the interconnect structure may comprise any metal or any conducting material suitable for electroplating, in different embodiments.
Furthermore, in other embodiments, the interconnect structure can be formed on any surface that can be subjected to electroplating for formation of the interconnect structure. Also, if the interconnect structure is to be formed on surfaces that cannot be subjected to electroplating, a seed plating layer may be deposited. An additional adhesion layer may be required if the seed layer cannot adhere directly to the base material of the surface.
In various embodiments, the interconnect structure can be fabricated by other electroplated metals like nickel or gold. The adhesion layer can be TiW, Ti or Cr and the seed layer for plating can be nickel or gold if a silicon, glass or ceramic substrate is used. For other materials like epoxy-glass fibre base, the seed or plating layer can be laminated on the base material.
| Number | Date | Country | Kind |
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| 200717535-9 | Nov 2007 | SG | national |
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|---|---|---|---|---|
| PCT/SG2008/000406 | 10/21/2008 | WO | 00 | 6/21/2010 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2009/061282 | 5/14/2009 | WO | A |
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