The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from continuous reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFPs), pin grid array (PGA) packages, ball grid array (BGA) packages, and so on.
Currently, integrated fan-out packages are becoming increasingly popular for their compactness.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIG.s. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIG.s. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
Referring to
In some embodiments, a die 120a and a die 20b are attached side by side to the de-bonding layer 11 over the carrier 10 through an adhesive layer 12 such as a die attach film (DAF), silver paste, or the like. The die 120a and the die 20b may respectively be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, a memory chip or the like. The die 120a and the die 20b may be the same types of dies or the different types of dies. In some embodiments, the two dies 120a and 20b are two small die partitions with different function of a larger single die. The size (refers to the height and/or the width) of the two dies 120a and 20b may be the same or different. In some embodiments, a gap 21 is existed between the two dies 120a and 20b. The number of the dies attached to the carrier 10 is not limited to that is shown in
In some embodiments, the two dies 120a and 20b have similar structures. For the sake of brevity, the die 120a is taken for example. The die 120a includes a substrate 13a, a pad 14a, a passivation layer 15a, conductive posts 19a and a protection layer 18a.
In some embodiments, the substrate 13 is made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 13 includes other elementary semiconductor materials such as germanium, gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substrate 13 may further include other features such as various doped regions, a buried layer, and/or an epitaxy layer. Moreover, in some embodiments, the substrate 13 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate 13 may be a semiconductor on insulator such as silicon on insulator (SOI) or silicon on sapphire.
The pads 14a may be a part of an interconnection structure (not shown) and electrically connected to the devices (not shown) formed on the substrate 13a. In some embodiments, the devices may be active devices, passive devices, or a combination thereof. In some embodiments, the devices are integrated circuit devices. The passivation layer 15a is formed over the substrate 13a and covers a portion of the pads 14a. A portion of the pads 14a is exposed by the passivation layer 15a and serves as an external connection of the die 120a. In some embodiments, the passivation layer 15a includes a first passivation layer 8a and a second passivation layer 9a on the first passivation layer 8a. The material of the first passivation layer 8a and the material of the second passivation layer 9a may be the same or different. The second passivation layer 9a is also referred as a post-passivation layer, and is optionally formed.
The conductive posts 19a are formed on and electrically connected to the pads 14a exposed by the passivation layer 15a. In some embodiments, the conductive post 19 includes a first portion 16a and a second portion 17a. The first portion 16a is embedded in and laterally covered by the passivation layer 15a. The second portion 17a is on the first portion 16a and the passivation layer 15a. In some embodiments, the second portion 17a covers a portion of the top surface of the passivation layer 15a. In some other embodiments, the second portion 17a is on the first portion 16a and does not cover the top surface of the passivation layer 15a. The second portion 17a is also referred as a connector. The conductive posts 19a include solder bumps, gold bumps, copper bumps, copper posts, copper pillars, or the like. The protection layer 18a is formed over the passivation layer 15a and aside the connectors 17a to cover the sidewalls of the connectors 17a. The passivation layer 15a and the protection layer 18a respectively include an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof. The polymer includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like, for example. In some embodiments, the passivation layer 15a and the protection layer 18a are free of fillers. The materials of the passivation layer 15a and the protection layer 18a may be the same or different. In some embodiments, the top surface of the protection layer 18a is substantially level with the top surface of the connectors 17a.
Similar to the die 120a, the die 20b includes a substrate 13b, a pad 14b, a passivation layer 15b, and a conductive post 19b. In some embodiments, the passivation layer 15b includes a first passivation layer 8b and a second passivation layer 9b. The second passivation layer 9b is also referred as a post-passivation layer and is optionally formed. The conductive post 19b includes a first portion 16b and a second portion 17b. The second portion 17b is also refereed as a connector. The material and the structural characteristics of the substrate 13b, the pad 14b, the passivation layer 15b, and the conductive post 19b of the die 20b are substantially the same as or different from those of the substrate 13a, the pad 14a, the passivation layer 15a, the conductive post 19a of the die 120a. The die 20b differs from the die 120a in that, no protection layer is formed aside the connectors 17b. That is to say, the sidewalls of the connectors 17b are not covered by a protection layer, but exposed. In some embodiments, the top surfaces of the connectors 17a and the top surfaces of the connectors 17b are substantially coplanar with each other, but the disclosure is not limited thereto. In some other embodiments, the top surfaces of the connectors 17a and the top surfaces of the connectors 17b may be not coplanar with each other.
In some embodiments, the dies 120a and 20b respectively has a first sidewall 40a and a second sidewall 40b opposite to each other. The first sidewall 40a of the die 120a or 20b is the sidewall adjacent to another die 20b or 120a, and the second sidewall 40b of the die 120a or 20b is the sidewall far away from another die 20b or 120a. The first sidewalls 40a and the second sidewalls 40b may be straight or inclined.
Referring to
In some embodiments, the first encapsulant material layer 22 is formed of an underfill material, a molding underfill material, polymer, or a combination thereof. The polymer includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. Referring to the enlarged view of the first encapsulant material layer 22, in some embodiments in which the first encapsulant material layer 22 is formed of underfill material or molding underfill material, the first encapsulant material layer 22 includes polymer and a plurality of fillers 22′. The filler 22′ may be a powdered inorganic material, the filler 22′ may be a single element, a compound such as nitride, or a combination thereof, e.g., silica, alumina, carbon, or aluminum nitride, or mixtures thereof. In some embodiments, the filler 22′ is fine filler whose particle size is very small. The average particle size of the filler 22′ ranges from 0.1 μm to 10 μm, or even smaller than 0.1 μm, for example. In some other embodiments, the first encapsulant material layer 22 may be free of filler. The first encapsulant material layer 22 may be formed by a dispensing process, for example. In some embodiments, after the first encapsulant material layer 22 is dispensed in the gap 21 and on the die 20b, a curing process is further performed.
Still referring to
Referring to
Referring to the enlarged view of the first encapsulant material layer 22 and the second encapsulant material layer 23, in some embodiments, the second encapsulant material layer 23 is a composite material including a polymer and a plurality of fillers 23′. The filler 23′ may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers 23′ may comprise silicon oxide, aluminum oxide, boron nitride, alumina, silica, and the like, for example. The cross-section shape of the filler 22′ or 23′ may be circle, square, rectangle, or any other shape, and the disclosure is not limited thereto. In some embodiments, the particle size of the filler 23′ is larger than the particle size of the filler 22′, herein, the particle size of the filler 22′ or 23′ refers to the diameter, length, width or height of the filler 22′ or 23′. The average particle size of the filler 23′ ranges from 3 μm to 30 μm, or even larger than 30 μm, for example. In some embodiments, the particle size is referred to the average particle size D50, and the average particle size D50 of the filler 23′ is larger than the average particle size D50 of the filler 22′.
Referring to
Referring to
Still referring to
Interfaces also exist between the protection layer 18a and the first encapsulant 22a, and between the protection layer 18a and the second encapsulant 23a. In some embodiments, the interface between the protection layer 18a and the first encapsulant 22a and the interface between the protection layer 18a and the second encapsulant 23a may respectively be straight or inclined.
Referring to
The redistribution layer RDL1 penetrates through the polymer layer PM1 and is electrically connected to the connectors 17a and 17b of the dies 120a and 20b. The redistribution layer RDL2 penetrates through the polymer layer PM2 and is electrically connected to the redistribution layer RDL1. The redistribution layer RDL3 penetrates through the polymer layer PM3 and is electrically connected to the redistribution layer RDL2. The redistribution layer RDL4 penetrates through the polymer layer PM4 and is electrically connected to the redistribution layer RDL3.
The material of the polymer layer PM1, PM2, PM3, PM4 may be the same as or different from the material of the protection layer 18a of the die 120a, the material of the first encapsulant 22a or the material of the second encapsulant 23a. In some embodiments, each of the polymer layers PM1, PM2, PM3 and PM4 includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. In some embodiments, the protection layer 18a is referred as a polymer layer PM0.
In some embodiments, each of the redistribution layers RDL1, RDL2, RDL3 and RDL4 includes conductive materials. The conductive materials includes metal such as copper, nickel, titanium, a combination thereof or the like, and is formed by an electroplating process. In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 respectively includes a seed layer (not shown) and a metal layer formed thereon (not shown). The seed layer may be a metal seed layer such as a copper seed layer. In some embodiments, the seed layer includes a first metal layer such as a titanium layer and a second metal layer such as a copper layer over the first metal layer. The metal layer may be copper or other suitable metals.
In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 respectively includes a plurality of vias V and a plurality of traces T connected to each other. The vias V vertically penetrate through the polymer layers PM1, PM2, PM3 and PM4 to connect the traces T of the redistribution layers RDL1, RDL2, RDL3 and RDL 4, and the traces T are respectively located on the polymer layers PM1, PM2, PM3 and PM 4, and are respectively horizontally extending on the top surface of the polymer layers PM1, PM2, PM3 and PM4.
In some embodiments, the traces T of the redistribution layers RDL1, especially the traces T1 connecting the die 120a and the die 20b, are routing over the first encapsulant 22a and the protection layer 18a, and not over the second encapsulant 23a. As the top surface of the first encapsulant 22a is relatively more flat than the top surface of the second encapsulant 23a, therefore, the traces T or T1 on the first encapsulant 22a may achieve a fine quality, and the trace broken (open) or bridge (short) issues may occur due to the roughness of the encapsulant is avoided.
In some embodiments, the redistribution layer RDL4 is the topmost redistribution layer of the RDL structure 26, and is referred as an under-ball metallurgy (UBM) layer for ball mounting.
Still referring to
Referring to
Referring to
In some embodiments, the first encapsulant 22a is located between the die 120a and the die 20b, and on the die 20b. The first encapsulant 22a at least encapsulates the first sidewall 40a of the die 120a, the first sidewall 40a of the die 20b, the sidewalls of the connectors 27 of the die 20b, and a portion of the top surface of the passivation layer 15b of the die 20b. In some embodiments, the cross-section shape of the portion of the first encapsulant 22a under the trace T1 is reversed L-shaped, for example. In some embodiments, the sidewalls of the portion of the first encapsulant 22a between the two dies 120a and 13b are straight or inclined. The sidewall of the first encapsulant 22a on the edge of the die 20b is inclined, curved, or arced.
In some embodiments, the second encapsulant 23a is aside and encapsulates the sidewall of the first encapsulant 22a, aside and encapsulates the second sidewalls 40b of the dies 120a and 20b.
The connectors 17a of the die 120a are laterally covered by and in contact with the protection layer 18a, and are separated from the first encapsulant 22a. The protection layer 18a of the die 120a is in contact with the first encapsulant 22a at the first sidewall 40a of the die 120a, and in contact with the second encapsulant 23a at the second sidewall 40b of the die 120a. The connectors 17b of the die 20b are laterally covered by and in contact with the first encapsulant 22a, and separated from the second encapsulant 23a.
The corner θ1 of the die 20b is covered by and in contact with the first encapsulant 22a. The corner θ2 of the die 20b is covered by and in contact with the first encapsulant 22a or/and the second encapsulant 23a. The corner β1 of the die 120a is covered by and in contact with the protection layer 18a and the first encapsulant 22a. The corner β2 of the die 120a is covered by and in contact with the protection layer 18a and the second encapsulant 23a. Herein, the corners θ1 and θ2 are referred to the corners of the passivation layer 15b of the die 20b, the corners β1 and β2 are referred to the corners of the passivation layer 15b of the die 20b.
In some embodiments, the interface 24 includes two end points 24a and 24b. The end point 24a is in contact with the polymer layer PM1 of the RDL structure 26, and at the same plane as the top surfaces of the connectors 17a/17b. The end point 24b is on the edge of the die 20b and is in contact with the protection layer 15b. In some embodiments, the end point 24b is on the top surface of the protection layer 15b, and away from the second sidewall 40b of the die 20b. In some embodiments, the end point 24b is at the intersection point of the top surface of the passivation layer 15b and the second sidewall 40b of the die 20b. In some embodiments, an included angle α between the interface 24 and the top surface of the passivation layer 15b is less than 90°. In other words, the interface 24 is inclined towards the connector 17a of the die 20b. A portion of the second encapsulant 23a is located over the die 20b.
In some embodiments in which the interface 24 is connected to the second sidewall 40b of the die 20b, the top surface of the passivation layer 15b of the die 20b is covered by the first encapsulant 22a, and is not in contact with the second encapsulant 23a. However, the disclosure is not limited thereto. In some other embodiments in which the interface 24 is not connected to the second sidewall 40b of the die 20b (shown as the dotted line A′), a portion of the top surface of the passivation layer 15b adjacent to the corner θ2 is not covered by the first encapsulant 22a, but is covered by the second encapsulant 23a.
In some embodiments, the package structure 50a may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27.
Referring to
Still referring to
In some embodiments, the first sidewall 40a, the second sidewall 40b and the corners θ1 and θ2 of the die 20b are covered and in contact with the first encapsulant 22a, and are not in contact with the second encapsulant 23a. The second sidewall 40b and the corner θ2 of the die 20b are separated from the second encapsulant 23a by the first encapsulant 22a therebetween. The structural relationship between the die 120a and the encapsulants 22a and 23a are substantially the same as those of the package structure 50a (
Referring to
Referring to
In some embodiments, the top surfaces of the passivation layer 15a and 15b are completely covered by the first encapsulant material layer 122, but the disclosure is not limited thereto. In some other embodiments, portions of the top surfaces of the passivation layer 15a and 15b on the edge (the edge adjacent to the second sidewalls 40b) of the dies 20a and 20b may be not covered by the first encapsulant material layer 122, but exposed (shown as the dotted line C).
In some embodiments, the second sidewalls 40b of the dies 20a and 20b are not covered by the first encapsulant material layer 22, and are exposed. However, the disclosure is not limited thereto. In some other embodiments, the first encapsulant material layer 122 may further extend to encapsulate the second sidewalls 40b of the dies 20a and 20b (shown as the dotted line D).
Referring to
Referring to
Referring to
Thereafter, the de-bonding layer 11 is decomposed under the heat of light, and the carrier 10 is then released. In some embodiments, the adhesive layer 12 is removed by, for example, a cleaning process. The bottom surfaces (or referred as back surfaces) of the dies 20a and 20b are exposed.
Referring to
The first encapsulant 122a is located between the die 20a and the die 20b, and on the dies 20a and 20b. The first encapsulant 122a at least encapsulates and contacts with the first sidewalls 40a of the dies 20a and 20b, the sidewalls of the connectors 17a and 17b, and portions of the top surfaces of the passivation layer 15a and 15b. The top surface of the first encapsulant 122a is in contact with the bottom surface of the polymer layer PM1. In some embodiments, the cross-section shape of the portion of the first encapsulant 122a under the trace T1 of the RDL1 is T-shaped. In some embodiments, the sidewalls of the first encapsulant 122a are inclined, curved, or arced.
The second encapsulant 123a is located aside and encapsulates the second sidewalls 40b of the dies 20a and 20b and the sidewalls of the first encapsulant 122a.
An interface 124 is existed between the first encapsulant 122a and the second encapsulant 123a. The interface 124 includes a first interface 124a and a second interface 124b. The interface 124a is on an edge (the edge adjacent to the corner β2) of the die 120a. In some embodiments, the first interface 124a is connected to the second sidewall 40b of the die 20a. In some other embodiments, the first interface 124a is not connected to the second sidewall 40b of the die 20a (shown as the dotted line C′). The interface 124b is on an edge (the edge adjacent to the corner θ2) of the die 20b. In some embodiments, the second interface 124b is connected to the second sidewall 40b of the die 20b. In some other embodiments, the interface 124b is not connected to the second sidewall 40b of the die 20b (shown as the dotted line). In some embodiments, the first interface 124a and the second interface 124b are symmetrical to each other, but the disclosure is not limited thereto. The structural characteristics of the first interface 124a and the second interface 124b are respectively similar to those of the interface 24 shown in
The connectors 17a of the die 20a and the connectors 17b of the die 20b are laterally covered by and in contact with the first encapsulant 122a, and are separated from the second encapsulant 123a. The corner β1 of the die 20a and the corner θ1 of the die 20b are covered by and in contact with the first encapsulant 122a. The corner β2 of the die 20a and the corner θ2 of the die 20b are covered by and in contact with the first encapsulant 122a or/and the second encapsulant 123a. In some embodiments in which the interface 124 is on the edges of the dies 20a and 20b, and not connected to the second sidewalls 40b of the dies 20a and 20b (shown as the dotted line C′), the corner β2 of the die 20a and the corner θ2 of the die 20b are covered by the second encapsulant 123a.
In some embodiments, the top surfaces of passivation layer 15a and the passivation layer 15b are covered by the first encapsulant 122a, and are not in contact with the second encapsulant 123a, but the disclosure is not limited thereto. In some other embodiments, a portion of the top surface of the passivation layer 15a adjacent to the corner β2 of the die 20a, and a portion of the top surface of the passivation layer 15b adjacent to the corner θ2 of the die 20b are not covered by the first encapsulant 122a, but covered by the second encapsulant 123a (shown as the dotted line C′).
Thereafter, the package structure 150a may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27.
Referring to
Still referring to
The second encapsulant 123a is located aside the first encapsulant 122a, encapsulating the sidewalls of the first encapsulant 122a. The second encapsulant 123a is not in contact with the second sidewalls 40b of the dies 20a/20b, but separated from the dies 20a/20b by the first encapsulant 122a therebetween.
The interface 124′ between the first encapsulant 122a and the encapsulant 123a is not in contact with the edge of the dies 20a and 20b, or connected to the second sidewalls 40b of the dies 20a and 20b. Instead, portions of the interface 124′ are located aside the second sidewalls 40b of the dies 20a and 20b. The interface 124′ includes a first interface 124a′ aside the second sidewall 40b of the die 20a, and a second interface 124b′ aside the second sidewall 40b of the die 20b. In some embodiments, the first interface 124a′ and the second interface 124b′ are symmetrical to each other, but the disclosure is not limited thereto. The structural characteristics of the first interface 124a′ and the second interface 124b′ are respectively similar to those of the interface 24′ shown in
Referring to
Referring to
A second encapsulant material layer 223 is formed on the carrier 10, the dies 120a and 120b, and the first encapsulant material layer 222. The materials and the forming methods of the first encapsulant material layer 222 and the second encapsulant material layer 223 are substantially the same as those of the first encapsulant material layer 22 and the second encapsulant material layer 23 described in the first embodiment, respectively.
Referring to
Referring to
The de-bonding layer 11 is decomposed under the heat of light, and the carrier 10 is then released. In some embodiments, the adhesive layer 12 is removed. The bottom surfaces (or referred as back surfaces) of the dies 120a and 120b are exposed.
Referring to
The first encapsulant 222a is located between the die 120a and the die 120b, that is, aside the first sidewalls 40a of the dies 120a and 120b, encapsulating and contacting with the first sidewalls 40a of the dies 120a and 120b. In some embodiments, the cross-section shape of the first encapsulant 222a includes I-shape, rectangle, square, or a combination thereof. The second encapsulant 223a is located aside, encapsulates and contacts with the second sidewalls 40b of the dies 120a and 120b. In this embodiment, the first encapsulant 222a and the second encapsulant 223a are not in contact with each other. The connectors 17a and 17b are not in contact with the first encapsulant 222a or the second encapsulant 223a, but are respectively surrounded by and in contact with the protection layers 18a and 18b. Interfaces are existed between the protection layer 18a/18b and the first encapsulant 222a or between the protection layer 18a/18b and the second encapsulant 223a, and the interfaces may be straight or inclined.
Thereafter, the package structure 250 may further be electrically coupled to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors 27.
In the foregoing embodiments, package structure including two dies and method of manufacturing the same are illustrated. However, the disclosure is not limited thereto, the disclosure may also applied to single die package structure including one die or multiple die package structure including more than two dies.
In the embodiments of the disclosure, the encapsulant including a first encapsulant and a second encapsulant aside the dies are formed of two different materials by two step processes. The first encapsulant is formed at least aside the first sidewalls of the two dies, the second encapsulant is formed aside the second sidewalls of the two dies. The first encapsulant is formed of a material comprising fine fillers or no filler. Therefore, the problem of roughness surface or even pits may be caused by large filler are avoided. On the other hand, the first encapsulant is formed at least between the two dies, especially under the traces connecting the two dies. In other words, the traces of the bottommost redistribution layer are routing over the first encapsulant or/and the protection layer of the die in which no filler or fine filler is included. Therefore, the traces may achieve a fine quality, and the trace broken (open) and bridge (short) issues may occur due to the roughness of the encapsulant is avoided.
In accordance with some embodiments of the disclosure, a package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a conductive terminal. The first die includes a first connector, and the second die includes a second connector. The first encapsulant includes: a first portion, on the second die; a second portion, sandwiched between a first sidewall of the first die and a first sidewall of the second die; and a third portion, covering a second sidewall of the second die. The second encapsulant laterally encapsulates the first die, the second die and the first encapsulant. The conductive terminal is electrically connected to the first die and the second die through a redistribution layer (RDL) structure. The third portion of first encapsulant is sandwiched between the second sidewall of the second die and the second encapsulant.
In accordance with alternative embodiments of the disclosure, a package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a conductive terminal. The first die includes a first connector, and the second die includes a second connector. The first encapsulant laterally encapsulates the first die and the second die, and is sandwiched between a first sidewall of the first die and a first sidewall of the second die adjacent to the first sidewall of the first die. The second encapsulant laterally encapsulates the first encapsulant. The conductive terminal is electrically connected to the first die and the second die through a redistribution layer (RDL) structure. The first encapsulant is further laterally sandwiched between a second sidewall of the first die and the second encapsulant, and a second sidewall of the second die and the second encapsulant.
In accordance with some embodiments of the disclosure, a method of forming a package structure includes: providing a first die and a second die, wherein the first die includes a first connector, and the second die includes a second connector; forming a first encapsulant, laterally encapsulating the first die and the second die, and sandwiched between a first sidewall of the first die and a first sidewall of the second die adjacent to the first sidewall of the first die; forming a second encapsulant, laterally encapsulating the first encapsulant; and forming a conductive terminal, electrically connected to the first die and the second die through a redistribution layer (RDL) structure. The first encapsulant is further laterally sandwiched between a second sidewall of the first die and the second encapsulant, and a second sidewall of the second die and the second encapsulant.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.
This application is a divisional application of and claims the priority benefit of a prior application Ser. No. 17/207,748, filed on Mar. 22, 2021. The prior application Ser. No. 17/207,748 is a continuation application of and claims the priority benefit of a prior application Ser. No. 15/835,466, filed on Dec. 8, 2017, now allowed. The prior application Ser. No. 15/835,466 claims the priority benefit of U.S. provisional application Ser. No. 62/584,914, filed on Nov. 13, 2017. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
Number | Date | Country | |
---|---|---|---|
62584914 | Nov 2017 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 17207748 | Mar 2021 | US |
Child | 18786606 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 15835466 | Dec 2017 | US |
Child | 17207748 | US |