Patent Application
20100171543
The present invention relates to semiconductor devices and more particularly to power MOSFET devices.
Power switching devices connected in pairs in a totem pole fashion between the upper and lower rails of the power source are common in power electronics applications as described in, for example, U.S. Pat. No. 6,246,296 to Smith, the entirety of which is hereby incorporated by reference herein. As shown in FIG. 1 of Smith (reprinted as FIG. 1 of this application) for the case of two insulated-gate bipolar transistor (IGBT) devices, one switch is connected between the supply voltage and the load connector and the second switch is connected between the load connector and ground. The totem pole configuration of the switches is a basic element of the majority of Pulse Width Modulation (PWM) systems like Switched Mode Power Supply (SMPS) or motor control schemes.
The same configuration of two power switches implemented in a converter circuit is usually called a push-pull stage, as described in U.S. Pat. No. 4,633,106 to Backes et al. and U.S. Pat. No. 5,515,258 to Viertler, the entirety of each of which is hereby incorporated by reference herein. An example from Viertler reprinted as FIG. 2 in this application uses bipolar transistors as power switches. Voltage regulators, such as DC-to-DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC-to-DC converters are particularly needed for battery management in low power devices, such as laptop notebooks and cellular phones. Switching voltage regulators (or simply “switching regulators”) are known to be an efficient type of DC-to-DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage, and filtering the high frequency input voltage to generate the output DC voltage. Specifically, the switching regulator includes a switch for alternately coupling and decoupling an input DC voltage source, such as a battery, to a load, such as an integrated circuit. An output filter, typically including an inductor and a capacitor, is coupled between the input voltage source and the load to filter the output of the switch and thus provide the output DC voltage. A controller, such as a pulse width modulator or a pulse frequency modulator, controls the switch to maintain a substantially constant output DC voltage.
A more recent example of a SMPS circuit is a synchronous buck converter as presented by Jon Mark Hancock at the Intel Technology Symposium in 2003 (“The future of discrete power in VRM solutions: LV device roles and silicon/package technology to meet upcoming mainstream power delivery requirements”) (hereinafter, the “ITS'2003 Presentation”). Two power MOSFET switches are connected in a push-pull configuration as shown in FIG. 3. The MOSFET Q1 connected between the supply voltage (Vin) and the LC output filter is called the high side switch or control FET. The second device, MOSFET Q2, connected between the LC output filter and ground is called the low side switch or sync FET, as it works as a synchronous rectifier substituting for a free wheeling diode. The common node between the high side and the low side switches is called a switched node.
As explained by J. Hancock in his ITS'2003 Presentation, parasitic inductances introduced by the assembly of the push-pull stage have a detrimental impact on the performance of the converter. Specifically, the total inductance in the main current path from Vin to ground (inductance nos. 3, 8, 9 and 10 in FIG. 3) determines the voltage ringing on the switched node and the resulting power loss.
In a conventional approach, the two power switches Q1 and Q2 and the corresponding driver shown in FIG. 3 are integrated into a power module as shown in FIG. 4, as described in a presentation by Dr. P. Rutter at the 2004 Intel Technology Symposium (“Design Challenges of Integrated Power Trains (DrMOS)”) (hereinafter “ITS'2004 Presentation). In the power modules shown in FIG. 4, the wired connections between the switches (labeled 6.5 mΩ and 2 mΩ) as well as wired connections to the output terminals introduce significant inductance into the power circuit.
A more advanced module assembly reprinted in FIG. 5 is disclosed in Hashimoto et al., “Advanced Power SiP with Wireless Bonding for Voltage Regulators” July 2007, IEEE. In this module assembly, copper plates substitute for the connecting wires. These copper plates are wide and introduce minimum parasitic inductance. However, when used with power MOSFET devices with vertical current flow, e.g., devices such as planar DMOS (Double Diffused) and trench devices where the top metal is the source and the backside contact is the drain of the transistor, there is a need to connect the front metal on the high side switch (source) to the lead frame of the low side FET (drain). This approach consumes some area and increases the footprint of the module.
One possible solution to this problem is the use of lateral FETs (LDMOS), such as disclosed in U.S. Pat. No. 5,907,173 to Kwon et al., the entirety of which is hereby incorporated by reference herein, and shown in FIG. 6. LDMOS transistors can be integrated monolithically in a single power IC chip as proposed by U.S. Pat. No. 7,038,274 to You et al., the entirety of which is hereby incorporated by reference herein. As described by You et al., and shown in FIG. 8 reprinted therefrom, You et al. integrates the controller, driver transistor and switches on the same piece of silicon into a single IC. However, monolithic power IC implementation is very expensive and complicated, making this approach prohibitive for most power electronics applications.
A configuration for power switches is desired that does not introduce significant parasitic inductance, has minimum footprint area and low manufacturing cost.
A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.
The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings.
The accompanying drawings illustrate preferred embodiments of the invention, as well as other information pertinent to the disclosure, in which:
This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
In embodiments of an exemplary packaged power switching device described herein, two power MOSFET transistors are connected in a totem pole or push-pull (used interchangeably herein) fashion where at least one of them has a device structure with a vertical current flow and a source electrode at the backside of the die. This setup allows for two device terminals at the switched output node to be placed in intimate contact or, alternatively, to connect the front metallization electrodes with a wide connector (e.g., clip or strap) that introduces minimal parasitic inductance.
Examples of preferred power MOSFET devices that may be used in the packaged power switch device with vertical current flow and backside source electrode/terminal are described in the commonly assigned U.S. Pat. No. 7,235,845 to Xu et al. entitled “Power LDMOS transistor,” the entirety of which is hereby incorporated by reference herein. LDMOS transistors as disclosed in Xu et al. are preferred for switching regulators because of their performance in terms of a tradeoff between their specific on-resistance (Rdson) and drain-to-source breakdown voltage (BVds). Although LDMOS devices are preferred for devices having vertical current flow, in embodiments, one or more of the devices may be, for example, a DMOS device or a trench device.
An epitaxial layer 214 is formed over the substrate 112 and has an upper surface 116. The epitaxial layer 214 can have dopants of N (arsenic or phosphorous) or P (boron) dopant type and a dopant concentration of N− or P−. The epitaxial layer 214 preferably has a thickness between about 2 to 4 μm including the transition region of the dopant concentration gradient. The epitaxial layer 214 includes a buffer region 202 formed between the substrate 112 and the body region 232 and lightly doped drain region 226. The buffer region 202 comprises a layer of silicon doped with p-dopants at a concentration equal to or greater than the dopant concentration of the body region 232. The buffer layer 202 abuts the sidewalls of source contact layer 150 and is preferably formed to a thickness between about 0.3 to 0.6 μm. The buffer layer 202 may be formed by deep implantation of Boron into the epitaxial layer 214 before the formation of the gate 118. The buffer layer 202 serves to suppress the well-documented short channel effects by helping to ensure that the depletion region does not reach too far into the channel. The buffer layer provides for better control and reproducibility of the breakdown voltage of the transistor. The breakdown is limited between the drain contact region 128 and the buffer layer 202, rather than between the drain contact region 128 and the upper surface of the substrate 112
A conductive gate 118 overlies the upper surface 116 of the epitaxial layer 214. The conductive gate 118 comprises a lower doped polysilicon layer 120 with an upper silicide layer 122 formed therein or thereover. Silicide layer 122 can comprise any transition metal silicide selected from the group consisting of Ti, W and Co silicides. The conductive gate 118 is formed over a gate dielectric 124.
Drain implant region 128, having dopant concentration N+, is formed in epitaxial layer 214. Lightly doped drain region 126 is formed completely within epitaxial layer 214 and forms an enhanced drift region. The lightly doped drain region 226 forms a PN junction with the layer 202. The LDMOS structure 100 also includes a source implant region 130 having a conductivity N+ spaced from the enhanced drift region 226 and a body region 232 having P-type dopants and having a conductivity of P concentration, which has a subregion between the source 130 and enhanced drain region 226, forming a channel region therebetween.
The transistor device 100 includes an insulating layer 138 formed over the source implant region 130, over the sidewalls of the conductive gate 118 (forming side spacers) and its upper surface, as well as over the enhanced drain drift region 226 and drain implant region 128. The insulating layer 138 insulates the drain and gate regions from the source contact layer described below.
A deep trench 140 is etched adjacent to and contacting the source implant region 130 and body region 132. The trench 140 is preferably formed entirely through the epitaxial layer 214 and, optionally, partially into the substrate layer 112. A highly doped contact implant region 136 is then formed in the substrate 112 having a concentration P++. A conductive layer 150 is formed by a CVD deposition of a silicide, which is subsequently patterned to form the shield electrode 154. The continuous layer 150 forms a source contact, a gate shield and a field plate for the LDMOS transistor 100. The source contact that shorts the source implant region 130, body region 232, buffer layer 202 and highly doped contact region 136. The continuous layer 150 extends over insulation layer 138, over gate 118 and the sidewall spacers of the gate 118 to form a gate shield 154, which shields the gate 118 and source 130 from the drain electrode. Still further, the continuous layer 150 extends over a portion of the insulation layer 138 that is formed over lightly doped region 126 to form a field plate portion 152. The trench 140 is filled with an insulating material during the deposition of the insulating layer 144 over which the drain electrode/terminal 148 is formed.
Details of the gate driver circuit 502, which drives the switching device 504 in power conversion applications are familiar to those in the art and are not detailed herein. One example of a voltage regulator having driver and control circuitry is shown in, for example,
The intermediate terminal is coupled to the output terminal by an output filter. The output filter converts the rectangular waveform of the intermediate voltage at the intermediate terminal into a substantially DC output voltage at the output terminal. Specifically, in a buck-converter topology, the output filter includes an inductor connected between the intermediate terminal and the output terminal and a capacitor connected in parallel with the load. During a high side conduction period, the high side switch is closed, and the voltage source supplies energy to the load and the inductor through the high side switch. On the other hand, during a low side conduction period, the low side transistor switch is closed, and current flows through the low side transistor switch as energy is supplied by the inductor. The resulting output voltage is a substantially DC voltage.
The switching regulator includes a controller and a pair of drivers for controlling the operation of the switching circuit. The controller causes the switching circuit to alternate between the aforementioned high side and low side conduction periods to generate an intermediate voltage at the intermediate terminal that has a rectangular waveform. The controller can also include a feedback circuit, which measures the output voltage and the current passing through the output terminal. Although the controller is typically a pulse width modulator, other modulation schemes, such as pulse frequency modulation, can be used.
Although the switching regulator discussed above in connection with You et al. has a buck converter topology, the other voltage regulator topologies, such as a boost converter or a buck-boost converter, are also applicable.
Improvements to the switching circuit component of, for example, prior art voltage regulators are illustrated herein and discussed below with reference to
Devices 504a and 504b of switching device 504 are preferably mounted on a lead frame and arranged in a single packaged semiconductor device having a first die (or dies) for the high side transistor device 504a and a second die (or dies) for the low side transistor device 504b. As shown in
In the embodiment illustrated in
The high voltage lead 640 (labeled VIN) is also coupled to the drain D1 of the die 610 by a wide, low inductance connector 660. Limiting inductance at this connection is important for device performance. The bottom surface of die 620 is mounted directly onto the ground lead portion 650 of the leadframe of the packaged device 604. Again, a layer conductive solder (not shown) can be used to facilitate this connection. This intimate connection between the source (S2) of the low side transistor and the ground lead 650 also contributes negligible parasitic inductance at an important connection.
As also shown in the figures, the leadframe includes a gate lead portion 646 (labeled G2) for connections to the gate of the die 620, i.e., the gate of the low side transistor switch 504b. This connection is made with a wirebond as, with reference to
Finally, the packaged device includes a source lead portion 644 (labeled S1) that is wirebonded to the source S1 of the die 610 via its connection to the drain D2 of the die 620 (i.e., S1 and D2 are at the common switched output node). This lead 644 is used for coupling the source S1 to the gate driver 502 as shown in
As discussed above, limiting parasitic inductances in the current path, i.e., between the high voltage rail and the high side switch, between the high side switch and the low side switch, and between the low side switch and low voltage rail, is important. Limiting parasitic inductance in this path reduces voltage ringing at the switched node and thus limits power losses. In the device of
In embodiments, a Kelvin source terminal is used for the high side switch in order to decouple the gate drive circuit from the main current path. As known to the people skilled in the art, this allows for a more effective and fast switching of the high side device, which in turn improves the efficiency of the converter.
The embodiment shown in
Die 810 corresponds to high side switch 504a of
As can be seen from the figures, all critical connections, i.e., VIN to S1, S1 to D2, and S2 to GND, are made by direct connection to the lead frame or by wide connector 870. These connections introduce minimal parasitic inductance. The device 804, in which only the low side transistor switch has a backside source electrode, exhibits a larger footprint than the packages of
Using a p-channel transistor for the high side switch 904a simplifies the driving scheme of the push-pull stage. In low voltage applications, the gate of the high side p-channel device can be driven from rail-to-rail and does not require a charge pump or bootstrap circuit as may be required for n-channel transistor device in low voltage applications. As shown in
With more specific reference to
As can be seen from the drawings, critical connections, i.e., VIN to S1, D1 to D2, and S2 to GND, are made by direct connection to the lead frame or by wide connector 1070. These connections introduce minimal parasitic inductance.
As with the device 1004, all critical connections, i.e., VIN to S1, D1 to D2, and S2 to GND, are made by direct connection to the lead frame or by wide connector 1070. These connections introduce minimal parasitic inductance.
As discussed above and shown in the drawings, the various illustrated embodiments focus on the integration and packaging of two MOSFET transistor dies coupled in a push-pull/totem pole configuration into one power module which exhibits low parasitic inductance at critical connections in the current path through the push-pull/totem pole configuration. Critical connections are made either by wide connectors or by direct connections of the dies to each other or to the lead frame. Using one or more devices with vertical current flow and a backside source terminal/electrode facilitates formation of these low inductance connections. As will be recognized by people skilled in the art, the packaging and connection structures and methods shown herein can be used to integrate multiple high side and low side dies in parallel, and/or to integrate a gate driver IC into the same module.
It should also be understood that
Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly to include other variants and embodiments of the invention that may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.
