Patent Application
20080296717
The present invention relates to microelectronic packaging. Microelectronic chips typically are thin, flat bodies with oppositely facing, generally planar front and rear surfaces and with edges extending between these surfaces. Chips generally have contacts on the front surface, which are electrically connected to the circuits within the chip. Certain chips require a protective element, referred to herein as a cap, lid or cover, over all or part of the front surface. For example, chips having optoelectronic devices, e.g., image sensors or light emitting devices and the like incorporate optically active regions on their front surfaces, which are best protected from physical and chemical damage by a cap, lid or cover. Often, the cap, lid or cover overlies a cavity above the active region of the chip.
Certain other types of devices such as microelectromechanical or “MEMS” chips include microscopic electromechanical devices, e.g., acoustic transducers such as microphones or surface acoustic wave (“SAW”) filters, which must be covered by a cap. The caps used for MEMS and SAW chips must be spaced from the front surface of the chip to an open gas-filled or vacuum void beneath the cap in the active area, so that the cap does not touch the acoustical or mechanical elements. Voltage controlled oscillators (VCOs) sometimes also require a cap to be placed over the active area.
Desirably, protective elements such as caps, lids or covers are added to such units by processing which is efficient and which provides reliable protection for the sensitive devices early in the packaging process. For example, protective elements can be provided for each chip by wafer level processing in which, for example, a lid wafer is assembled with a device wafer containing multiple chips which remain attached together. The assembled wafers can then be cut into individual units each containing a chip and a lid overlying the chip.
In accordance with an aspect of the invention, a lidded chip is provided which includes a chip having a major surface. Desirably, a plurality of first chip contacts are exposed at the major surface. A lid is provided such that it desirably overlies the major surface. A chip carrier is disposed between the chip and the lid. Desirably, an inner surface of the chip carrier confronts the major surface, such that an outer surface confronts the lid. A plurality of first carrier contacts of the chip carrier can be conductively connected to the first chip contacts, and a plurality of second carrier contacts can extend upwardly from a surface of the chip carrier, e.g., the outer surface, such that the second carrier contacts extend at least partially through the openings in the lid.
The chip can include an active region having an optoelectronic device. The lid may be at least partially transmissive to radiation at frequencies of interest to the optoelectronic devices or may be transparent to such radiation, e.g., light.
The chip carrier may have an opening permitting transmission of radiation at frequencies of interest between the major surface and a space above the chip carrier. A standoff structure may be provided for supporting an inner surface of the lid a distance from the major surface. In such way, a cavity may be defined between the inner and major surfaces.
Lateral dimensions of the major surface of the chip are desirably at least substantially the same as lateral dimensions of the lidded packaged chip. Second carrier contacts of the chip carrier may include metallic posts such that tips of the posts protrude above the outer surface of the lid. In an assembly including the lidded chip, a circuit panel can have terminals conductively joined to the exposed tips of the posts. In a particular embodiment, an inner surface of the lid may be bonded to the outer surface of the chip carrier.
In a lidded chip assembly in accordance with another embodiment of the invention, a chip is provided which has a major surface on which an active region including an optoelectronic device is desirably aligned with the major surface. Desirably, a plurality of contacts are exposed at the major surface. A lid overlies the active region. The lid has an inner surface confronting the major surface of the chip, an outer surface remote from the inner surface. Desirably, a plurality of through holes extend between the inner and outer surfaces. A plurality of conductive package interconnects may extend at least partially through the through holes. An interconnection element is typically included in the lidded chip assembly. Desirably, the interconnection element includes horizontal metal elements connected to the package interconnects and metal posts connected to the horizontal metal elements. The interconnection element may be disposed between the lid and the major surface. The horizontal metal elements may extend along the inner surface of the lid, such as, for example, for interconnecting the horizontal metal elements to the contacts on the chip. Typically, the horizontal elements include conductive traces extending along the interconnection element, although other types of horizontal conductive elements can be provided.
In accordance with another embodiment of the invention, a lidded chip is provided which includes a chip including an active region, the active region having an optoelectronic device, for example. The chip has a major surface and edges which extend away from the major surface. Desirably, a plurality of contacts are exposed at the major surface. A lid overlies the chip, the lid desirably having an inner surface which confronts the major surface of the chip. The lidded chip may further include an interconnection element having a dielectric layer, and lands exposed beyond the edges of the chip. Conductive traces may extend from the lands along the dielectric layer. Desirably, metal posts conductively connect the conductive traces to the contacts on the chip. A plurality of conductive metal bumps desirably extend from the lands away from the inner surface of the lid.
In accordance with another embodiment of the invention, a lidded chip is provided which includes a chip having a major surface, and desirably, an active region including an optoelectronic device at the major surface. Desirably, a plurality of chip contacts are provided at the major surface. A lid overlies the active region. An inner surface of the lid confronts the major surface of the chip. A plurality of package interconnects can be provided which are exposed at an exterior surface of the lidded chip. An interconnection element may be disposed between the inner surface of the lid and the major surface of the chip. Such interconnection element may include horizontal metal elements in conductive communication with the contacts and the package interconnects.
In a particular embodiment, the chip includes a plurality of active regions and the interconnection element includes a plurality of openings aligned with the active regions. The lid may further include through holes extending between the inner and outer surfaces. The package interconnects may extend from at least some of the chip contacts at least partially through the through holes.
Some or all of the chip contacts may be exposed beyond edges of the lid. The package interconnects may include some or all of the exposed chip contacts.
Some or all of the chip contacts may be exposed within recesses in edges of the lid. The package interconnects may include some or all of the exposed chip contacts.
In a particular embodiment, the lid may include through holes extending between the inner and outer surfaces and the package interconnects may be disposed adjacent to peripheral edges of the chip. For example, the package interconnects may be provided such that they extend from at least some of the chip contacts at least partially through the through holes.
In accordance with another aspect of the invention, a lidded microelectronic assembly is provided which includes a microelectronic element having a major surface, a first active region and a second active region at the major surface. First conductive pads are desirably provided, the first conductive pads being conductively connected to the first active region. Second conductive pads are desirably conductively connected to the second active region. A lid desirably overlies the first and second active regions. The lid has an inner surface which confronts the major surface. An outer surface of the lid is remote from the inner surface. Desirably, a plurality of through holes extend between the inner and outer surfaces. The assembly can include a plurality of package interconnects extending from the first and second conductive pads at least partially through the through holes. An interconnect element may overlie the lid, the interconnect element desirably including a dielectric element having a first surface confronting the lid, a second surface remote from the first surface, a plurality of first contacts at the first surface joined to the plurality of package interconnects, a plurality of second contacts exposed at the second surface, and a plurality of conductive traces extending along the first surface.
The conductive traces and the package interconnects of the lidded microelectronic assembly desirably connect the first conductive pads with the second conductive pads.
The package interconnects can include metallic posts extending downwardly from the first surface. The lidded microelectronic assembly may further include a second microelectronic element having third contacts. The third contacts may be conductively connected to the second contacts. Bond wires may conductively connect the third contacts to the second contacts.
Desirably, a front face of the second microelectronic element confronts the second surface of the interconnect element. A fusible metal may conductively connect the second and third contacts.
The first and second active regions may include optoelectronic devices. In such case, desirably, the lid is at least partially transmissive to radiation at frequencies of interest to the optoelectronic devices. The optoelectronic devices in at least one of the first or second active regions may include imaging sensor. The assembly may further include an optical element aligned with at least one of the first or second active regions.
The lid may include openings which are aligned with the first and second active regions.
In accordance with one or more aspects of the invention, a lidded microelectronic assembly is provided which includes a microelectronic element having a major surface. Desirably, a first active region and a second active region are provided at the major surface. First conductive pads can be provided, the first conductive pads being conductively connected to the first active region. Second conductive pads may be conductively connected to the second active region. Desirably, at least one lid overlies the first and second active regions. Desirably, the lid has an inner surface confronting the major surface, an outer surface remote from the inner surface and at least one channel extending between the inner and outer surfaces. Desirably, the channel exposes the first conductive pads and the second conductive pads. An interconnect element can be provided overlying the lid. Desirably, the interconnect element includes a dielectric element having a first surface remote from the lid, a second surface confronting the lid, and a plurality of first contacts conductively connected to the first and second conductive pads. The interconnect element may include a plurality of second contacts, and a plurality of conductive traces can be provided thereon or therein which extend parallel to the first surface. The conductive traces may connect the first and second contacts, for example.
In a lidded microelectronic assembly in accordance with an embodiment of the invention, the first and second contacts may be exposed at the first surface, and the lidded microelectronic assembly may further include bond wires. The bond wires may be used to conductively connect the first contacts to the first and second conductive pads.
The interconnect element may include locating features, such as protrude downwardly, for example, between the second surface and the outer surface of the lid. The locating features may include metallic posts, for example. The locating features may in some cases be bonded to the outer surface of the lid. The first contacts may include conductive features which extend downwardly between the second surface and the first and second conductive pads. For example, the first contacts may include metallic posts.
In a lidded microelectronic assembly in accordance with one or more aspects of the invention, a first microelectronic element has a major surface, an active region at the major surface and first conductive pads exposed at the major surface. Desirably, a lid overlies the active region, the lid having an inner surface confronting the major surface and an outer surface remote from the inner surface. The lid may have a plurality of through holes extending between the inner and outer surfaces. The lid may further have an opening extending between the inner and outer surfaces. A plurality of conductive interconnects may extend upwardly from the conductive pads at least partially through the through holes. A second microelectronic element can be provided which includes a rear face confronting the first microelectronic element within the opening. The second microelectronic element has a front face remote from the rear face and may have second conductive pads at the front face. The second conductive pads can be conductively connected to the conductive interconnects.
A plurality of lid contacts may be exposed at the outer surface of the lid. Conductive traces can be provided which connect the lid contacts to the conductive interconnects. Bond wires may conductively connect the second conductive pads to the lid contacts.
In accordance with an aspect of the invention, a lidded microelectronic assembly is provided which includes a first microelectronic element having a major surface, an active region at the major surface and first conductive pads exposed at the major surface. A lid overlies the active region, the lid having an inner surface confronting the major surface, an outer surface remote from the inner surface and edges extending between the inner and outer surfaces. The lid may further include lid contacts exposed at the outer surface. An opening may extend between the inner and outer surfaces. A plurality of recesses may be provided in at least one edge which exposes at least ones of the first conductive pads. A second microelectronic element may have a rear face confronting the first microelectronic element within the opening, and a front face remote from the rear face. Second conductive pads may be provided at the front face. Desirably, the first and second conductive pads are conductively connected to the lid contacts.
The lidded microelectronic assembly may further include bond wires which conductively connect the first and second conductive pads to the lid contacts. The lid contacts may include first lid contacts and second lid contacts, and the bond wires may include first bond wires and second bond wires. The first bond wires can conductively connect the first conductive pads to the first lid contacts and the second bond wires can conductively connect the second conductive contacts to the second lid contacts. The lidded microelectronic assembly may further include conductive traces connecting the first lid contacts to the second lid contacts.
In accordance with an aspect of the invention, a method is provided for fabricating a lidded packaged chip. In such method, a chip carrier can be assembled with a semiconductor chip to form a chip carrier assembly such that the chip carrier overlies a major surface of the chip. A plurality of first chip contacts of the chip can be conductively connected to a plurality of first carrier contacts of the chip carrier. In such packaged chip, the chip carrier can include a plurality of second conductive contacts protruding above a surface of the chip carrier remote from the chip. A lid may be mounted to the chip carrier assembly such that tips of the plurality of second conductive contacts protrude upwardly through openings in the lid. The tips of the second conductive contacts may be exposed above an outer surface of the lid remote from the chip carrier.
In mounting the lid to the chip carrier assembly, an inner surface of the lid may be supported a predetermined distance above the major surface of the chip.
In accordance with one or more particular aspects of the invention, second carrier contacts may include metallic posts such that tips of the posts protrude above the outer surface of the lid. The chip carrier may include a dielectric layer which defines a major surface. Each post of the plurality of posts may have a base proximate to the major surface and a tip remote from the base, such that the base occupies a first area in the plane of the major surface, and the tip occupies a second area in a plane parallel to the major surface. Desirably, the first area is greater than the second area. Each of the openings desirably occupies a third area greater than the second area and less then the first area. Desirably, the step of mounting the lid to the chip carrier assembly includes press-fitting the posts into the openings in the lid.
In accordance with one or more particular aspects of the invention, a surface of the chip carrier may be mounted to an inner surface of the lid with an adhesive. In one example, the surface of the chip carrier may be bonded to the inner surface of the lid before the chip carrier is assembled together with the chip.
When the chip includes an optoelectronic device, the lid desirably is either transparent to or is at least partially transparent to radiation, e.g., light, at wavelengths of interest, e.g., at wavelengths in visible, infrared or ultraviolet ranges or in a combination of such ranges. For example, for transparency in the visible wavelength range, the lid can consist essentially of glass. For example, the lid may include undoped or doped silicate glasses, quartz, polymers, certain metal oxides or other material transparent to visible light. On the other hand, when the chip includes an optoelectronic device which receives or emits infrared radiation or both, the lid can include another material such as silicon, among others, which is transparent to infrared wavelengths, even though such other material may not permit light of visible wavelength or other wavelengths to pass. Alternatively, when the device is a MEMs device or radio frequency device which does not need to transmit or receive radiation through the lid, the lid need not be especially transmissive. In fact, in the case of radio frequency devices, the lid 110 may need to provide electromagnetic shielding for the device 104. In such case, the lid may include or consist essentially of one or more metals, one or more conductive compounds of metals or both. When the lid consists essentially of a metal, e.g., copper, aluminum, silver, or other metal, for example, the lid can provide shielding for the device 104 from electric or magnetic fields external to the lidded chip. In addition, such metallic lid functions to shield other devices (not shown) disposed externally to the lidded chip from electric and magnetic fields generated by operation of the device 104.
As illustrated in
A feature of the embodiment shown in
Electrical interconnection between the chip contacts and external contacts 118 of the lidded chip is provided in accordance with a novel arrangement including an interconnect element 116. The interconnect element 116 can be variously referred to as an interposer, interconnect substrate, flexible circuit panel, or a “tape” typically having one or more metal layers, its function being to electrically interconnect the chip contacts 112 to external contacts 118 of the lidded chip 100. The interconnect element 116 includes a dielectric element 120 which desirably is capable of flexing under low to moderate stress or pressure. The dielectric element 120 can include a material such as polyimide or other polymeric material, for example. A metal layer disposed on one surface of the dielectric element includes a series of conductive traces 117.
From first pads 121, e.g., first ends of the traces 117, conductive bumps 122 including a fusible metal such as solder, tin or eutectic, extend downwardly from a lower surface 128 of the traces through the dielectric element 120 where the bumps 122 are joined to the contacts 112 of the chip 102. From other pads 125, e.g., second ends of the traces, conductive posts 132 extend upward from an upper surface 130 of the traces 112. The posts 132 extend upward at least partially through corresponding openings in the lid 110. Desirably, top surfaces 136 of the conductive posts extend above the top or “outer” surface 134 of the lid 110. The conductive posts 132 typically are solid metal features which consist essentially of one or more metals such as copper, nickel, platinum, palladium, aluminum, silver or other noble metal. Desirably, the posts consist essentially of one or more metals which has a melting temperature higher than that of a fusible metal 138 which may be provided on external surfaces of the posts for interconnection to other microelectronic elements, e.g., a circuit panel.
Typically, the conductive posts are formed by processing done prior to assembly of the interconnect element 116 to the chip 102 and lid 110. Desirably, the conductive posts can be formed by a subtractive process of etching a metal layer in accordance with a stencil or photolithographically defined photoresist patterns, e.g., by a process such as that described in commonly owned U.S. Pat. No. 6,826,827 to Fjelstad et al., or U.S. Pat. No. 6,528,874 to Iijima et al., the disclosures of which are hereby incorporated herein. Alternatively, the conductive posts can be formed by an additive process of plating a metal within predefined openings in a patterned photoresist layer or dielectric layer, as also described in the above-referenced incorporated U.S. patents. In another variation, the conductive posts 132 are solid metal conductive stud bumps formed as by a wire-bonding tool or tool designed specifically for forming stud bumps.
As further shown in
Typically, lids made of glass, metal, silicon or other semiconductor material provide a greater degree of impenetrability than lids made of polymeric material. To help achieve hermeticity, the support structure 114 may also consist essentially of metal, glass, silicon or other semiconductor material. In a particular embodiment, the lid 110 and support structure 114 may be provided as one unitary member having uniform composition of metal, glass, silicon, or other semiconductor material, in which the cavity 106 is provided as a recessed portion within the unitary member. However, the lid and the support structure need not be of the same material. For example, a metallic support structure can be used to both support and seal a glass, semiconductor or metal lid 110 above the front surface 101 of the chip. A glass support structure, formed, for example, by a low melting temperature glass can be used to support and seal lids having glass, semiconductor or metal composition. Even a support structure consisting essentially of semiconductor material can be used to support and seal a metallic lead to a corresponding metal feature such as a seal ring at the front surface of the chip.
On the other hand, certain other devices do not require hermetic seals. Most optoelectronic devices, such as imaging devices, e.g., charge-coupled device (“CCD”) arrays, are protected from spoilage by a lid from dust and other contamination, but usually do not need to be enclosed in hermetically sealed packages. In such case, the external contacts 118 may not even need to form a seal with the openings in the lid at the conductive posts. When the openings do not require seals, the wettable metal layer 140 also may not need to be provided on walls of the openings in the lid.
In addition, when the posts 132 are press-fitted into the openings, it may be possible to obtain a packaged device having a lower profile, i.e., a smaller thickness 142 in a direction from the outer surface 144 of the lid 110 to a rear surface 146 of the chip. The decreased thickness results because the distance between an outer surface 148 of the metal layer 117 and an inner surface 108 of the lid is reduced or eliminated.
As seen in
In another variation of the embodiment illustrated in
In yet another variation, the width of the interconnect element can be greater such that the interconnect element extends the entire width 160 of the chip 102 in the direction shown. In a particular embodiment, the interconnect element desirably extends across the entire width of the chip in at least one lateral direction when the assembly illustrated in
In the embodiment illustrated in
As noted above, the metal layer of the interconnect element illustrated in FIGS. 6 and 7-8 has a “circuits-in” configuration. Namely, the traces 317 and contacts of the interconnect element 316 are provided at a lower surface 322 of the dielectric layer 320 and face the front surface 101 of the chip. In a variation of the embodiments illustrated in FIGS. 6 and 7-8, the positions of the metal layer and dielectric element of the interconnect element can be reversed to provide a “circuits-out” arrangement in which the metal layer is provided at an upper surface 323 (
Conductive masses 538 are attached to the lands. The conductive masses include, for example, solder balls or bumps of fusible conductive material, other conductive material, or a combination of fusible and other conductive material. The conductive masses may include nonconductive elements as well, such as polymeric cores, etc., which may be coated with conductive, e.g., fusible or nonfusible metals, or combination of such. The conductive masses extend downward such that surfaces of the masses define a reference plane 550 which lies at a greater distance from the lower surface 508 of the lid 510 than the distance of the rear surface 503 of the chip 502 from that lower surface 508.
The structure illustrated in
Alternatively, when contamination concerns are not as great, the conductive masses 538 be applied to the interconnect element after the interconnect element is joined to the lid but before the chip is joined to the interconnect element.
In a lidded chip assembly 600 (
The wettable metal layer 609 on the bond pads and through holes typically includes a diffusion barrier layer which includes a metal or metal compound or both which is deposited in contact with a base metal such as copper or aluminum. In an example, zinc, tungsten, titanium or various nitrides of tungsten or titanium can be used as the diffusion barrier layer. Typically, then, at least one layer including a metal wettable by the fusible or flowable conductive material is deposited to overlie the diffusion barrier layer. The wettable metal layer may include a diffusion barrier layer including zinc, over which layers of nickel and then gold are deposited, such as by electroless deposition. In an example, the thickness of the diffusion barrier layer is about 0.1 micron (μm), the thickness of the nickel layer is between about three and about five microns, and the thickness of the gold layer is about 0.1 microns.
The wettable metal layer 609 may be formed after depositing an initial layer of aluminum on walls of through holes 604, on bond pads 608, or both, such as by a sputtering process or various vapor deposition processes. Alternatively, such aluminum layer can be deposited by chemical electrodeposition or electroless deposition. A seed material including palladium or other material can be used in such deposition processes. When deposited by sputtering or other vapor deposition, silicon or copper or both may be incorporated into the deposited layer to help control the size of deposited grains and subsequent growth of the grains. Desirably, the aluminum layer is deposited at a stage of fabrication after a lid wafer including the lid 610 is joined to a device wafer which includes the chip 602. In an example, the aluminum layer deposited at this stage of fabrication may have a nominal thickness of about 5 microns (μm).
Desirably, the aluminum layer is deposited onto the bond pads and walls of the through holes after any surface oxides, e.g., native oxides, or other dielectrics or contaminants are removed from exposed surfaces of the bond pads. In one example, about 30% of the thickness of the deposited aluminum layer is removed by such cleaning process. Reverse bias sputtering, fast atom bombardment or other cleaning technique, among others, can be used to prepare the surface of the bond pads. In such way, the layer of deposited aluminum forms an ohmic connection with the bond pads.
In a particular embodiment, a quantity of conductive paste, e.g., solder paste, etc., may be applied to the wettable metal layer 609 before introducing solder into the through holes to form the conductive interconnects 612. The solder paste can be applied to the wettable layer 609 on the bond pads 608, such as by screening or stenciling from above the lid 610. In this way, the solder paste can bridge the gap between the front surface 601 of the chip and the inner surface of the lid. When the solder is applied through the outer surface of the lid by causing solder balls to come to rest in the through holes as described in the incorporated U.S. patent application Ser. No. 10/949,674, heating the substrate causes the solder of the solder balls to melt, wet the wettable metal layer 609 and merge with the flowing solder paste applied to the bond pads 608.
In a particular process which does not require the application of a solder paste, the gap can be bridged by making the wettable metal layer thicker. For example, the thickness of the wettable metal layer can be increased by depositing the nickel layer thereof to a greater thickness such as 10 to 20 microns, a thickness comparable to the height of the gap needed for many lidded chip packages.
A layer 614 including an adhesive overlies the front surface 601 of the chip between the chip 602 and the lid 610, an opening being provided in the layer such that a device region 616 of the chip is exposed. Away from the device region, an opening 606 is provided in the lid in which a secondary chip or element is mounted to the layer 614. A heat conducting element 620, which can be referred to variously as a heat spreader or thermal conductor, for example, is disposed between a rear surface 622 of the secondary element 618 and layer 614. In this way, the heat spreader 620 conducts heat away from the secondary element 618 into the base chip 602. First contacts 626 are provided at a front surface 624 of the secondary element and are conductively connected to second contacts 628 on a top surface 611 of the lid by bond wires 630.
In this embodiment, a single lid 810 overlies each of the device regions 816a, 816b for protection against dust or other contamination. Conductive interconnects 812a, 812b extend upward through through holes in the lid 810, the conductive interconnects being exposed at the outer surface 811 of the lid. Desirably, external electrical interconnection for a first device region 816a is available through conductive interconnects 812a and external electrical interconnection for a second device region 816b is available through conductive interconnects 812b.
As shown in
The conductive interconnects 912 can be formed, for example, by a process such as that described in commonly owned application Ser. No. 10/949,674 (incorporated herein). As described in that application, masses of fusible material, e.g., solder, tin or eutectic composition are allowed to flow into the through holes after joining the lid to the chip with the dielectric element interposed between them. Alternatively, the conductive interconnects can be formed by other techniques such as, without limitation, plating or conductive paste screening, or a combination thereof.
The dielectric element has an inner surface 1121 confronting the lidded chip assembly 800 and an outer surface 1123 facing away from the lidded chip assembly. Windows 1160, i.e., openings extending through the dielectric element from the inner surface to the outer surface, are provided for passage of light or other electromagnetic signal energy to device regions of the lidded chip assembly.
The contacts include inner contacts 1122 at the inner surface which are joined to conductive interconnects 1112 of the lidded chip assembly 800. The interconnect element 1120 further includes outer contacts 1124 at the outer surface available to provide conductive interconnection to a circuit panel, such as through bond wires (not shown) from those contacts to terminals of a circuit panel, similar to the terminals 1048 of the circuit panel 1046 shown in
In a further variation (
In a further variation, a microelectronic element 1450 (
Similar to the embodiment described above with respect to
Another variation is illustrated in
As these and other variations and combinations of the features discussed herein can be utilized without departing from the present invention, the foregoing description of the preferred embodiments should be taken by way of illustration rather than by way of limitation of the invention as defined by the claims.
