Claims
- 1. A method of forming a package for an integrated circuit device comprising:
providing a plastic sheet having a first surface; applying a first metal layer to the first surface of the plastic sheet; patterning the first metal layer so as to form an array of package sites, wherein each package site formed includes a die pad and a plurality of leads adjacent to the die pad; placing an integrated circuit device on each die pad of the array; electrically connecting each integrated circuit device to at least some of the leads adjacent to the die pad on which the integrated circuit device is placed; applying an encapsulating material onto the array and the first surface of the plastic sheet so that each package site is encapsulated; removing the plastic sheet from the array, and separating individual packages from the encapsulated array, wherein a planar first surface of the die pad and leads of the packages is exposed at an external surface of each package.
- 2. The method of claim 1, wherein removing the plastic sheet comprises using a solvent to dissolve a connection between the array and the plastic sheet so that the plastic sheet may be separated from the array.
- 3. The method of claim 2, wherein an adhesive material is applied to the first surface of the plastic sheet prior to application of the metal layer.
- 4. The method of claim 1, wherein applying the first metal layer to the first surface of the plastic sheet comprises:
providing a sheet of metal: and attaching the sheet of metal to the first surface of the plastic sheet with an adhesive.
- 5. The method of claim 4, wherein removing the plastic sheet comprises using a solvent to dissolve a connection between the array and the plastic sheet so that the plastic sheet may be separated from the array.
- 6. The method of claim 1, wherein the first metal layer comprises a layer of one type of metal plated with one or more layers of another type of metal.
- 7. The method of claim 1, wherein patterning the metal layer comprises:
applying a second metal layer in a pattern on the first metal layer, wherein the pattern of the second metal layer defines said package sites; and selectively etching the first metal layer to form said package sites using said second metal layer as a mask.
- 8. The method of claim 7, wherein the first metal layer comprises copper and the second metal layer is gold.
- 9. The method of claim 8, wherein the first metal layer comprises a layer of copper and a layer of nickel, wherein said gold is applied onto said layer of nickel.
- 10. A method of forming a package for an integrated circuit device comprising:
providing a substrate sheet having a first surface; applying a first layer of an electrically conductive material on the substrate sheet, wherein said first layer is applied in a pattern that defines an array of package sites, wherein each package site formed includes a die pad and a plurality of leads adjacent to the die pad; placing an integrated circuit device on each die pad of the array; electrically connecting each integrated circuit device to at least some of the leads adjacent to the die pad on which the integrated circuit device is placed; applying an encapsulating material onto the array and the first surface of the substrate sheet so that each package site is encapsulated; removing the substrate sheet from the array, and separating individual packages from the encapsulated array, wherein a planar first surface of the die pad and leads of the packages is exposed at an external surface of the package.
- 11. The method of claim 10, further comprising applying a second layer of an electrically conductive material on the die pads and leads so that the second layer overhangs the first layer.
- 12. The method of claim 11, wherein the substrate sheet is a plastic material.
- 13. The method of claim 12, wherein the first and second layers of electrically conductive material are applied by silk screening.
- 14. The method of claim 12, wherein the first and second layers of electrically conductive material are applied using a stencil.
- 15. A method of forming a package for an integrated circuit device comprising:
providing a plastic sheet having a first surface; applying a metal layer to the first surface of the first plastic sheet; patterning the metal layer to form a die pad and a plurality of leads adjacent to the die pad; placing an integrated circuit device on the die pad; consecutively connecting the integrated circuit device to one or more of the leads; applying an encapsulating material so that the integrated circuit device and the first surface of the plastic sheet are covered by the encapsulant material; and removing the plastic sheet, wherein a planar first surface of the die pad and a first surface of the leads are exposed at an exterior surface of the package.
- 16. The method of claim 15, wherein removing the plastic sheet comprises using a solvent to dissolve a connection between the die pad and leads and the plastic sheet so that the plastic sheet may be separated therefrom.
- 17. The method of claim 15, wherein applying the first metal layer to the first surface of the plastic sheet comprises:
providing a sheet of metal: and attaching the sheet of metal to the first surface of the plastic sheet with an adhesive.
- 18. The method of claim 15, wherein patterning the metal layer comprises:
applying second metal layer in a pattern on the first metal layer, wherein the pattern of the second metal layer defines said package sites; and selectively etching the first metal layer to form said package sites using said second metal layer as a mask.
- 19. The method of claim 18, wherein the first metal layer comprises copper and the second metal layer is gold.
- 20. A method of forming a package for an integrated circuit device comprising:
providing a substrate sheet having a first surface; applying a first layer of a electrically conductive material on the substrate sheet, wherein said first layer is applied in a pattern that defines an array of package sites, wherein each package site formed includes a die pad and a plurality of leads adjacent to the die pad; placing an integrated circuit device on the die pad; consecutively connecting the integrated circuit device to one or more of the leads; applying an encapsulating material so that the integrated circuit device and the first surface of the substrate sheet are covered by the encapsulant material; and removing the substrate sheet, wherein a planar first surface of the die pad and a first surface of the leads are exposed at an exterior surface of the package.
- 21. The method of claim 20, further comprising applying a second layer of an electrically conductive material on the die pads and leads so that the second layer overhangs the first layer.
- 22. The method of claim 21, wherein the substrate sheet is formed of a plastic material, and the plastic sheet is removed by peeling or dissolving the plastic sheet in a solvent.
- 23. The method of claim 21, wherein the substrate sheet is formed of a plastic material, and an adhesive connection between the plastic sheet and the encapsulated array is dissolved with a solvent.
- 24. The method of claim 1, wherein removing the plastic sheet includes subjecting the plastic sheet to ultraviolet light.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 09/383,022 (attorney docket M-5311 US), which is entitled “Method of Forming an Integrated Circuit Package Using Plastic Tape as a Base” and was filed on Aug. 25, 1999.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09504007 |
Feb 2000 |
US |
Child |
09863359 |
May 2001 |
US |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09383022 |
Aug 1999 |
US |
Child |
09504007 |
Feb 2000 |
US |