Patent Grant
11064609
The present invention relates generally to structures and methods for electrically interconnecting chiplets using micro-transfer printing.
Substrates with electronically active components distributed over the extent of the substrate may be used in a variety of electronic systems, for example, flat-panel imaging devices such as flat-panel liquid crystal or organic light emitting diode (OLED) display devices and in flat-panel solar cells. A variety of methods may be used to distribute electronically active circuits over substrates, including forming the electronically active circuits on a substrate and forming the components on separate substrates and placing them on a substrate. In the latter case, a variety of assembly technologies for device packaging may be used.
The electronically active components are typically formed on a substrate by sputtering a layer of inorganic semiconductor material or by spin-coating organic material over the entire substrate. Inorganic semiconductor materials can be processed to improve their electronic characteristics, for example amorphous silicon can be treated to form low-temperature or high-temperature poly-crystalline silicon. In other process methods, microcrystalline semiconductor layers can be formed by using an underlying seeding layer. These methods typically improve the electron mobility of the semiconductor layer. The substrate and layer of semiconductor material can be photo-lithographically processed to define electronically active components, such as transistors. Such transistors are known as thin-film transistors (TFTs) since they are formed in a thin layer of semiconductor material, typically silicon. Transistors may also be formed in thin layers of organic materials. In these devices, the substrate is often made of glass, for example Corning Eagle® or Jade® glass designed for display applications.
The above techniques have some limitations. Despite processing methods used to improve the performance of thin-film transistors, such transistors may provide performance that is lower than the performance of other integrated circuits formed in mono-crystalline semiconductor material. Semiconductor material and active components can be provided only on portions of the substrate, leading to wasted material and increased material and processing costs. The choice of substrate materials can also be limited by the processing steps necessary to process the semiconductor material and the photo-lithographic steps used to pattern the active components. For example, plastic substrates have a limited chemical and heat tolerance and do not readily survive photo-lithographic processing. Furthermore, the manufacturing equipment used to process large substrates with thin-film circuitry is relatively expensive. Other substrate materials that may be used include quartz, for example, for integrated circuits using silicon-on-insulator structures as described in U.S. Patent Application No. 2010/0289115 and U.S. Patent Application No. 2010/0123134. However, such substrate materials can be more expensive or difficult to process.
Other methods used for distributing electronically functional components over a substrate in the circuit board assembly industry include, for example, pick-and-place technologies for integrated circuits provided in a variety of packages, for example, pin-grid arrays, ball-grid arrays, and flip-chips. However, these techniques may be limited in the size of the integrated circuits that can be placed.
In further manufacturing techniques, a mono-crystalline semiconductor wafer is employed as the substrate. While this approach can provide substrates with the same performance as integrated circuits, the size of such substrates may be limited, for example, to a 12-inch diameter circle, and the wafers are relatively expensive compared to other substrate materials such as glass, polymer, or quartz.
In yet another approach, thin layers of semiconductor are bonded to a substrate and then processed. Such a method is known as semiconductor-on-glass or silicon-on-glass (SOG) and is described, for example, in U.S. Pat. No. 7,605,053, issued Oct. 20, 2009. If the semiconductor material is crystalline, high-performance thin-film circuits can be obtained. However, the bonding technique and the processing equipment for the substrates to form the thin-film active components on large substrates can be relatively expensive.
Publication No. 11-142878 of the Patent Abstracts of Japan entitled Formation of Display Transistor Array Panel describes etching a substrate to remove it from a thin-film transistor array on which the TFT array was formed. TFT circuits formed on a first substrate can be transferred to a second substrate by adhering the first substrate and the TFTs to the surface of the second substrate and then etching away the first substrate, leaving the TFTs bonded to the second substrate. This method may require etching a significant quantity of material, and may risk damaging the exposed TFT array.
Other methods of locating material on a substrate are described in U.S. Pat. No. 7,127,810. In this approach, a first substrate carries a thin-film object to be transferred to a second substrate. An adhesive is applied to the object to be transferred or to the second substrate in the desired location of the object. The substrates are aligned and brought into contact. A laser beam irradiates the object to abrade the transferring thin film so that the transferring thin film adheres to the second substrate. The first and second substrates are separated, peeling the film in the abraded areas from the first substrate and transferring it to the second substrate. In one embodiment, a plurality of objects is selectively transferred by employing a plurality of laser beams to abrade selected area. Objects to be transferred can include thin-film circuits.
U.S. Pat. No. 6,969,624 describes a method of transferring a device from a first substrate onto a holding substrate by selectively irradiating an interface with an energy beam. The interface is located between a device for transfer and the first substrate and includes a material that generates ablation upon irradiation, thereby releasing the device from the substrate. For example, a light-emitting device (LED) is made of a nitride semiconductor on a sapphire substrate. The energy beam is directed to the interface between the sapphire substrate and the nitride semiconductor releasing the LED and allowing the LED to adhere to a holding substrate coated with an adhesive. The adhesive is then cured. These methods, however, may require the patterned deposition of adhesive on the object(s) or on the second substrate. Moreover, the laser beam that irradiates the object may need to be shaped to match the shape of the object, and the laser abrasion can damage the object to be transferred. Furthermore, the adhesive cure takes time, which may reduce the throughput of the manufacturing system.
Another method for transferring active components from one substrate to another is described in AMOLED Displays using Transfer-Printed Integrated Circuits published in the Proceedings of the 2009 Society for Information Display International Symposium Jun. 2-5, 2009, in San Antonio Tex., US, vol. 40, Book 2, ISSN 0009-0966X, paper 63.2 p. 947. In this approach, small integrated circuits are formed over a buried oxide layer on the process side of a crystalline wafer. The small integrated circuits, or chiplets, are released from the wafer by etching the buried oxide layer formed beneath the circuits. A PDMS stamp is pressed against the wafer and the process side of the chiplets is adhered to the stamp. The chiplets are pressed against a destination substrate or backplane coated with an adhesive and thereby adhered to the destination substrate. The adhesive is subsequently cured. In another example, U.S. Pat. No. 8,722,458 entitled Optical Systems Fabricated by Printing-Based Assembly teaches transferring light-emitting, light-sensing, or light-collecting semiconductor elements from a wafer substrate to a destination substrate or backplane.
In such methods it is generally necessary to electrically connect the small integrated circuits or chiplets to electrically conductive elements such as backplane contact pads on the destination substrate. By applying electrical signals to conductors on the destination substrate the small integrated circuits are energized and made operational. The electrical connections between the small integrated circuits and the backplane contact pads are typically made by photolithographic processes in which a metal is evaporated or sputtered onto the small integrated circuits and the destination substrate to form a metal layer, the metal layer is coated with a photoresist that is exposed to a circuit connection pattern, and the metal layer and photoresist are developed by etching and washing to form the patterned electrical connections between the small integrated circuits and the connection pads on the destination substrate. Additional layers, such as interlayer dielectric insulators can also be required. This process is expensive and requires a number of manufacturing steps. Moreover, the topographical structure of the small integrated circuits over the destination substrate renders the electrical connections problematic, for example it can be difficult to form a continuous conductor from the destination substrate to the small integrated circuit because of the differences in height over the surface between the small integrated circuits and the destination substrate.
As integrated circuit technology progresses, ever-smaller features are used in electronic elements such as transistors and interconnections to reduce power, improve switching speed, and increase density. To increase density further, some electronic systems use stacked integrated circuits, for example as taught in U.S. Patent Publication No. 20010033030. However, these structures require packaged integrated circuits and thermal diffusion bond layers, increasing the size and interconnection complexity of the structure. Other methods use stacked die layers with through interconnects, for example as discussed in U.S. Patent Publication No. 20130293292, but construction of through interconnections, for example with through silicon vias, is difficult. Other methods employ interface wafers with through silicon vias to interconnect bonded active-circuitry wafers (U.S. Patent Publication No. 20100044826) or integrated circuits (U.S. Patent Publication No. 20120313207) but these are limited in the number of layers that can be interconnected.
There is a need, therefore, for structures and methods that enable the electrical interconnection of small integrated circuits, such as printable chiplets, in simple, inexpensive, extensible, and flexible ways that enable robust, three-dimensional electronic or opto-electronic structures.
The present invention provides, inter alia, structures and methods for electrically connecting relatively small electrical components such as integrated circuit chiplets in a simple, efficient, extensible, flexible, and cost-effective way that enables robust, three-dimensional electronic or opto-electronic structures. The integrated circuit chiplets (chiplets) can be electrically connected to a destination substrate or one chiplet can be electrically connected directly to another chiplet, for example in a three-dimensional stack of chiplets.
In accordance with some embodiments of the present invention, a micro-transfer printable electronic component includes a component substrate and a circuit disposed in or on the component substrate, one or more electrically conductive connection posts protruding from the component substrate, and one or more electrically conductive exposed component contact pads on or over the component substrate on a side of the component substrate opposite the one or more connection posts. The one or more component contact pads and the one or more electrically conductive connection posts are both electrically connected to the circuit.
In some embodiments, a printed electronic structure includes at least first and second printable electronic components and at least one of the connection posts of the second component is in electrical contact with at least one of the component contact pads of the first component. In some embodiments, connection posts and contact pads of the first and second components are disposed in spatially corresponding locations and can be aligned in a direction orthogonal to the component surface so that the second component can be micro-transfer printed onto and electrically connected with the first component. In some embodiments, a component is micro-transfer printed with aligned connection posts and contact pads onto two or more other components. Different components (e.g., directly electrically connected components) can be spatially offset from each other in one dimension, two dimensions or three dimensions. In some embodiments, connection posts are aligned and in electrical contact with destination substrate contact pads on a destination substrate. In certain embodiments, two or more component contact pads are spatially separated from each other as disposed on a component substrate.
In various configurations, a component substrate has at least one of a width, length, and height from 1 to 2 μm, 2 to 5 μm, 5 to 10 μm, 10 to 20 μm, or 20 to 50 μm.
In accordance with some embodiments of the present invention, a micro-transfer printable component source wafer includes a wafer substrate having one or more sacrificial portions spaced apart by anchor portions and a component disposed entirely over each sacrificial portion and connected to at least one anchor portion by one or more tethers. A wafer substrate can be anisotropically etchable and each sacrificial portion can be a designated portion of the wafer substrate. In some embodiments, each sacrificial portion comprises sacrificial material that is differentially etchable from the wafer substrate, or the sacrificial portion can be a gap between a component and the wafer substrate.
In some embodiments, a circuit is a passive circuit, includes only wires, includes resistors, includes capacitors, is a capacitor, or is an active circuit including one or more transistors.
In some embodiments, components have the same circuits, the same number or disposition of contact pads, or the same number or disposition of connection posts. In some embodiments, the components have different circuits, different numbers or dispositions of contact pads, or different numbers or dispositions of connection posts.
A method of making a micro-transfer printed electronic structure according to some embodiments of the present invention includes providing a micro-transfer printable component source wafer, providing a destination substrate having one or more destination substrate contact pads, and providing one or more micro-transfer printing stamps. At least a first component is micro-transfer printed from the source wafer to the destination substrate using a stamp. At least one connection post of the first component is aligned and in electrical contact with at least one destination substrate contact pad. At least a second component is micro-transfer printed from the source wafer to the first component using a stamp and at least one connection post of the second component is aligned and in electrical contact with at least one component contact pad of the first component.
In some embodiments, the second component is micro-transfer printed so that each connection post of the second component is aligned and in electrical contact with at least one component contact pad of the first component. In another embodiment, at least a third component is micro-transfer printed from a component source wafer to the destination substrate using a stamp before micro-transfer printing the second component. At least one connection post of the third component is aligned and in electrical contact with at least one destination substrate contact pad. The second component is micro-transfer printed so that at least one connection post of the second component is aligned and in electrical contact with at least one component contact pad of the third component.
In some embodiments, a micro-transfer printable electronic component includes a component substrate and a plurality of capacitors formed in or on the component substrate. In some embodiments, capacitors are electrically connected in parallel and have first and second capacitor terminals. First and second electrically conductive connection posts protrude from the component substrate. The first connection post is electrically connected to the first capacitor terminal and the second connection post is electrically connected to the second capacitor terminal separately from the first terminal. In some embodiments, capacitors are vertical capacitors. In some embodiments, capacitors are horizontal capacitors. The capacitors can be formed in or on a side of the component substrate opposite the connection posts or within the component substrate.
In some embodiments of the present invention, two or more directly electrically connected connection posts are provided to contact a common destination substrate contact pad. In some embodiments, two or more directly electrically connected contact pads are provided to contact one or more directly electrically connected connection posts. By providing two or more connection posts in contact with a common destination substrate contact pad or providing two or more component contact pads in contact with a commonly electrically connected connection posts, faults in electrical connections between the component and the destination substrate contact pad or component contact pads are reduced by providing redundant electrical connections.
The present invention provides, inter alia, structures and methods that enable the construction of electrical interconnections between small integrated circuits that are printed (e.g., micro-transfer printed) onto each other or onto a destination substrate. In certain embodiments, the electrical interconnection process is simple and inexpensive requiring fewer process steps than known alternative methods and provides a robust, three-dimensional electronic structure that is indefinitely expandable in a variety of configurations and circuits.
The foregoing and other objects, aspects, features, and advantages of the present disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:
The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not drawn to scale since the variation in size of various elements in the Figures is too great to permit depiction to scale.
The present invention provides, inter alia, structures and methods for electrically connecting relatively small electrical components such as integrated circuit chiplets in a simple, efficient, extensible, flexible, and cost-effective way. The integrated circuit chiplets (chiplets) can be electrically connected to a destination substrate or one chiplet can be electrically connected directly to another chiplet, for example in a three-dimensional stack of chiplets, or to three or more chiplets, forming a three-dimensional electronic structure.
Referring to the cross section of
In certain embodiments, components 10 of the present invention can be micro-transfer printed. Micro-transfer printing can transfer very small integrated circuit chiplets from a source wafer to a destination substrate. Other methods, such as pick-and-place or surface-mount techniques cannot transfer such small components 10. In some embodiments of the present invention, the component substrate 12 has at least one of a width, length, and height from 1 to 2 μm, 2 to 5 μm, 5 to 10 μm, 10 to 20 μm, or 20 to 50 μm.
The circuit 14 can, optionally, include circuit contact pads 13 designating electrical connections to the circuit 14. The electrodes 18 can be electrical conductors electrically connected to the component contact pads 19 or the connection posts 16, or both (as shown in
The connection posts 16 can be electrically connected to the circuit 14 separately from the component contact pads 19 or directly electrically connected in common to the circuit 14 and component contact pads 19 (as shown in
Referring to
A component substrate 12 can be any substrate on which circuits 14, electrodes 18, insulating layers or patterned dielectric structures 15, and electrical conductors (e.g., electrodes 18) can be formed, for example a semiconductor substrate or a glass or plastic substrate as found in the display or integrated circuit industries. The component substrate 12 can be rigid or flexible as well as transparent or opaque. Electrodes 18 can be any patterned electrical conductor, for example electrically conductive metal wires or traces, can be metal oxide conductors, or can be organic conductors and can be transparent or opaque, and can be provided in various widths, materials, and thicknesses.
A circuit 14 can be formed in or on a component substrate 12, and can include, for example, transistors formed in or on a semiconductor component substrate 12 or electrodes 18 formed in or on a semiconductor, glass, or plastic component substrate 12. In some embodiments, a circuit 14 can be formed in a circuit substrate separate from a component substrate 12 and disposed on the component substrate 12, for example, by micro-transfer printing the circuit substrate from a circuit substrate source wafer to the component substrate 12. Circuit connection pads 13 can be metallized or otherwise electrically conductive portions of the component substrate 12 or the circuit substrate (if present), or can simply be designated portions of the component substrate 12 or the circuit substrate (if present) or a designated portion of the circuit 14 to which the electrodes 18 are electrically connected.
In various embodiments of the present invention, a circuit 14 is a passive circuit. For example, the circuit 14 can include only wires and only provide electrical connections. For example, in some embodiments, a circuit 14 forms an electrical jumper or electrical pass-through from a connection post 16 to a component contact pad 19. In some embodiments, a circuit 14 is an active circuit including one or more transistors or diodes, for example, light-emitting diodes. A circuit 14 can include resistors or capacitors or be a resistor or capacitor, or include multiple capacitors or resistors electrically connected in series or in parallel. In some embodiments, a circuit 14 comprises both passive and active elements.
Connection posts 16 are electrically conductive and can include a non-conductive structure coated with an electrically conductive layer, such as a metal layer. Connection posts 16 can protrude from a component substrate 12 in a direction orthogonal to the component surface 17 of the component substrate 12. The connection posts 16 can be a spike and have a point with a smaller area than a base adjacent to the component substrate 12.
In some embodiments, and as shown in
Referring to
Multiple directly electrically connected connection posts 16 can be electrically connected to a common destination substrate contact pad 22. Electrically separate connection posts 16 can be electrically connected to electrically separate destination substrate contact pads 22 (as shown in
An adhesive layer 24 can be coated in a pattern over the destination substrate contact pads 22 or, as shown in
Referring to
The first and second components 10A, 10B can have the same structure and circuit 14 or can have different structures and circuits 14. For example, in some embodiments, the circuit 14 in both of first and second components 10A, 10B are capacitors and the capacitors are electrically connected in parallel (as shown in
Referring to
Electronic structures 50 in accordance with certain embodiments of the present invention can be extended to a wide variety of components 10 and stacking configurations. Referring to
The electronic structure 50 illustrated in
In the illustrative embodiments of
Different components 10 can have different sizes (in contrast to their same-sized representation in the figures), include different numbers of connection posts 16, or include different numbers of component contact pads 19. The number of electrically separate connection posts 16 can be different from the number of electrically separate component contact pads 19 in a component 10. Components 10 can comprise different materials, be made in different processes, and have different structures.
Components 10 in accordance with certain embodiments of the present invention can be micro-transfer printed from a micro-transfer printable component source wafer 60. An exemplary micro-transfer printable component source wafer is shown in
The substrate of the component source wafer substrate 61 can be silicon, glass, ceramic, plastic or another wafer material suitable for photolithographic processing. In some embodiments, a circuit 14 is an active circuit and a substrate 61 of the component source wafer is a semiconductor. In some embodiments, a circuit 14 is a light-emitting circuit (for example including a light-emitting diode) and a substrate of the component source wafer substrate 61 is sapphire or a compound semiconductor. In some embodiments, a circuit 14 is a passive circuit and a substrate of the component source wafer substrate 61 is glass, ceramic, or plastic.
In various embodiments of the present invention, a component source wafer substrate 61 and sacrificial portion 62 include various materials. In some embodiments, a substrate 61 of the component source wafer 60 is anisotropically etchable (for example silicon {1 1 1}) and each sacrificial portion 62 is a designated portion of the component source wafer substrate 61. In some embodiments, each sacrificial portion 62 comprises sacrificial material (e.g., silicon dioxide) that is differentially etchable from the component source wafer substrate 61. In some embodiments, sacrificial portion 62 is an empty space forming a gap (as shown in
Illustrative methods of making certain embodiments of the present invention are illustrated in
Referring to
This generic process can be used to make a variety of components 10 having different circuits 14 and having differently patterned conductive layers 66. Referring to
Component contact pads 19 can be specially constructed (for example as a metallized area) or simply be designated portions of the electrodes 18. Referring to
Referring to
The capacitor components 10, 70 of the micro-transfer printable component source wafer 60 can be micro-transfer printed to a destination substrate 20, as shown in
Referring next to the flow charts of
Referring to the illustrative embodiment shown in
Referring to the illustrative embodiment shown in
In some embodiments of the present invention, a capacitive micro-transfer printable electronic component 10 does not necessarily include a component contact pad 19. An illustrative embodiment without a separate contact pad component 19 is shown in
A component 10 can be an active component, for example including one or more active elements such as electronic transistors or diodes or light-emitting diodes and photodiodes that produce an electrical current in response to ambient light. In some embodiments, a component 10 is a passive component, for example including one or more passive elements such as resistors, capacitors, or conductors. In some embodiments, a component 10 is a compound component 10 that includes both active and passive elements. A component 10 can be a semiconductor device having one or more semiconductor layers 11, such as an integrated circuit. A component 10 can be an unpackaged die. In some embodiments, a component 10 is a compound element having a plurality of active or passive elements, such as multiple semiconductor devices with separate substrates, each with one or more active elements or passive elements, or both. In certain embodiments, a plurality of elements is disposed and interconnected on a compound element substrate separate from the substrates of any semiconductor or other device or structure. The compound element can be micro transfer printed itself after the elements have been arranged thereon. Components 10 can be electronic processors, controllers, drivers, light-emitting diodes, photodiodes, light-control devices, or light-management devices.
Components 10 can include active elements such as electronic circuits 14 formed using lithographic processes and can include passive elements such as electrical connections (e.g., wires) to component contact pads 19 and connection posts 16. In certain embodiments, component contact pads 19 are planar electrical connections formed on a process side of the component 10 (e.g., a process side of a micro-transfer printable component source wafer 60). Such component contact pads 19 are typically formed from metals such as aluminum or polysilicon using masking and deposition processes used in the art. In certain embodiments, component contact pads 19 are electrically connected to a circuit 14 with wires or electrodes 18. In some embodiments, component contact pads 19 are directly electrically connected to a circuit 14 without intervening wires. In some embodiments, component contact pads 19 and a circuit 14, together with other functional structures formed in the active layer on the component source wafer 60, make up a component 10 or small integrated circuit chiplet of the component 10.
In some embodiments of the present invention, components 10 are small integrated circuits, for example chiplets, having a thin substrate with a thickness of only a few microns, for example less than or equal to 25 microns, less than or equal to 15 microns, or less than or equal to 10 microns, and a width or length of 5-10 microns, 10-50 microns, 50-100 microns, or 100-1000 microns. Such chiplet components 10 can be made in a semiconductor component source wafer 60 (e.g., a silicon or GaN wafer) having a process side and a back side used to handle and transport the wafer. In certain embodiments, components 10 are formed using lithographic processes in an active layer on or in the process side of the component source wafer 60. In certain embodiments, an empty release layer space (gap 69) is formed beneath the components 10 with tethers 67 connecting the components 10 to anchors 68 in the component source wafer 60 in such a way that pressure applied against the components 10 breaks the tethers 67 to make broken (e.g., fractured) tether 67B and release the components 10 from the component source wafer 60. Methods of forming such structures are described, for example, in the paper AMOLED Displays using Transfer-Printed Integrated Circuits and U.S. Pat. No. 8,889,485 referenced above. Lithographic processes for forming components 10 in a component source wafer 60, for example transistors, wires, and capacitors, can be found in the integrated circuit art.
According to various embodiments of the present invention, a native source wafer can be provided with the components 10, release layer, tethers 67, and connection posts 16 already formed, or they can be constructed as part of a process in accordance with some embodiments of the present invention.
In certain embodiments, connection posts 16 are structures that provide electrical connections that extend generally perpendicular to the surface of a component substrate 12. Such connection posts 16 can be formed from metals such as aluminum, titanium, tungsten, copper, silver, gold, or other conductive metals. Connection posts 16 can be formed by repeated masking and deposition processes that build up three-dimensional structures. In some embodiments, the connection posts 16 are made of one or more high elastic modulus metals, such as tungsten. As used herein, a high elastic modulus is an elastic modulus sufficient to maintain the function and structure of the connection post 16 when pressed into a destination substrate contact pad 22.
In certain embodiments, electrodes 18 include patterned metal layers forming component contact pads 19. Component contact pads 19 can be made using integrated circuit photolithographic methods. Likewise, connection posts 16 can be made by etching one or more layers of metal evaporated or sputtered on a component 10. In some embodiments, as illustrated in
Connection posts 16 can have a variety of aspect ratios and typically have a peak area smaller than a base area. Connection posts 16 can have a sharp point for embedding in or piercing destination substrate contact pads 22. Components 10 with protruding connection posts 16 generally are discussed in U.S. Pat. No. 8,889,485, the disclosure of which is hereby incorporated by reference herein in its entirety.
Destination substrate contact pads 22 can be made of a relatively soft metal, such as tin, solder, or tin-based solder, to assist in forming good electrical contact with connection posts 16 and adhesion with components 10. As used herein, a soft metal may refer to a metal into which a connection post 16 can be pressed to form an electrical connection between the connection post 16 and a destination substrate contact pad 22 or the component contact pads 19. In this arrangement, destination substrate contact pad 22 or component contact pad 19 can plastically deform and flow under mechanical pressure to provide a good electrical connection between the connection post 16 and the destination substrate contact pad 22 or the component contact pad 19.
In some embodiments of the present invention, connection posts 16 can include a soft metal and destination substrate contact pads 22 or component contact pads 19 can include a high elastic modulus metal. In this arrangement, connection posts 16 can plastically deform and flow under mechanical pressure to provide a good electrical connection between the connection post 16 and the destination substrate contact pads 22 or the component contact pads 19.
If an optional adhesive layer 24 is formed on a destination substrate 20, connection posts 16 can be driven through the adhesive layer 24 to form an electrical connection with destination substrate contact pads 22 beneath the adhesive layer 24. In certain embodiments, an adhesive layer 24 can be cured to more firmly adhere components 10 to a destination substrate 20 and maintain a robust electrical connection between the connection posts 16 and destination substrate contact pads 22 in the presence of mechanical stress. In certain embodiments, an adhesive layer 24 can undergo some shrinkage during the curing process that can further strengthen the electrical connectivity and adhesion between a connection post 16 and a destination substrate contact pad 22 or a component contact pad 19. In some embodiments of the present invention, an adhesive layer 24, for example a curable adhesive layer 24, is coated over a first layer 11A of first components 10A so that a second level 11B of second components 10B disposed over the first layer of first components 10A can be adhered to the first layer 11A of first components 10A. In some embodiments, an adhesive layer 24 can be patterned or otherwise coated over component contact pads 19 and connection posts 16 of components 10 in the second level 11B of components 10 make electrical contact with component contact pads 19 in the first layer 11A of components 10 through the adhesive layer 24.
As shown in
In some embodiments of the present invention, connection posts 16 of components 10 are in contact with, are embedded in, or pierce destination substrate contact pads 22 or component contact pads 19. In some embodiments, either or both of one or more of connection posts 16 and destination substrate contact pads 22 or component contact pads 19 are deformed or crumpled into a non-planar shape or are deformed so that the surfaces of the connection posts 16 and the destination substrate contact pads 22 or component contact pads 19 change shape on contact with each other. Without wishing to be bound by any particular theory, deformation or crumpling can improve the electrical connection between connection posts 16 and destination substrate contact pads 22 or component contact pads 19 by increasing the surface area that is in contact between the connection posts 16 and the destination substrate contact pads 22 or component contact pads 19. To facilitate deformation, in some embodiments, two or more connection posts 16 have a composition softer than that of the destination substrate contact pads 22 or component contact pads 19 or the destination substrate contact pads 22 or component contact pads 19 have a composition softer the two or more connection posts 16.
A connection post 16 can include conductive material such as a solder that is melted to promote the electrical connection between the connection post 16 and a destination contact pad 22 or component contact pad 19. In some embodiments, the destination substrate contact pads 22 or component contact pads 19 include or are coated with a conductive material or solder. Connection posts 16 can contact, be embedded in, or pierce the conductive material. In some embodiments, a destination substrate contact pad 22 or component contact pads 19 has a first conductive layer and a second conductive layer over the first conductive layer, and the second conductive layer has a lower melting temperature than the first conductive layer. With a subsequent heat treatment, the solder can reflow and promote the electrical connection between the connection post 16 and the destination substrate contact pad 22 or component contact pad 19. In some embodiments, both the connection posts 16 and the destination substrate contact pads 22 or component contact pads 19 include a layer of conductive material such as solder or have a layer of conductive material other than the material making up the connection posts 16 or destination substrate contact pads 22 or component contact pads 19 that electrically connects the destination substrate contact pad 22 or component contact pad 19 to the connection post 16. As noted above, a heat treatment can also serve to weld a destination substrate contact pad 22 or component contact pad 19 to a connection post 16. Welding can be facilitated by providing a common material on the surfaces of the connection posts 16 and the destination substrate contact pads 22 or component contact pads 19.
The spatial distribution of components 10 is a matter of design choice for the end product desired. In some embodiments of the present invention, all of the components 10 in a component source wafer 60 array are transferred to the stamp 30 (i.e., in a single step). In some embodiments, a subset of the components 10 in a component source wafer 60 array is transferred in a single step. By varying the number and arrangement of pillars 32 on a transfer stamps 30, the distribution of components 10 on the pillars 32 of the transfer stamp 30 can be likewise varied, as can the distribution of components 10 on a destination substrate 20 or onto a layer of components 10.
In certain embodiments, components 10 are pressed onto or into a destination substrate contact pads 22 or component contact pads 19 by micro-transfer printing with sufficient mechanical pressure against the destination substrate contact pads 22 or component contact pads 19 to drive connection posts 16 into or through a surface of the destination substrate contact pads 22 or component contact pads 19 to form a robust electrical contact between the connection posts 16 of the component 10 and the destination substrate contact pads 22 or component contact pads 19. In some embodiments, a sufficient mechanical pressure is an amount of force needed to cause a destination substrate contact pad 22, component contact pad 19, or connection post 16 to plastically deform as the connection post 16 is pressed into the destination substrate contact pad 22 or component contact pads 19. Thus, in some embodiments, connection posts 16 on an active components 10 may have sharp points and/or a high elastic modulus, for example, by incorporating tungsten. A connection post 16 can have a sharp point, for example, if the top of the post has an area less than 10 microns square, less than 5 microns square, or less than one-micron square. Destination substrate contact pads 22 can also provide adhesion to help adhere components 10 to a destination substrate 20 or to another component 10.
Adhesion between components 10 and the receiving side of a destination substrate 20 or component contact pad 19 should be greater than the adhesion between the components 10 and the pillars 32 of a transfer stamp 30. As such, when the transfer stamp 30 is removed from the receiving side of the destination substrate 20 or component 10, the components 10 adhere more strongly to the destination substrate 20 or component 10 than to the transfer stamp 30, thereby transferring the components 10 from the transfer stamp 30 to the receiving side of the destination substrate 20 or another component 10.
The transfer stamp 30 is then removed leaving the components 10 adhered to the destination substrate 20 or component 10. An optional heat treatment can solder or weld the connection posts 16 of the components 10 to the destination substrate contact pads 22 of the destination substrate 20 or component contact pads 19 of a component 10. Thus, in some embodiments of the present invention, destination substrate contact pads 22, component contact pads 19, or connection posts 16 are heated, causing the destination substrate contact pad 22 metal to reflow and improve adhesion between the components 10 and the destination substrate 20 or component contact pads 19 and improve the electrical connection to the connection posts 16.
In some embodiments of the present invention, a component 10 is a light-emitting component that emits light. In one arrangement, the light is emitted in a direction opposite to the connection posts 16. In some embodiments, a component 10 is covered with a second dielectric layer 15. The second dielectric layer 15 can be transparent to visible light or to the frequencies of light emitted by the light emitter and the light can be emitted through the second dielectric layer 15.
According to some embodiments of the present invention, a component source wafer 60 can be provided with components 10 and component contact pads 19 and connection posts 16 already formed on the component source wafer 60. In some embodiments, an unprocessed component source wafer 60 can be provided with components 10 formed on or in the component source wafer 60. As used herein, an unprocessed component source wafer 60 is a substrate that does not yet include components 10. An unprocessed component source wafer 60 can have other processing steps completed, for example, cleaning, deposition of material layers, or heat or chemical treatments, as are used in the photo-lithographic arts. Components 10 are formed, for example using photo-lithographic processes including forming or providing masks over the component source wafer 60, etching materials, removing masks, and depositing materials. Such processes are used in the photo-lithographic arts. Using such processes, components 10 are formed on or in a component source wafer 60.
Components 10 can be small electronic integrated circuits, for example, having a size of about 5 microns to about 5000 microns in a dimension. Electronic circuits can include semiconductor materials (for example inorganic materials such as silicon or gallium arsenide, or inorganic materials) having various structures, including crystalline, microcrystalline, polycrystalline, or amorphous structures. In some embodiments, components 10 are passive, for example including a conductor that, when used in a printed electronic structure 50 serves to electrically connect one conductor (e.g., a destination substrate contact pad 22 or component contact pad 19) to another, thereby forming an electrical jumper. Components 10 can also include insulating layers and structures such as silicon dioxide, nitride, and passivation layers and conductive layers or structures including wires or electrodes 18 made of aluminum, titanium, silver, or gold that form an electronic circuit. Connection posts 16 or component contact pads 19 can be formed of metals such as aluminum or polysilicon semiconductors deposited and patterned on a component substrate 12. Useable methods and materials for making component 10 electronic circuits are known in the integrated circuit arts. In certain embodiments, large numbers of such small integrated circuits are formed on a single component source wafer 60. Components 10 are typically packed as closely as possible to use the surface area of the component source wafer 60 as efficiently as possible.
In some embodiments, components 10 are small integrated circuits formed in a semiconductor wafer, for example gallium arsenide or silicon, which can have a crystalline structure. Processing technologies for these materials typically employ high heat and reactive chemicals. However, by employing transfer technologies that do not or minimally stress a component 10 or substrate materials, more benign environmental conditions can be used as compared to thin-film manufacturing processes. Thus, in certain embodiments, the present invention has an advantage in that flexible substrates, such as polymeric substrates, that are intolerant of extreme processing conditions (e.g., heat, chemical, or mechanical processes) can be employed for destination substrates 20. Furthermore, without wishing to be bound by any particular theory, it has been demonstrated that crystalline silicon substrates have strong mechanical properties and, in small sizes, can be relatively flexible and tolerant of mechanical stress. This is particularly true for substrates having 5-micron, 10-micron, 20-micron, 50-micron, or even 100-micron thicknesses. In some embodiments, components 10 can be formed in a microcrystalline, polycrystalline, or amorphous semiconductor layer.
In some embodiments, components 10 can be constructed using foundry fabrication processes used in the art. Layers of materials can be used, including materials such as metals, oxides, nitrides and other materials used in the integrated-circuit art. Each component 10 can be a complete semiconductor integrated circuit and can include, for example, transistors. Components 10 can have different sizes, for example, 1000 square microns or 10,000 square microns, 100,000 square microns, or 1 square mm, or larger, and can have variable aspect ratios, for example, 1:1, 2:1, 5:1, or 10:1. Components 10 can be rectangular or can have other shapes.
Certain embodiments of the present invention provide advantages over other printing methods described in the prior art. By employing connection posts 16 on components 10 and a printing method that provides components 10 on a destination substrate 20 or in a component stack, a low-cost method for printing chiplets in large quantities at high density over a destination substrate 20 is provided. Furthermore, additional process steps for electrically connecting the components 10 to the destination substrate 20 are obviated in certain embodiments.
A component source wafer 60 and components 10, stamp 30, and destination substrate 20 can be made separately and at different times or in different temporal orders or locations and provided in various process states.
Methods according to certain embodiments of the present invention can be iteratively applied to a single or multiple destination substrates 20. By repeatedly transferring sub-arrays of components 10 from a transfer stamp 30 to a destination substrate 20 or to layers of components 10 and relatively moving the transfer stamp 30 and destination substrates 20 between stamping operations by a distance equal to the size of a sub-array of the selected components 10 in the transferred sub-array between each transfer of components 10, an array of components 10 formed at a high density on a component source wafer 60 can be transferred to a destination substrate 20 at a much lower density. In practice, a component source wafer 60 is likely to be expensive, and forming components 10 with a high density on the component source wafer 60 will reduce the cost of the components 10, especially as compared to forming components on the destination substrate 20. Transferring components 10 to a lower-density destination substrate 20 can be used, for example, if the components 10 manage elements distributed over the destination substrate 20, for example in a display, digital radiographic plate, or photovoltaic system.
In particular, in some embodiments wherein an active component 10 is an integrated circuit formed in a crystalline semiconductor material, an integrated circuit substrate provides sufficient cohesion, strength, and flexibility that it can adhere to a destination substrate 20 without breaking as the transfer stamp 30 is removed.
In comparison to thin-film manufacturing methods, using densely populated component source wafers 60 and transferring components 10 to a destination substrate 20 that requires only a sparse array of components 10 located thereon does not waste or require active layer material on a destination substrate 20. Methods in accordance with certain embodiments of the present invention can also be used to transfer components 10 made with crystalline semiconductor materials that have higher performance than thin-film active components. Furthermore, flatness, smoothness, chemical stability, and heat stability requirements for a destination substrate 20 used in certain embodiments of the present invention may be reduced because the adhesion and transfer process is not substantially limited by the material properties of the destination substrate 20. Manufacturing and material costs may be reduced because of high utilization rates of more expensive materials (e.g., the source substrate) and reduced material and processing requirements for the destination substrate 20.
For a discussion of micro-transfer printing techniques see U.S. Pat. Nos. 8,722,458, 7,622,367 and 8,506,867. Additional details useful in understanding and performing aspects of the present invention are described in U.S. Patent Application Serial No. U.S. Patent Application Ser. No. 62/148,603 filed Apr. 16, 2015, entitled Micro Assembled Micro LED Displays and Lighting Elements and in U.S. Patent Application Ser. No. 62/055,472 filed Sep. 25, 2014, entitled Compound Micro-Assembly Strategies and Devices, the disclosure of each of which is hereby incorporated herein in its entirety by reference.
As is understood by those skilled in the art, the terms “over” and “under” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present invention. For example, a first layer on a second layer, in some implementations means a first layer directly on and in contact with a second layer. In other implementations a first layer on a second layer includes a first layer and a second layer with another layer therebetween.
Having described certain implementations of embodiments, it will now become apparent to one of skill in the art that other implementations incorporating the concepts of the disclosure may be used. Therefore, the disclosure should not be limited to certain implementations, but rather should be limited only by the spirit and scope of the following claims.
Throughout the description, where apparatus and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus, and systems of the disclosed technology that consist essentially of, or consist of, the recited components, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.
It should be understood that the order of steps or order for performing certain action is immaterial so long as the disclosed technology remains operable. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously. The invention has been described in detail with particular reference to certain exemplary embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.
This application claims priority to and benefit of U.S. Provisional Patent Application No. 62/371,008, filed Aug. 4, 2016, entitled Printable 3D Electronic Structure, the disclosure of which is hereby incorporated by reference in its entirety. Reference is made to U.S. Pat. No. 8,889,485, entitled Methods for Surface Attachment of Flipped Active Components by Christopher Bower, U.S. patent application Ser. No. 14/743,788, entitled Micro Assembled LED Displays and Lighting Elements by Christopher Bower et al., and U.S. patent application Ser. No. 14/822,864, entitled Chiplets with Connection Posts by Prevatte et al., the disclosures of which are incorporated herein by reference in its entirety.
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| Number | Date | Country | |
|---|---|---|---|
| 20180042110 A1 | Feb 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62371008 | Aug 2016 | US |
