1. Field of the Invention
The present invention relates to a chip package structure and process of fabricating the same. More particularly, the present invention relates to a chip package structure with superior heat-dissipating capacity and process of fabricating the same.
2. Description of the Related Art
In this fast and ever-changing society, information matters to all people. Many types of portable electronic devices are produced which attempts to catch up with our desires to transmit and receive more data. Nowadays, manufacturers have to factor into their chip package many design concepts such as digital architecture, network organization, local area connection and personalized electronic devices. To do so demands special consideration in every aspect of the design process that affects the processing speed, multi-functional capability, integration level, weight and cost of the chip package. In other words, chip packages must be miniaturized and densified. Flip chip (F/C) bonding technique, through the bonding of bumps to a carrier, is currently one of the principle means of reducing overall wiring length over the conventional wire-bonding method. With a shortening of wiring length in a F/C package, signal transmission rate between the chip and a carrier is increased. Thus, F/C packaging technique is one of the most popular methods of forming high-density packages. However, as density of each package continues to increase, heat dissipation becomes a major problem facing chip manufacturers.
To prevent any damage to the chip 50 due to an incursion of moisture and any damage to the bumps 54 due to mechanical stress, an encapsulating material layer 65 is formed within the bonding gap between the chip 50 and the carrier 60. Conventionally, the encapsulating material layer 65 is formed by channeling a liquid encapsulating material with low viscosity into the bonding gap between the chip 50 and the carrier 60 through capillary effect and then curing the injected material afterwards.
The flip-chip package structure 40 as shown in
Although the aforementioned chip package structure 70 can have a high heat-dissipating capacity, the package also requires a large surface area. Hence, producing a package with a high input/output pin count is difficult. Moreover, the assembling process is rather complicated so that the production cycle is quite long.
Accordingly, at least one objective of the present invention is to provide a chip package structure and process of fabricating the same that combine the superior electrical performance of a flip-chip bonded device with the high heat dissipating capacity of a package with a heat sink.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a chip package structure. The chip package structure mainly comprises a carrier, a chip, a heat sink and an encapsulating material layer. The chip has an active surface with a plurality of bumps thereon. The active surface of the chip is flipped over and bonded to the carrier in a flip-chip bonding process so that the chip and the carrier are electrically connected. The heat sink is set over the chip. The heat sink has an area larger than the chip. The encapsulating material layer completely fills a bonding gap between the chip and the carrier and covers the carrier. Furthermore, the encapsulating material layer is formed in a simultaneous molding process and at least part of the surface of the heat sink away from the chip is exposed.
The encapsulating material layer within the bonding gap between the chip and the carrier has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than 0.5 times the said thickness. The chip package structure of this embodiment further comprises a thermal conductive adhesive layer set between the chip and the heat sink.
This invention also provides an alternative chip package structure. The chip package structure mainly comprises a carrier, a chipset, a heat sink and an encapsulating material layer. The chipset is set over and electrically connected to the carrier. The chipset comprises a plurality of chips and at least one of the chips is flip-chip bonded to the carrier or another chip so that a flip-chip bonding gap is created. The heat sink is set over the chipset. The heat sink has an area larger than the chipset. The encapsulating material layer completely fills the bonding gap between the chip and the carrier and covers the carrier. Furthermore, the encapsulating material layer is formed in a simultaneous molding process and at least part of the surface of the heat sink away from the chip is exposed.
The encapsulating material layer within the bonding gap between the chip and the carrier has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than 0.5 times the said thickness. The chip package structure of this embodiment further comprises a thermal conductive adhesive layer set between the uppermost chip of the chipset and the heat sink.
In addition, the chipset of this embodiment comprises a first chip and a second chip. The first chip has a first active surface. The first chip is attached to the carrier such that the first active surface is away from the carrier. The second chip has a second active surface with a plurality of bumps thereon. The second chip is bonded and electrically connected to the first chip in a flip-chip bonding process. The bumps set a flip-chip bonding gap between the first and the second chip.
Furthermore, the chipset further comprises a plurality of conductive wires. Each conductive wire connects a bonding pad on the first chip electrically with a corresponding contact pad on the carrier.
Alternatively, the chipset of this embodiment comprises a first chip, a second chip and a third chip. The first chip has a first active surface with a plurality of first bumps thereon. The first chip is bonded and electrically connected to the carrier in a flip-chip bonding process. The second chip has a second active surface. The second chip is attached to the first chip such that the second active surface is away from the first chip. The third chip has a third active surface with a plurality of second bumps thereon. The third chip is bonded and electrically connected to the second chip in a flip-chip bonding process. The first bumps set a flip-chip bonding gap between the first chip and the carrier and the second bumps set a flip-chip bonding gap between the second chip and the third chip.
Furthermore, the chipset further comprises a plurality of conductive wires. Each conductive wire connects a bonding pad on the second chip electrically with a corresponding contact pad on the carrier.
In the aforementioned embodiments of the chip package structure, the encapsulating material is made from resin and the heat sink is made from a metal, for example. The chip package structure may further comprise an array of solder balls and at least a passive component. The solder balls are attached to the surface of the carrier away from the chip. The passive components are set over and electrically connected to the carrier. The carrier can be a packaging substrate or a lead frame, for example.
This invention also provides a process for fabricating a chip package structure. First, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. Thereafter, the chips and the carrier are electrically connected together. A heat sink is attached to the back of a chip through a thermal conductive adhesive layer. A heat-resistant buffering film is formed over part of the heat sink surface. Finally, an encapsulating material layer is formed covering the carrier and filling a flip-chip bonding gap between the chip and the carrier.
Furthermore, the encapsulating material layer is formed by performing a reduced-pressure transfer molding process. After forming the encapsulating material layer, the carrier is singulated to form a plurality of chip package structures. The reduced-pressure transfer molding process is carried out at a pressure below 20 mm-Hg (Torr) and a temperature at least 10° C. lower than the melting point of the bumps. Moreover, if the encapsulating material layer within the bonding gap between the chip and the carrier has a thickness, maximum diameter of particles constituting the encapsulating material layer must be less than 0.5 times the said thickness.
In brief, the chip package structure incorporates a heat sink having an area larger than the chip. Hence, this invention provides an ideal thermal conductive pathway for distributing the heat generated by a high-pin-count chip package structure. Therefore, operational speed and reliability of the chip package structure is improved. Furthermore, the chip packaging process has the advantage of having a high productivity.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The chip 150 has an active surface 152 with a plurality of bonding pads (not shown) thereon. A plurality of bumps 160 is attached to the bonding pads on the active surface 152 of the chip 150. The active surface 152 of the chip 150 is flipped over to face the carrier 180. Thereafter, the chip 150 is bonded to the carrier 180 through the bumps 160 on the bonding pads so that the chip 150 and the carrier 180 are electrically connected. In other words, the chip package structure 100 of this embodiment includes at least a chip 150 bonded to the upper surface of a carrier 180 using a flip-chip bonding technique. However, aside from the chip 150, this invention also permits the mounting of other chips or passive components such as resistors or capacitors on the carrier 180 within the package structure 100.
The heat sink 140 is set over the chip 150. The heat sink 140 has an area larger than the chip 150 so that a higher heat dissipating capacity is provided. Furthermore, the heat sink 140 is not limited to a single integrative unit. The heat sink 140 may comprise a multiple of individual heat sinks providing more flexibility to the design of the chip package structure.
In addition, the encapsulating material layer 170 completely fills a bonding gap between the chip 150 and the carrier 180 and covers the carrier 180. The encapsulating material layer 170 is formed in a simultaneous molding process using a resin, for example.
The heat sink 140 is fabricated using a metallic material, for example. In this invention, the heat sink 140 has an area larger than the chip 150 so that the heat generated by the chip 150 is able to spread out into a large area. Therefore, metallic materials with high thermal conductivity including, for example, copper plate, aluminum plate, iron plate, nickel plate or other gold electroplated thereon is preferred. In addition, the heat sink 140 must withstand the pressure encountered during a molding process. Hence, the heat sink 140 is preferably fabricated using a high strength material with anti-warping capacity. Although there is a variety of high thermal conductive metallic material to choose from, the heat sink 140 preferably has a thickness between 0.1˜0.6 mm. Moreover, to ensure a strong adhesion between the encapsulating material layer 170 and the heat sink 140, the heat sink 140 may undergo a chemical treatment, a roughening process or a gold plating operation prior to the molding process.
To ensure the formation of a suitable bond between the heat sink 140 and the chip 150, a thermal conductive adhesive layer 145 is applied to the junction between the heat sink 140 and the chip 150 (as shown in an enlarged portion of
The chip package structure 100 may further comprise an array of solder balls 190. The solder balls 190 are attached to the contact pads on the lower surface of the carrier 180 for subsequently connecting with a printed circuit board, for example.
Among the chip package structures in
The encapsulating material layer 270 within the flip-chip bonding gap 256 has a thickness. Maximum diameter of particles constituting the encapsulating material layer 270 must be less than 0.5 times the said thickness of the bonding gap 256. To ensure the formation of a suitable bond between the heat sink 240 and the chipset 250, a thermal conductive adhesive layer 245 is applied to the junction between the heat sink 240 and the uppermost chip of the chipset 250. Typically, the thermal conductive adhesive layer 245 is a layer of silicone, silver epoxy, soldering paste or other highly thermal conductive materials, for example.
As shown in
Furthermore, the chipset 250 further comprises a plurality of conductive wires 254b. The carrier 280 has a plurality of contact pads (not shown) thereon. The solder balls 190 are attached to the contact pads on the lower surface of the carrier 280 which is similar or the same to the solder balls 190 shown in FIGS. 4A˜4I. The first active surface 252a of the first chip 250a and the second active surface 252b of the second chip 250b have a plurality of bonding pads (not shown) thereon. The bumps 260 on the second chip 250b are set in the flip-chip bonding gap 256 between the first chip 250a and the second chip 250b. In other words, the second chip 250b is flip-chip bonded to the first active surface 252a of the first chip 250a. Each conductive wire 254b electrically connects a bonding pad on the first chip 250a with a corresponding contact pad on the carrier 280.
As shown in
In the second embodiment, the number of chips within the chip package structure is increased. In addition, not all the chips have to be bonded to the carrier using the flip-chip bonding technique. In fact, the main characteristic of this invention is that the chip package structures has at least a chip bonded to a carrier or another chip using the flip-chip bonding technique. Furthermore, a heat sink is mounted on the top of the chip and an encapsulating material layer is formed over the carrier as well as inside the flip-chip bonding gap. Moreover, the encapsulating material layer is formed in a simultaneous molding process such that at least part of upper surface of the heat sink is exposed. Any chip package structure with the aforementioned characteristics should be counted as a design within the scope of this invention.
This invention also provides a process for fabricating the aforementioned chip packages structure. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier are electrically connected together. Thereafter, a heat sink is attached to the back of the chips and then at least one heat-resistant buffering film is formed over part of the heat sink surface. An encapsulating material layer is formed over the carrier and filling bonding gaps between the chips and the carrier.
It is to be noted that a reduced-pressure transfer molding process may be used to form the encapsulating material layer in the process of fabricating the chip package structure. In the reduced-pressure transfer molding process, the chips to be enclosed are placed inside a mold cavity. After reducing the pressure inside the mold cavity, encapsulant is channeled into the mold cavity. Thereafter, the mold is heated and pressurized so that the resin is cured. Ordinary transfer molding process has insufficient capacity for forming a fully filled encapsulating material layer in the flip-chip bonding gap or the over mold layer. On the other hand, if the pressure inside the mold cavity is allowed to lower to a level below 20 mm-Hg, the filling capability of the encapsulating material will improve considerably. Preferably, the mold cavity is set to a pressure below 10 mm-Hg.
During the reduced-pressure molding process, the mold is controlled at a temperature at least 10° C. below the melting point of the bumps 160. If temperature of the mold is higher than this value, the pressure generated by the melting encapsulating material may peel off the chip 150 when the bonding strength between the bumps 160 and the carrier 180 is not strong enough.
Furthermore, if part of the heat sink 140 needs to be exposed after the molding process, a heat-resistant buffering film 380 must be used. Without the heat-resistant buffering film 380, the exposed surface of the heat sink 140 may contain flush. On the other hand, if a pressure is directly applied to the heat sink 140 by adjusting the upper mold 310 simply to prevent the formation of flush, the molding pressure may act on the chip 150 via the heat sink 140 and cause some damage to the chip 150. Therefore, the heat-resistant buffering film 380 on the heat sink 140 is one of the most effective means of reducing the flush.
The heat-resistant buffering film 380 is typically a polyamide or fluorinated resin layer but is not limited thereto. In general, the heat-resistant buffering film 380 has a thickness between 25˜75 μm so that the buffering action according to this invention can be produced. In addition, the heat-resistant buffering film may be fabricated from a rubbery material such as fluorinated rubber.
In addition, according to the chip packaging process of this invention, the maximum diameter of particles constituting the encapsulating material is preferably less than 0.5 times the flip-chip bonding gap. If the encapsulating material contains particles with diameter greater than 0.5 times the flip-chip bonding gap, difficulties in filling the flip-chip bonding gap or the gap between the carrier and the heat sink may occur. Moreover, friction between the encapsulating material and chip surface may scratch and damage the chip leading to a drop in overall reliability of the package.
In the following, actual examples and contrast examples of this invention as well as their application results are described.
Chips each having a total area 8 mm×8 mm, 800 lead-tin bumps (melting point 183° C., pitch separation 0.25 mm) and a thickness 0.3 mm are set as an array over a FR-5 carrier with an area 35 mm×35 mm, a thickness 0.4 mm. To provide a uniform distribution of current, aluminum wires are set on the surface of the chip. The flip-chip bonding gap is between 50 to 75 μm. A 22 mm×22 mm copper plate (heat sink) with a thickness of about 0.2 mm is provided. After plating a layer of nickel over the copper plate, a piece of conventional 20 mm width φPFA film (having a thickness 50 μm) is taped onto the copper plate. The lower surface of the copper plate is also roughened to increase bonding strength. The copper plate is attached to the chip using a conventional thermal conductive adhesive material. A set of transfer molding equipment with reduced-pressure molding capability is used to performing the reduced-pressure molding process. The pressure inside the mold cavity is reduced to an almost vacuum state of 1 mm-Hg during the molding process. The encapsulating material is CV8700F2 (having a maximum particle diameter 21 μm, average particle diameter 5 μm, all silicon filler) produced by Matsushita Electric Works, Ltd. The upper mold cavity has a thickness 0.6 mm and a total encapsulating area around 27 mm×27 mm. The molding process is carried out at 170° C. and a pressure of 70 kg/cm2 for about 2 minutes. Thereafter, a post-curing process is carried out at a temperature of 175° C. for 4 hours to produce a chip package structure as shown in
The same chip as in example 1 and conventional underfill material (Matsushita Electric Works product CV5183F) is used. Spot injection equipment is deployed to carry out the flip-chip bonding gap filling process. After curing the filling material at prescribed conditions, a chip package structure as shown in
The same chip and carrier as in example 1 is used. Aside from not providing a pressure reduction through a vacuum pump, all other aspects are identical. A chip package structure identical to
Aside from changing the degree of vacuum in example 1 to the one in
Aside from changing the degree of vacuum in example 1 to the one in
Aside from changing the molding temperature in example 1 to the one in
Aside from changing the molding temperature in example 1 to the one in
Aside from changing the maximum diameter of particles constituting the encapsulating material shown in example 1 to the one in
Aside from changing the maximum diameter of particles constituting the encapsulating material shown in example 1 to the one in
Aside from changing the PFA film in example 1 to a polyamide film with a thickness 50 μm, other aspects are identical. A chip package structure identical to
Aside from changing the copper plate in example 1 into an aluminum plate, all other aspects are identical. A chip package structure identical to
Aside from changing the thickness of the PFA film in example 1 to 30 μm, an integrative molding process (all the surfaces of the chip package structure as well as everything inside the mold) is performed to produce a chip package structure with a smooth surface as shown in
Aside from not using any film in example 8, all other aspects are identical. A chip package structure as shown in
Aside from not using any film in example 8 and changing the package thickness to 0.5 mm, all other aspects are identical. A chip package structure as shown in
In the aforementioned examples and contrast examples, the testing conditions and results of various chip package structures are listed in
The process of fabricating a chip package structure according to the preferred embodiment of this invention is based on a technique disclosed in a Japanese pattern JP392698 (2001). This invention aims at optimizing the package dimension as well as incorporating a heat sink so that the chip package structure can have optimal reliability and heat-dissipating capacity.
In summary, this invention incorporates a heat sink into the chip package structure. Furthermore, the chip is encapsulated in a simultaneous molding process. Hence, the chip package structure has a higher level of reliability and heat-dissipating capacity than a conventional chip package structure. If an encapsulating material with a high thermal conductivity is deployed, a much higher heat-dissipating capacity can be obtained. Moreover, mass production is possible because the chip package has a simple structure,
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Number | Date | Country | Kind |
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2003-117601 | Apr 2003 | JP | national |
92129524 | Oct 2003 | TW | national |
This application is a divisional of a prior application Ser. No. 10/707,687, filed Jan. 5, 2004 claims the priority benefit of Japan application serial no. 2003-117601, filed Apr. 22, 2003 and Taiwan application serial no. 92129524, filed Oct. 24, 2003. All disclosures are incorporated herewith by reference.
Number | Date | Country | |
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Parent | 10707687 | Jan 2004 | US |
Child | 11309106 | Jun 2006 | US |