Patent Application
20100164083
Embodiments of the invention are in the field of microelectronic assembly, more specifically pertaining to materials formed over a microelectronic chip mounted to a package substrate.
A microelectronic package may use a package substrate to deliver power from a power supply and signals from outside the package to a microelectronic chip or die. A package substrate may be connected to a microelectronic die using a molded matrix array package (MMAP) process.
There are moisture related reliability concerns for such molded packages during packaging reliability testing. Under conditions of high temperature and high humidity, moisture may be absorbed into the plastic molding compounds and die attach adhesive materials typically used in molded packages. As a result, molded packages may fail conditions in a bias HAST (Highly Accelerated Stress Test). Such failures incurred at the package level are extremely costly.
This problem is exacerbated by the industry trend toward stacked-die chip-scale packages (SCSPs) to provide higher performance while consuming nearly the same footprint as conventional single-die packages. Because SCSPs combine two or more ICs, both the odds and cost of a moisture-based package reliability failure are higher than for single-die packages. With the number of die integrated into an SCSP increasing, methods for reducing moisture-based package reliability failures become all the more important.
Embodiments of the present invention are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which:
Embodiments of a method for reducing moisture penetration into active metallization pad areas are described herein with reference to figures. Particular embodiments may be practiced without one or more of the specific details described, or in combination with other known methods, materials, and apparatuses. In the following description, numerous specific details are set forth, such as specific materials, dimensions and processes parameters etc. to provide a thorough understanding of the present invention. In other instances, well-known microelectronic design and packaging techniques have not been described in particular detail to avoid unnecessarily obscuring the present invention. Reference throughout this specification to “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one structure or layer with respect to other structures or layers. As such, for example, one layer deposited or disposed over or under another may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer or structure “on” a second layer or structure is in contact with that second layer or structure. Additionally, the relative position of one structure with respect to other structure is provided assuming operations deposit, modify and remove films relative to a starting substrate without consideration of the absolute orientation of the substrate.
WB-MMAP method 100 begins at the die attach operation 101. During the die attach operation 101 a microelectronic die, typically having been thinned with a back side grind (BSG) and polish process, is attached to a package substrate.
The package substrate 212 provides a larger area to distribute signals from the microelectronic die 202, as well as providing physical protection and support for the thinned die. The package substrate 212 may include any materials employed in the art for such purposes and in one embodiment is constructed from a composite material. In an embodiment, the package substrate 212 is a multi-layer substrate having at least ground plane and a power plane. The package substrate 212 may further include a number of vias (not shown) to facilitate vertical electrical signal travel within the package substrate. For example, a substrate via may extend from a metallized substrate bond pad 218 on the substrate top side 208 to a substrate ball limiting metallurgy (BLM) pad 226 on the substrate bottom side 224. The metallized substrate bond pad 218 and BLM pad 226 may be of any metal commonly employed in the art for such purposes (e.g., copper, titanium, aluminum, etc.).
During the die attach operation 101, the die backside 204 is adhered to the substrate top side 208 with a die attach material 206. The die attach material 206 may be a paste, a die-attach film (DAF) or a dicing die-attach film (DDF) applied to the die backside 204. In certain embodiments (die attach paste or DDF), the die attach material 206 is a composite including an epoxy resin and glass or polymer organic spheres to provide good bond line thickness control at a desired thickness. Depending die attach method, the die attach operation 101 may further include a cure (e.g., for paste attach). Additionally, the die attach operation 101 may include a post-die attach plasma clean using an oxidizing or reducing chemistry to remove organic residues from the non-bonded surfaces of the microelectronic die 202 and package substrate 212. Such a clean advantageously prepares metallized bond pads, such as the metallized substrate bond pad 218, for wire bonding.
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Following the wire bond operation 110, the WB-MMAP method 100 proceeds to a thin film coat operation 120. In certain embodiments, prior to forming the thin film, a plasma clean using an oxidizing or reducing chemistry may be performed to clean residues left behind by the wire bond operation 110. A plasma clean may improve adhesion between the subsequently deposited thin film and the microelectronic die, package substrate and bond wires.
Generally, the thin film is formed over surfaces of microelectronic die(s), bond wire(s), die attach film(s) and package substrate such that a moisture barrier is created around package regions susceptible to moisture. The thin film is of a material and is formed in a manner to reduce moisture penetration into these package regions.
It has been found that the moisture absorbed into the molding and die attaching materials increases the mobility of certain ions, such as a copper-II ion originating from, for example, the metallized die bond pad 216 and/or metallized substrate bond pad 218. Copper dendrite growth which eventually electrically shorts I/O pads of the packaged microelectronic die has been attributed to this higher ion mobility. While the microelectronic die 202 will typically include a passivation layer, the metallized die bond pad 216 is free of such passivation to allow for wire bonding and therefore remains an active surface within the package. The thin film reduces moisture penetration into such active sources and sinks of such mobile ions, reducing copper electrochemical migration failures and improving package reliability.
In an embodiment, as depicted in
For any of the exemplary embodiments depicted in
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In this manner, the thin film 332 may prevent substantially any contact between metallized surfaces and a subsequently formed molding compound. This is particularly advantageous where a metallized surface has a low density of bonding states (e.g., a gold surface) and adheres poorly to molding compounds. It has been found that the free volume present in a poorly adhered interface sinks moisture present in the molding compound bulk. For embodiments where the thin film 332 conformally coats gold bonding wires, moisture adsorption and migration along the length of the bonding wires is reduced.
In a further embodiment the thin film 332 also covers the die sidewall 215, the sidewalls of the die attach material 206, and covers the substrate top side 208 to reduce moisture penetration into these surfaces. Sealing the die sidewall 215 with the thin film 332 reduces moisture penetration where a die passivation layer is breached during die saw and improves the integrity of the die edge seal. Sealing both the die sidewall 215 and the die attach material 206 with the thin film 332 is particularly advantageous for SCSP to reduce moisture penetration into the active die and bonded interfaces within a die stack. For example, die attach material in a film over wire (FOW) die stack may not completely cover a wire bond or may be of a porous or hygroscopic material which benefits from sealing. Similarly, sealing the substrate top side 208 with the thin film 332 reduces moisture penetration into the metallization layers of a multi-layered substrate (e.g., inter-layer vias, etc.). Additionally, the thin film 332 adheres to solder resists (not depicted) surrounding metallized regions such as the metallized die bond pad 216 and metallized substrate bond pad 218. In certain embodiments, and as depicted in
In the exemplary embodiment depicted in
Generally, to serve as a good moisture barrier, the thin film 332 should have a low porosity, for example less than 5%. In particularly advantageous embodiments, the porosity is below 1%. In a further embodiment, the thin film 332 is substantially free of pin holes (voids spanning the thickness of the film).
In one embodiment, the thin film 332 is an inorganic material including alumina (Al2O3). In a particular embodiment, alumina is the primary constituent of the thin film 332. In a further embodiment, an alumina-based inorganic material is deposited by atomic layer deposition (ALD) at approximately room temperature (i.e., 25° C.). In one such embodiment the ALD alumina film is deposited to a thickness of approximately 10 nanometers (nm) and 300 nm. ALD alumina has the advantages of being highly conformal, providing good electrical insulation, having essentially 0% porosity, pin hole free at very low thickness, and may be deposited at low temperatures.
It is advantageous to employ low temperature processes for the formation of the thin film 332 because at the thin film coat operation 120, the microelectronic die 202 has been attached and wire bonded to the package substrate 212 and variations in the temperature may cause a resultant differential expansion between the chip and the package substrate. The differential expansion may induce stresses that can cause the connections between the chip and the package substrate to fail (e.g., crack one or more wire bonds).
ALD alumina films also provide high adhesion strength with the polymer resin materials, such as those which may be found on the package substrate top side 208 and in the die attach material 206. Furthermore, a subsequently formed molding compound will also adhere well to the ALD alumina. The thin film 332 may be formed using any ALD alumina process commonly known in the art and therefore a detailed listing of process parameters is not provided.
In an alternative embodiment, the thin film 332 is parylene Type N, C, D, or F. Parylene is a commonly used name for poly-(para-xylenes). In a particularly advantageous embodiment, the thin film 332 is parylene deposited by chemical vapor deposition (CVD) at approximately 25° C. Like ALD, CVD has the advantage of being a vapor phase deposition which is capable of much thinner films than are most non-vapor phase depositions (e.g., liquid phase). CVD parylene is also substantially free of pinholes at such thickness and provides a hydrophobic layer with good adhesion characteristics. Vapor-phase deposition techniques are also advantageous because they can be solvent free. CVD parylene processes are generally sub-atmospheric, but are at pressures high enough that the deposition is non-line of sight and therefore can be made highly conformal. In one such embodiment the CVD parylene film is deposited to a thickness of approximately 10 nanometers (nm) and 300 nm. Low temperature parylene CVD processes are commercially available and therefore a detailed listing of process parameters is not provided herein.
In other embodiments, the thin film 332 is a polyimide (PI), a polyalkene (polyolefin), or benzocyclobutene (BCB). For such embodiments, these materials may be applied at low temperatures using either a spray coating process or sub-atmospheric CVD. Exemplary spray coating embodiments employ nanoparticle mass flow deposition techniques, such as aerosol deposition (AD). Nanoparticle mass flow deposition is distinguished from thermal spray processes by the smaller size of the particles deposited onto a substrate. For example, a particular aerosol deposition processes utilizes particles in the range of 10 nm-1 μm in diameter. Nanoparticle mass flow deposition is typically also performed at a low temperature (nanoparticles are not melted or softened). In one such embodiment, the PI, polyalkene or BCB is applied to a thickness between approximately 1 μm and 10 μm. Alternatively, PI may be formed with low temperature CVD process, for example by co-evaporation of dianhydride and diamine monomers. BCB may also be deposited by low temperature plasma enhanced CVD (PECVD).
In other embodiments, the thin film 332 is an epoxy, a room temperature vulcanized (RTV) silicone, a fluorinated silicone (e.g., polysiloxanes), a fluorinated acrylic or a polyurethane. For such embodiments, these materials may be applied at low temperature using a spray coating process, such as an AD. Sol-gel methods may also be employed. In particular embodiments, the epoxy, RTV silicone, fluorinated silicone, fluorinated acrylic or polyurethane is deposited at a temperature of approximately 25° C. to a thickness of approximately 1 μm-100 μm. Generally, the smallest thickness that can be controlled and is substantially pinhole free is preferred to ensure conformality of the thin film 332. In particular embodiments, AD is employed to form the thin film 332 to a thickness of approximately 1 μm-10 μm.
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Following application of the mold operation 125, the WB-MMAP method 100 proceeds to solder ball attach and reflow operation 130. As further depicted in
Thus, packaging of a device with a thin film layer between the microelectronic die and a molding compound has been disclosed. Although the present invention has been described in language specific to structural features or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are to be understood as particularly graceful implementations of the claimed invention in an effort to illustrate rather than limit the present invention.
