Quad flat no-lead chip carrier with stand-off

Information

  • Patent Application
  • 20070273017
  • Publication Number
    20070273017
  • Date Filed
    May 23, 2006
    18 years ago
  • Date Published
    November 29, 2007
    17 years ago
Abstract
A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.
Description

BRIEF DESCRIPTION OF THE DRAWING


FIG. 1 shows a plan view of the bottom side of a conventional QFN chip carrier.



FIG. 2 shows a cross-sectional view of the conventional QFN chip carrier of FIG. 1 taken along line at 2-2.



FIG. 3 shows a cross-sectional view of the QFN chip carrier shown in FIG. 2 as attached to a PCB.



FIG. 4 shows a plan view of the bottom side of a QFN chip carrier, in accordance with the present invention.



FIG. 5 shows a cross-sectional view of the QFN chip carrier of FIG. 4 taken along line 5-5.



FIG. 6 shows a cross-sectional view of the QFN chip carrier shown in FIG. 5 as attached to a PCB.



FIG. 7 shows a plot of the expected improvement in QFN second level interconnect fatigue life.





DETAILED DESCRIPTION

The bottom of a conventional QFN chip carrier is shown in FIG. 1. This is the side of the carrier that attaches to a substrate, such as, a PCB. Typically, the QFN chip carrier comprises a leadframe made from a flat copper plate. The leadframe 1 in FIG. 1 comprises a pattern that includes copper die paddle 5 and leads 6. The pattern of the paddle and leads may be etched or stamped out of the flat copper plate.



FIG. 2 shows a cross-sectional view of the QFN chip carrier of FIG. 1 taken along line 2-2. As shown, copper leads 6 are plated on the top with a layer 9 of, for example, silver and on the bottom with a layer 11 of, for example, solder to thereby form lead contacts 3. In this regard, it can be seen that the surfaces of die paddle 5 are also similarly plated on top and bottom at the same time leads 6 are plated. Wires 13, made of gold for example, connect contact pads 14 on chip 7 to lead contacts 3. Similarly, gold wire 15 forms a ground connection. As shown, this assembly is encapsulated in conventional insulating mold material.


As previously described, since copper lead 6 is limited in its protrusion, the surface over which solder may wet in joining the chip carrier to the pads on a substrate, such as a PCB, is also limited. This limited protrusion not only limits wetting and the ability to make reliable contact in joining the chip carrier to the PCB, it also creates other problems with joining, some of which were previously described.



FIG. 3 shows a cross-sectional view of the conventional QFN chip carrier of FIG. 2, as mounted on PCB 23. As demonstrated in FIG. 3, respective solder joint connections 19 and 20, between leads 6 and conductive pads 21 and between die paddle 5 and conductive pad 22 on PCB 23, is limited in height due to the limited ability to use a sufficient volume of solder and for the solder to wet.


The bottom of the QFN chip carrier, in accordance with the present invention, is shown in FIG. 4. The QFN chip carrier embodiment of FIG. 4, which includes copper leadframe 25 with eight copper leads 27 on each side, as previously shown in FIGS. 1-3. However, each of the copper leads also has a rounded protrusion or bump 29 formed therein to provide additional chip carrier standoff. In addition, die paddle 31 also has an array of like rounded protrusions or bumps 33 formed therein. As shown, the array is a 6×7 array of rounded protrusions 33. However, a different array could as readily be employed. Similarly, the number of copper leads along the carrier sides may vary, depending upon the particular application.



FIG. 5 shows a rotated cross-sectional view of FIG. 4, taken along line 5-5. In FIG. 5, the rounded protrusions are shown along the bottom of the chip carrier with copper lead protrusions, shown at 29, and die paddle protrusions, shown at 33. FIG. 5 also shows wire connections 13 between chip pad 14 and lead contacts 35. Similarly, wire connection 15 provides a ground connection to die paddle 31. These wire connection may be made of any of a variety of conductors, such as, gold.


The rounded protrusions 29 and 33 may be formed in the copper plate of the leadframe before forming the pattern of leads and die paddle. Alternatively, the rounded protrusions may be formed after the pattern of leads and die paddle is formed. The protrusions in the leads and die paddle may also be formed at the same time that the leads and die paddle are formed. Regardless, the copper plate of the leadframe itself is used to form the rounded protrusions. One method of forming the protrusions is to employ a half-stamp or partial stamp process. The die of the stamp would comprise an array of rounded protrusions, similar to the array of protrusions to be stamped into the copper plate of the leadframe. The die of the stamp would then be pressed partially into the plate such as to form a dimple but not so as to break through the plate. Alternatively, a single rounded protrusion in a die may be employed and the protrusions stamped, one at a time, at selected points in the copper plate.


The extent to which the stamp is pressed, i.e., depth of penetration of the dimple, is somewhat a matter of design choice and thickness of the plate. Typically, it would be preferred to obtain the greatest stand-off height, i.e., protrusion height, possible without punching through the plate, consistent with the particular application. For example, rounded protrusions of up to 100 μm would be consistent with current QFN chip carrier technology. It is to be noted that the stand-off protrusions, as formed from the copper plate itself, simplifies the process of forming the protrusions, since protrusion attachment method, materials used, position and the like, of the protrusions are readily determined and formed during the leadframe forming process. It should be understood that although the use of stamping has been described for making the rounded protrusions, a molding process for creating the copper plate with integral rounded protrusions could also be employed. The mold, thus, would include dimples in the flat bottom part of the mold.


After stamping the rounded protrusions and the leads and die paddle have been formed, the copper leadframe is then plated. In most cases only the top surface of the leadframe is plated and typically, the top surface of the leadframe is plated with silver, as shown by silver layer 37, although other conductive materials may also be used. As also shown, the voids 41 created by the dimples 33 are also filled with silver. The bottom layer may be plated or otherwise formed on the copper leadframe. Typically the bottom surface of the leadframe is covered with a layer of solder 39, for example, after the chip carrier molding process. There are also other options, such as, using pre-plated leadframes wherein the leadframe is plated on both sides after stamping the rounded protrusions, and the leads and die paddle are formed. In such a case, the top surface is typically plated with silver, as shown by silver layer 37. The bottom layer may be plated or otherwise formed on the leadframe. For preplated leadframes, the bottom surface is typically plated with nickel palladium with a gold flash although other conductive layers may be used.


As can be seen, because of the protrusions, the area covered by solder is increased. It is to be noted that the protrusions in the area of die paddle 31 also act to provide stability and, because the surface is not flat, provides some degree of relief from shock-induced stress, and like stress, for chip 7. In this


regard, chip 7 is attached to die paddle 31 with an adhesive 51, such as, Ablebond 2300 paste adhesive or Ablefilm 5320CE dry film adhesive. Although FIGS. 5 and 6 show plated silver layer 37 extending beneath chip 7, typically the area beneath chip 7 would not include silver layer 37 but rather the chip would be directly attached by adhesive to bare copper of the die paddle.


After attaching chip 7 to die paddle 31, the wire connections are made, as hereinabove described, and the assembly is encapsulated in mold 43 of insulating material. The mold may be made, for example, from Loctite FP4450, Nitto GE 1100L, or Sumitomo Bakelite EME-G700 material, for example. After encapsulation, the QFN chip carrier with rounded protrusions for enhanced stand-off is ready for connection to a substrate, such as, a PCB.



FIG. 6 shows the chip carrier of FIG. 5, as attached to a PCB 45. The protrusions 29 and 33 act to provide a structure that allows more wetting area and room for more solder during reflow attachment to pads 47 and 48 on PCB 45. This results in lead solder joints 49 and die paddle solder joint 50 acting to provide more stand-off height, i.e., solder joint thickness, and more solder joint area and integrity with improved fillets, as shown at 51 and 52. The structure also results in less paste “pushout” when the chip carrier is pushed into the solder paste on the PCB during the pick and place process at card assembly. It further offers better self-alignment of the chip carrier leads to the pads on the PCB, less floating of the chip carrier and reduced “shorts” and “opens”. Thus, the assembly results in better yield and more overall reliability.



FIG. 7 shows a plot of expected improvement in second level interconnect fatigue life versus QFN solder joint stand-off height. As shown, as conventional solder joint stand-off or joint solder thickness “t” increases up to around 75 μm, fatigue life increases by a factor of about 2. With the rounded protrusion structure, in accordance with the present invention, joint solder thickness or stand-off is expected to increase by a factor of about 4, or twice that of conventional QFN chip carrier arrangements.


Although description has been provided of embodiments of a QFN with leads on four side of a square package, it is clear that the arrangement described in accordance with the present invention could as readily be employed in no lead packages with leads on only two sides, for example. In addition, QFNs with two or dual rows of leads on four sides could also be employed. Similarly, either square or rectangular no lead packages with and without exposed die paddles could, as well, be employed.


It will be understood from the foregoing description that various modifications and changes may be made in the preferred embodiment of the present invention without departing from its true spirit. It is intended that this description is for purposes of illustration only and should not be construed in a limiting sense. The scope of this invention should be limited only by the language of the following claims.

Claims
  • 1. A chip carrier, comprising: a plate of material having a first surface having a chip attach region for attaching a chip to said carrier and another region around said chip attach region having a plurality of conductive leads for connecting to pads on said chip, said plate of material further having a second surface with an array of rounded conductive plate protrusions extending from said second surface.
  • 2. The chip carrier as set forth in claim 1 wherein said chip carrier is a no-lead chip carrier with chip attached to said chip attach region.
  • 3. The chip carrier as set forth in claim 1 wherein said protrusions extend from said second surface beneath at least said another region.
  • 4. The chip carrier as set forth in claim 3 wherein said protrusions extend beneath said another region and said chip attach region.
  • 5. The chip carrier as set forth in claim 1 wherein said plate of material is a plate of conductive material having a first surface with a chip attach region surrounded by a plurality of conductive lead regions and a second surface having an array of rounded protrusions of conductive material extending therefrom formed from said plate of conductive material.
  • 6. The chip carrier as set forth in claim 5 wherein said rounded protrusions of conductive material extend from beneath at least said conductive lead regions.
  • 7. The chip carrier as set forth in claim 6 wherein said array of rounded protrusions are each formed as a result of an array of opposing dimples formed in said first surface.
  • 8. The chip carrier as set forth in claim 6 including a chip attached to said chip attach region and wire connections between said chip and said conductive lead regions.
  • 9. The chip carrier as set forth in claim 8 wherein said conductive lead regions are respectively soldered to conductive pads on a printed circuit board.
  • 10. A method of forming an electronic package, comprising: forming a pattern in a plate of material including a chip attach region and conductive lead regions around said chip attach region for connecting said chip to said conductive lead regions on one surface of said plate of material; andforming an array of conductive protrusions extending from said plate of material on the surface opposing said one surface, said protrusions extending beneath at least said conductive lead regions.
  • 11. The method as set forth in claim 10 wherein said plate of material is a conductive plate and said protrusions are formed in said conductive plate by stamping dimples into said one surface at least in said conductive lead regions.
  • 12. The method as set forth in claim 11 wherein said conductive plate is a copper plate.
  • 13. The method as set forth in claim 11 wherein at least a portion of said one surface including conductive lead regions is coated with a layer of conductive material and where at least a portion of said surface opposing said one surface including conductive lead regions is coated with a layer of solder.
  • 14. The method as set forth in claim 13 including the steps of: attaching a chip to said chip attach region; andelectrically connecting pads on said chip to said layer of conductive material on said one surface of respective ones of said conductive lead regions to form a chip package.
  • 15. The method as set forth in claim 14 including the steps of: applying solder paste to respective pads on an array of conductive pads on a printed circuit board;pressing said chip package into said solder paste so that respective ones of said conductive lead regions coated with a layer of solder align with respective ones of said array of conductive pads on said printed circuit board; andreflowing said solder to form solder joints with improved fillets and stand-off height.
  • 16. A method of forming a chip carrier package, comprising: forming a leadframe from a conductive plate having a chip attach region and conductive lead regions surrounding said chip attach region;forming protrusions extending from one surface of said conductive plate in said chip attach region and conductive lead regions with said protrusions formed as an integral part of said conductive plate;coating said conductive lead regions and said chip attach region of said one surface of said conductive plate including protrusions with a layer of solder and plating at least said conductive lead regions of the opposing surface thereof with a layer of metal;attaching a chip to the said surface opposing said one surface with an adhesive;connecting respective pads on said chip to said layer of metal on respective ones of said conductive lead regions;forming a layer of solder on the respective pads of an array of pads on a substrate;aligning said layer of solder of said conductive lead regions and chip attach region including protrusions with said respective pads on said substrate so as to extend said protrusions into said layer of solder on said pads; andreflowing said solder to form a solder joint connection with improved stand-off.
  • 17. The method as set forth in claim 16 wherein said conductive plate is a copper plate.
  • 18. The method as set forth in claim 17 wherein said protrusions are formed in said one surface of said copper plate by stamping dimples into the said surface opposing said one surface.
  • 19. The method as set forth in claim 18 wherein said layer of metal plated on the said opposing surface thereof is silver.
  • 20. The method as set forth in claim 19 wherein said layer of solder formed on said respective pads of said substrate includes solder formed beneath the chip attach region of said copper plate.