Claims
- 1. A semiconductor device comprising:
a multi-layer wiring board including a plurality of insulation layers and a plurality of circuit pattern layers alternately laminated with said insulation layers, one of said circuit pattern layers being formed on a first side and a second side of each of said insulation layers, each of said insulation layers having a plurality of inner via holes extending between said first side and said second side of each of said insulation layers and electrically connecting said circuit pattern layers so as to form a three-dimensional wiring pattern; a first semiconductor element including electrodes and being mounted on a first side of said multi-layer wiring board; and a second semiconductor element including electrodes and having a front surface and a back surface, said front surface of said second semiconductor being mounted on a second side of said multi-layer wiring board opposite said first semiconductor element such that said electrodes of said second semiconductor element and said electrodes of said first semiconductor element are connected by said three-dimensional wiring pattern, said multi-layer wiring board being bent around said second semiconductor element and bonded to said back surface of said second semiconductor element so as to cover said back surface of said second semiconductor element.
- 2. The device of claim 1, wherein each of said insulation layers comprise a resin-impregnated fiber sheet.
- 3. The device of claim 2, wherein said first semiconductor element and said second semiconductor element are mounted face down on said multi-layer wiring board by flip chip bonding.
- 4. The device of claim 1, wherein said first semiconductor element and said second semiconductor element are mounted face down on said multi-layer wiring board by flip chip bonding.
- 5. The device of claim 1, wherein said electrodes of one of said first semiconductor element and said second semiconductor element are formed in an area array arrangement.
- 6. The device of claim 1, wherein said electrodes of said first semiconductor element are formed in an area array arrangement, and said electrodes of said second semiconductor element are formed in a peripheral arrangement, said first semiconductor element and said second semiconductor element being mounted face down on said multi-layer wiring board by flip chip bonding.
- 7. The device of claim 1, wherein said second semiconductor element comprises an electronic component including electrodes, said first semiconductor element being mounted face down on said multi-layer wiring board by flip chip bonding such that said electrodes of said first semiconductor element and said electrodes of said electronic component are connected by said three-dimensional wiring pattern.
- 8. The device of claim 7, wherein said electronic component comprises a bypass capacitor.
- 9. The device of claim 1, wherein said first semiconductor element includes projections and said second semiconductor element includes projections, said projections of said first semiconductor element and said projections of said second semiconductor element extending perpendicular to said multi-layer wiring board so as to overlap.
- 10. The device of claim 1, further comprising a third semiconductor element mounted on said multi-layer wiring board by flip chip bonding so as to oppose said back surface of said second semiconductor element via said multi-layer wiring board.
- 11. The device of claim 10, further comprising:
a mother multi-layer wiring board having a circuit pattern formed on a surface thereof, said third semiconductor element being mounted on said mother multi-layer wiring board such that said mother multi-layer wiring board and said third semiconductor element are electrically connected.
- 12. The device of claim 1, further comprising:
a mother multi-layer wiring board having a circuit pattern formed on a surface thereof, said multi-layer wiring board being mounted on said mother multi-layer wiring board such that said mother multi-layer wiring board and said multi-layer wiring board are electrically connected.
- 13. A semiconductor device comprising:
a wiring board including an insulation layer having a first side and a second side, said wiring board further including a circuit pattern layer formed on each of said first side and said second side, said insulation layer having a plurality of inner via holes extending between said first side and said second side so as to electrically connect said circuit pattern layers such that a three-dimensional wiring pattern is formed; a first semiconductor element including electrodes and being mounted on a first side of said wiring board; and a second semiconductor element including electrodes and having a front surface and a back surface, said front surface of said second semiconductor being mounted on a second side of said wiring board opposite said first semiconductor element such that said electrodes of said second semiconductor element and said electrodes of said first semiconductor element are connected by said three-dimensional wiring pattern, said wiring board being bent around said second semiconductor element and bonded to said back surface of said second semiconductor element so as to cover said back surface of said second semiconductor element.
- 14. The device of claim 13, wherein said insulation layer comprises a resin-impregnated fiber sheet.
- 15. The device of claim 14, wherein said first semiconductor element and said second semiconductor element are mounted face down on said wiring board by flip chip bonding.
- 16. The device of claim 13, wherein said first semiconductor element and said second semiconductor element are mounted face down on said wiring board by flip chip bonding.
- 17. The device of claim 13, wherein said electrodes of one of said first semiconductor element and said second semiconductor element are formed in an area array arrangement.
- 18. The device of claim 13, wherein said electrodes of said first semiconductor element are formed in an area array arrangement, and said electrodes of said second semiconductor element are formed in a peripheral arrangement, said first semiconductor element and said second semiconductor element being mounted face down on said wiring board by flip chip bonding.
- 19. The device of claim 13, wherein said second semiconductor element comprises an electronic component including electrodes, said first semiconductor element being mounted face down on said wiring board by flip chip bonding such that said electrodes of said first semiconductor element and said electrodes of said electronic component are connected by said three-dimensional wiring pattern.
- 20. The device of claim 19, wherein said electronic component comprises a bypass capacitor.
- 21. The device of claim 13, wherein said first semiconductor element includes projections and said second semiconductor element includes projections, said projections of said first semiconductor element and said projections of said second semiconductor element extending perpendicular to said wiring board so as to overlap.
- 22. The device of claim 13, further comprising a third semiconductor element mounted on said wiring board by flip chip bonding so as to oppose said back surface of said second semiconductor element via said wiring board.
- 23. The device of claim 22, further comprising:
a mother multi-layer wiring board having a circuit pattern formed on a surface thereof, said third semiconductor element being mounted on said mother multi-layer wiring board such that said mother multi-layer wiring board and said third semiconductor element are electrically connected.
- 24. The device of claim 13, further comprising:
a mother multi-layer wiring board having a circuit pattern formed on a surface thereof, said wiring board being mounted on said mother multi-layer wiring board such that said mother multi-layer wiring board and said wiring board are electrically connected.
Priority Claims (1)
Number |
Date |
Country |
Kind |
P 09-250304 |
Sep 1997 |
JP |
|
Parent Case Info
[0001] This application is a Continuation-in-Part of Ser. No. 09/153,069, filed Sep. 15, 1998.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09153069 |
Sep 1998 |
US |
Child |
09725283 |
Nov 2000 |
US |