Patent Application
20250167065
The present application claims priority under 35 U.S.C. § 119 (a) to Korean Patent Application No. 10-2023-0161079 filed in the Korean Intellectual Property Office on Nov. 20, 2023, which is incorporated herein by reference in its entirety.
Various embodiments of the disclosed technology generally relate to a semiconductor package including a heat dissipation member and a method for manufacturing the same.
An electronic product is increasingly required to process high-capacity data even while being decreased in volume. Accordingly, there is a growing need to increase the degree of integration of a semiconductor device used in the electronic product.
As the degree of integration of the semiconductor device increases, heat generated during the operation of the semiconductor device may adversely affect the operation of the element of a semiconductor chip.
In an embodiment, a semiconductor package may include: a heat dissipation member having a plurality of through holes which pass through a first surface of the heat dissipation member; a semiconductor chip disposed on the first surface of the heat dissipation member; a vertical connector connected to the semiconductor chip; a molding member sealing the semiconductor chip, sealing the vertical connector, and filling the plurality of through holes; and a redistribution layer disposed on the molding member.
In an embodiment, a method for manufacturing a semiconductor package may include: forming, on a carrier substrate, a heat dissipation member having a plurality of through holes; disposing a semiconductor chip on the heat dissipation member; forming a vertical connector connected to the semiconductor chip; forming a molding member which seals the semiconductor chip and the vertical connector and fills the plurality of through holes; and forming a redistribution layer on the molding member.
Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same elements will be designated by the same reference numerals although they are shown in different drawings. Further, in the following description of the present disclosure, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present disclosure rather unclear. It is to be noticed that the terms “comprising,” “having,” “including” and so on, used in the description and claims, should not be interpreted as being restricted to the means listed thereafter unless specifically stated otherwise. Where an indefinite or definite article is used when referring to a singular noun, e.g., “a,” “an” and “the,” this may include a plural of that noun unless specifically stated otherwise.
Also, in describing the components of the disclosure, there may be terms used like first, second, A, B, (a), and (b). These are solely for the purpose of differentiating one component from another component but do not limit the substances, order, sequence, or number of the components.
In descriptions for the positional relationships of components, in the case where it is described that at least two components are “connected,” “coupled” or “linked,” it is to be understood that the at least two components may be directly “connected,” “coupled” or “linked” but may be indirectly “connected,” “coupled” or “linked” with another component interposed between the two components. Here, another component may be included in at least one of the at least two components which are “connected,” “coupled,” or “linked” with each other.
In descriptions for time flow relationships of components, an operating method or a fabricating method, in the case where pre and post relationships in terms of time or pre and post relationships in terms of flow are described, for example, by “after,” “following,” “next,” or “before,” non-continuous cases may be included unless “immediately” or “directly” is used.
In the case where a numerical value for a component or its corresponding information (e.g., level, etc.) is mentioned, even though there is no separate explicit description, the numerical value or its corresponding information can be interpreted as including an error range that may be caused by various factors (for example, a process variable, an internal or external shock, noise, etc.).
Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings. Various embodiments are directed to providing a semiconductor package including a heat dissipation member and a method for manufacturing the same. According to some embodiments of the disclosed technology, it is possible to provide a semiconductor package including a heat dissipation member which has a plurality of through holes filled with a molding member, and a method for manufacturing the same.
Referring to
A heat dissipation member 10 may be disposed in the mounting region MR, and may include a plurality of through holes OP which pass through one surface 10a. For example, the through holes OP may extend from the one surface 10a to the other surface 10b of the heat dissipation member 10, and may pass through the other surface 10b. The other surface 10b of the heat dissipation member 10 may be a surface which is opposite to the one surface 10a. The other surface 10b of the heat dissipation member 10 may be a surface which is located farther away from a first semiconductor chip 21 than the one surface 10a. The one and other surfaces 10a and 10b of the heat dissipation member 10 are also referred to as the first and second, respectively, surfaces 10a and 10b of the heat dissipation member 10. The heat dissipation member 10 may have a mesh structure which has the plurality of through holes OP.
As illustrated in
The heat dissipation member 10 may include a material with a greater Young's modulus than a molding member 40 which will be described later. The heat dissipation member 10 may be made of metal.
The heat dissipation member 10 may have a structure in which a barrier metal layer 11, a seed metal layer 12, and a plated metal layer 13 are stacked. The seed metal layer 12 may be disposed on the barrier metal layer 11, and the plated metal layer 13 may be disposed on the seed metal layer 12. The barrier metal layer 11, the seed metal layer 12, and the plated metal layer 13 may have the same layout structure.
For example, the seed metal layer 12 and the plated metal layer 13 may include the same material. The seed metal layer 12 and the plated metal layer 13 may include copper (Cu). The barrier metal layer 11 may include metal with a lower ionization tendency than the plated metal layer 13. For example, the barrier metal layer 11 may include at least one of Titanium (Ti), titanium-tungsten (TiW), and Nickel (Ni). A metal having a lower ionization tendency refers to the metal having a more stable electronic configuration and thus a higher ionization energy.
The upper surface of the plated metal layer 13 may configure the one surface 10a of the heat dissipation member 10, and the lower surface of the barrier metal layer 11 may configure the other surface 10b of the heat dissipation member 10. The upper surface of the plated metal layer 13 is covered with the molding member 40 and is not exposed to the outside of the semiconductor package 1, but the lower surface of the barrier metal layer 11 is exposed to the outside of the semiconductor package 1. As the barrier metal layer 11 which has a surface exposed to the outside of the semiconductor package 1 is made of metal with a low ionization tendency, oxidation of the heat dissipation member 10 may be suppressed.
First to fourth semiconductor chips 21 to 24 may be stacked on the one surface 10a of the heat dissipation member 10.
Each of the first to fourth semiconductor chips 21 to 24 may include nonvolatile memory such as flash memory, PRAM (phase-change random-access memory), and MRAM (magnetoresistive random-access memory), or volatile memory such as DRAM (dynamic random-access memory) and SRAM (static random-access memory), or non-memory such as a logic circuit, but is not limited thereto.
Each of the first to fourth semiconductor chips 21 to 24 may have a front side on which a chip pad (one of 21A to 24A) is disposed and a back side which faces oppositely to the front side. The chip pad (one of 21A to 24A) may be electrically connected to an integrated circuit in the semiconductor chip (one of 21 to 24).
The first to fourth semiconductor chips 21 to 24 may be stacked on the heat dissipation member 10 in a face-up type so that the back sides thereof face the heat dissipation member 10.
First to fourth adhesive layers 61 to 64 may be attached to the back sides, respectively, of the first to fourth semiconductor chips 21 to 24. Each of the first to fourth semiconductor chips 21 to 24 may be attached to the semiconductor chip (one of 21 to 23) or the heat dissipation member 10 which is located immediately thereunder, using the adhesive layer (one of 61 to 64). The first to fourth semiconductor chips 21 to 24 may be offset-stacked on each other to expose the respective chip pads 21A to 24A.
Although
First to fourth vertical connectors 31 to 34 may be connected to the first to fourth semiconductor chips 21 to 24, respectively.
Each of the first to fourth vertical connectors 31 to 34 may extend in a vertical direction with one end thereof connected to a corresponding one of the chip pads 21A to 24A of the first to fourth semiconductor chips 21 to 24. The first to fourth vertical connectors 31 to 34 may be configured with interconnection members which extend substantially vertically or are erected substantially vertically from the surfaces of the first to fourth semiconductor chips 21 to 24.
The first to fourth vertical connectors 31 to 34 may provide paths through which electrical signals are transmitted to the first to fourth semiconductor chips 21 to 24, respectively. The first to fourth vertical connectors 31 to 34 may be formed of one or more conductive metals, such as gold (Au) or copper (Cu), for example.
The first to fourth vertical connectors 31 to 34 may be vertical bonding wires. Alternatively, among the first to fourth vertical connectors 31 to 34, the fourth vertical connector 34 connected to the fourth semiconductor chip 24 located uppermost may be a conductive bump, and the first to third vertical connectors 31 to 33 connected to the first to third semiconductor chips 21 to 23 excluding the fourth semiconductor chip 24 may be vertical bonding wires.
The molding member 40 is formed to cover the one surface 10a of the heat dissipation member 10, fill the through holes OP of the heat dissipation member 10, and cover the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34. The molding member 40 may serve to seal the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34 to protect the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34 from an external environment. The molding member 40 may include an encapsulant material such as an epoxy molding compound (EMC) material. The encapsulant material may include, for example, an epoxy resin component and fillers dispersed therein.
As the molding member 40 fills the through holes OP of the heat dissipation member 10, the heat dissipation member 10 may be combined with the molding member 40.
The heat dissipation member 10 combined with the molding member 40 may serve as a protective layer 10 and 40 which protects the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34. As the heat dissipation member 10 is combined with the molding member 40, the volume fraction occupied by the molding member 40 in the semiconductor package 1 may decrease. As described above, because the heat dissipation member 10 may be made of a material with a greater Young's modulus than the molding member 40, the heat dissipation member 10 may serve to increase the body strength of the protective layer 10 and 40.
The molding member 40 may include protrusions 41 which fill the through holes OP. Inner side surfaces 10d of the heat dissipation member 10 which are provided by the through holes OP may contact the protrusions 41 of the molding member 40.
The inner side surfaces 10d of the heat dissipation member 10 may be surfaces which are positioned in the through holes OP. In the disclosed technology, the through holes OP may pass through the one surface 10a and the other surface 10b of the heat dissipation member 10, and the inner side surfaces 10d of the heat dissipation member 10 may be surfaces which connect the one surface 10a and the other surface 10b. The ends of the protrusions 41 of the molding member 40 may be disposed on the same plane as the other surface 10b of the heat dissipation member 10. The molding member 40 might not extend to the other surface 10b of the heat dissipation member 10.
By forming the plurality of through holes OP in the heat dissipation member 10 and filling the through holes OP of the heat dissipation member 10 with the molding member 40, the contact area between the molding member 40 and the heat dissipation member 10 may increase. Accordingly, stress caused by a difference in properties such as ductility and thermal expansion coefficient between a material configuring the heat dissipation member 10 and a material configuring the molding member 40 may be mitigated or alleviated. Therefore, it is possible to mitigate, suppress, or prevent a delamination or/and a crack from occurring at the interface between the heat dissipation member 10 and the molding member 40 due to the stress.
The molding member 40 may be configured to surround outer side surfaces 10c of the heat dissipation member 10. The outer side surfaces 10c of the heat dissipation member 10 may be surfaces which connect the outer edge of the one surface 10a and the outer edge of the other surface 10b. The heat dissipation member 10 might not be disposed on the side surfaces of the molding member 40. The side surfaces of the molding member 40 may be surfaces which are cut in a sawing process that individualizes the semiconductor package 1. Because the heat dissipation member 10 is not disposed on the surfaces which are cut in the sawing process, a stress applied to a material during the sawing process may decrease, and it is possible to mitigate, suppress, or prevent the occurrence of a burr.
A redistribution layer 50 is provided on the molding member 40. The redistribution layer 50 may include redistribution lines 51 and a dielectric layer 52. The redistribution lines 51 may be connected to the vertical connectors 31 to 34 and may be connected to the semiconductor chips 21 to 24 through the vertical connectors 31 to 34. The redistribution lines 51 may be insulated from each other by the dielectric layer 52.
External connection terminals 70 may be connected to some of the redistribution lines 51. Although not illustrated, some of the redistribution lines 51 may include ball lands. The dielectric layer 52 may have openings which expose the ball lands. The external connection terminals 70 may be attached to the ball lands. The external connection terminals 70 may include solder balls.
As illustrated in
Although not illustrated in the drawings, the fiducial mark PM may be disposed at the same height level as the plated metal layer 13 of the heat dissipation member 10. The fiducial mark PM may be formed together with the plated metal layer 13 of the heat dissipation member 10 and may be made of the same material as the plated metal layer 13, but is not limited thereto. The fiducial mark PM may be formed in a separate process from the plated metal layer 13, or it may be made of a different material from the plated metal layer 13. Although
Referring to
The barrier metal layer 11 and the seed metal layer 12 of the heat dissipation member 10 may be disposed in the mounting region MR and the peripheral region ER, and the plated metal layer 13 may be disposed in the mounting region MR. The through holes OP may pass through the plated metal layer 13, but might not pass through the barrier metal layer 11 and the seed metal layer 12. The through holes OP may pass through the plated metal layer 13 to expose the seed metal layer 12. The plated metal layer 13 may have a thickness larger than the sum of the thicknesses of the seed metal layer 12 and the thickness of the barrier metal layer 11.
The molding member 40 may be configured to surround outer side surfaces 13c of the plated metal layer 13. The outer side surfaces 13c may be surfaces which connect the outer edge of a first surface 13a and the outer edge of a second surface 13b of the plated metal layer 13. The first surface 13a of the plated metal layer 13 may be a surface on which the first semiconductor chip 21 is mounted, and the second surface 13b of the plated metal layer 13 may be a surface which is opposite to the first surface 13a. The second surface 13b of the plated metal layer 13 may be a surface which is located farther away from the first semiconductor chip 21 than the first surface 13a and contacts the seed metal layer 12.
The side surfaces of the molding member 40 may be surfaces which are cut in a sawing process that individualizes a semiconductor package 1A. On the side surfaces of the molding member 40, only the barrier metal layer 11 and the seed metal layer 12 of the heat dissipation member 10 might be disposed, and the plated metal layer 13 might not be disposed. Because the plated metal layer 13 which has a relatively large thickness is not disposed on the surfaces which are cut in the sawing process, a stress applied to a material during the sawing process may decrease, and it is possible to mitigate, suppress, or prevent the occurrence of a burr.
Referring to
Process steps for manufacturing a semiconductor package based on an embodiment of the disclosed technology may be performed on the carrier substrate 100. The carrier substrate 100 may serve as a work table, a handling wafer, or a supporting substrate.
The carrier substrate 100 may be made of glass, silicon (Si), or metal. The carrier substrate 100 may have a circular shape such as a wafer.
A debonding layer 110 may be disposed on the carrier substrate 100. The debonding layer 110 may be made of a material which has an adhesion force and whose adhesion force may be reduced by at least one of chemical processing and optical processing. The carrier substrate 100 may be made of a transparent material.
Referring to
The heat dissipation member 10P may be a pre-structure of a heat dissipation member 10 of
The barrier metal layer 11 and the seed metal layer 12 may be formed on a mounting region MR and a peripheral region ER. The barrier metal layer 11 may include metal whose ionization tendency is different from metal included in the seed metal layer 12 and the plated metal layer 13. The barrier metal layer 11 may include metal whose ionization tendency is less than metal included in the seed metal layer 12 and the plated metal layer 13. For example, the seed metal layer 12 and the plated metal layer 13 may include copper (Cu), and the barrier metal layer 11 may include at least one of Titanium (Ti), titanium-tungsten (TiW), and Nickel (Ni). The barrier metal layer 11 and the seed metal layer 12 may be formed using electroless plating, evaporation, or sputtering, but are not limited thereto.
The mask layer PR may include a plurality of patterns which are separated by the mesh-shaped open regions. The mask layer PR is patterned to provide open regions which provide a template for the plated metal layer 13. The mask layer PR may cover the peripheral region ER so that the plated metal layer 13 is not formed in the peripheral region ER.
Through a plating process, the plated metal layer 13 is formed on the seed metal layer 12 which is exposed by the open regions of the mask layer PR. The plating process may use an electroless plating process or an electroplating process, but is not limited thereto. The plated metal layer 13 may have the same layout structure as the open regions of the mask layer PR. As a plurality of through holes OP corresponding to the plurality of patterns configuring the mask layer PR are formed in the plated metal layer 13, the plated metal layer 13 may have a mesh-shaped layout structure.
In the drawings of the present specification, it is illustrated that the thickness of the plated metal layer 13 is similar to the sum of the thickness of the barrier metal layer 11 and the thickness of the seed metal layer 12. However, the thickness of the barrier metal layer 11 and the thickness of the seed metal layer 12 are illustrated by being exaggerated, and the thickness of the plated metal layer 13 is larger than the sum of the thickness of the barrier metal layer 11 and the thickness of the seed metal layer 12.
In the process of forming the plated metal layer 13, a fiducial mark PM may be additionally formed together with the plated metal layer 13. The fiducial mark PM may be formed by patterning the mask layer PR to further include an opening region which provides a template for the fiducial mark PM and using the plating process of forming the plated metal layer 13. Meanwhile, for another example, the fiducial mark PM may be formed separately from the plated metal layer 13. A fiducial mark may be formed on the seed metal layer 12 before or after forming the plated metal layer 13.
The mask layer PR may be formed using photoresist, and may be removed after forming the plated metal layer 13.
Referring to
The barrier metal layer 11 and the seed metal layer 12 are etched using the plated metal layer 13 as an etch mask. Accordingly, the barrier metal layer 11 and the seed metal layer 12 may have substantially the same layout structure as the plated metal layer 13. The barrier metal layer 11 and the seed metal layer 12 may be disposed in the mounting region MR, and the barrier metal layer 11 and the seed metal layer 12 of the peripheral region ER may be removed. The barrier metal layer 11 and the seed metal layer 12 may have a mesh-shaped layout structure. By this fact, the heat dissipation member 10 having a structure in which the barrier metal layer 11, the seed metal layer 12, and the plated metal layer 13 are stacked is formed.
Referring to
A chip mounter (not illustrated) which is used in the process of disposing the first to fourth semiconductor chips 21 to 24 may recognize the fiducial mark PM (see
Each of the first to fourth semiconductor chips 21 to 24 may be attached to the semiconductor chip (one of 21 to 23) or the heat dissipation member 10 which is located immediately thereunder, using an adhesive layer (one of 61 to 64).
The first to fourth semiconductor chips 21 to 24 may be offset-stacked on each other to expose chip pads 21A to 24A. For example, the intermediate second and third semiconductor chips 22 and 23 may be offset-stacked in a first offset direction D1 with respect to the lowermost first semiconductor chip 21, and the uppermost fourth semiconductor chip 24 may be offset-stacked in a second offset direction D2 opposite to the first offset direction D1.
As the fourth semiconductor chip 24 is offset-stacked in the second offset direction D2 opposite to the first offset direction D1 being the offset direction of the second and third semiconductor chips 22 and 23, the layout area occupied by the first to fourth semiconductor chips 21 to 24 may be reduced.
Referring to
The first to fourth vertical connectors 31 to 34 may be formed of a conductive metal material such as gold (Au) or copper (Cu). The first to fourth vertical connectors 31 to 34 may be configured with interconnection members which extend substantially vertically or are erected substantially vertically from the surfaces of the chip pads 21A to 24A of the first to fourth semiconductor chips 21 to 24.
The first to fourth vertical connectors 31 to 34 which are connected to the first to fourth semiconductor chips 21 to 24, respectively, may be formed through a wire bonding process using wire bonding equipment (not illustrated). Alternatively, the first to third vertical connectors 31 to 33 which are connected to the first to third semiconductor chips 21 to 23 may be formed through a wire bonding process using wire bonding equipment, and the fourth vertical connector 34 which is connected to the fourth semiconductor chip 24 may be formed using a bump forming process. That is to say, a conductive bump may be formed on the chip pad 24A of the uppermost fourth semiconductor chip 24 without forming a bonding wire. The conductive bump may include copper (Cu).
The molding member 40 may be formed to cover and encapsulate the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34, cover the one surface of the heat dissipation member 10 and fill the through holes OP of the heat dissipation member 10.
The molding member 40 may be formed through a molding process using a liquid sealant. The molding process may include mounting, in a mold (not illustrated), the carrier substrate 100 which is provided with the first to fourth semiconductor chips 21 to 24 and the first to fourth vertical connectors 31 to 34, pouring the liquid sealant into the mold, pressing the mold, and curing the poured sealant. The sealant may include an EMC (epoxy molding compound).
Referring to
The thinning process may include a chemical mechanical polishing (CMP) or grinding process. The upper surface of the molding member 40 may be lowered by the thinning process. As a result of performing the thinning process, the first to fourth vertical connectors 31 to 34 may be exposed on the upper surface of the molding member 40.
Referring to
The redistribution layer 50 may include redistribution lines 51 and a dielectric layer 52 which insulates the redistribution lines 51 from each other. Some of the redistribution lines 51 may be connected to the first to fourth vertical connectors 31 to 34.
Referring to
Although not illustrated in detail, some of the redistribution lines 51 may include ball lands. The dielectric layer 52 may include openings which expose the ball lands. The external connection terminals 70 may be attached to the ball lands. The external connection terminals 70 may include solder balls.
After reducing the adhesion force of the debonding layer 110 using at least one of chemical processing and optical processing, the carrier substrate 100 may be removed and separated.
Thereafter, the redistribution layer 50 and the molding member 40 may be cut along a sawing line defined in the peripheral region ER through a sawing process. Because the heat dissipation member 10 does not exist in the peripheral region ER, a stress applied to a material during the sawing process may decrease, and occurrence of a burr may be mitigated or suppressed to obtain a clean cut surface.
Although some embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, and/or substitutions are possible, without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered in a descriptive sense only and not for limiting the technological scope. The technological scope of the present disclosure is not limited by the presented embodiments and the accompanying drawings.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0161079 | Nov 2023 | KR | national |
