Patent Application
20240063133
Device performance and cost pressures drive a continuous and increasing demand for denser and cheaper multichip devices. Such density improvements could readily impact larger and more complex devices but require correspondingly dense interconnections between tightly packed chips. For example, processor performance can be improved by interconnecting processor and memory chips in smaller spaces or by packing more processor and memory chips into the same space. More complex systems can be made better or less expensive with denser and cheaper multichip devices.
Structures and methods are needed to improve multichip devices and the larger systems they make up. It is with respect to these and other considerations that the present improvements have been needed. Such improvements may become critical as the desire to improve multichip devices becomes even more widespread.
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements, e.g., with the same or similar functionality. The disclosure will be described with additional specificity and detail through use of the accompanying drawings:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. The various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter.
References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled.
The terms “over,” “to,” “between,” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship, an electrical relationship, a functional relationship, etc.).
The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”
The vertical orientation is in the z-direction and recitations of “top,” “bottom,” “above,” and “below” refer to relative positions in the z-dimension with the usual meaning. However, embodiments are not necessarily limited to the orientations or configurations illustrated in the figure. The term “aligned” (i.e., vertically or laterally) indicates at least a portion of the components are aligned in the pertinent direction while “fully aligned” indicates an entirety of the components are aligned in the pertinent direction.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition is the first constituent. The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent.
Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
Views labeled “cross-sectional,” “profile,” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z and y-z planes, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.
Materials, structures, and techniques are disclosed to improve die density in multichip composite devices. A multichip composite device may have a number of chips or dies that are integrated and formed into a quasi-monolithic structure. For example, a quasi-monolithic structure may be a structure that integrates integrated circuit (IC) or other dies and couples base dies and other dies, chiplets, and the like to form a composite structure of a system, such as a processing system. As a composite structure, a multichip composite device has multiple components, such as chips, including active dies; dielectric material on and between the chips; and metallization layers coupled to the chips. Furthermore, a handle die or carrier may be attached to the multichip composite device, and the handle die or carrier may be part of the quasi-monolithic structure.
Chip (or die) thicknesses can be reduced and device densities increased by separating the thickest metallization layers from dies in multichip devices and stacking the dies over the thickest metallization layers, which may be in a standalone die. Dies may be coupled over the metallization layers, or the metallization layers may be coupled or formed over the dies. Splitting the metallization layers into on- and off-die stacks provides manufacturing flexibility. The split-out or off-die metallization layers can be processed separately at the wafer level or built up over dies bonded in a composite device. The off-die metallization layers can be processed as a separate die or using a handle die or carrier as a substrate. Dies can be manufactured using different process flows and bonded together, e.g., in a dense stack. The dies can be encapsulated in an inorganic dielectric material and densely interconnected with through-dielectric vias (TDVs) through the inorganic dielectric material. The reduced-thickness dies allow the inorganic dielectric material to be thinner and associated TDVs to be shorter. Packaging the dies in inorganic dielectric material protects the dies, vias, their interconnections, etc. and allows for, e.g., hybrid bonding and high-temperature annealing. Reducing die thicknesses lowers stresses caused by, e.g., differing thermal-expansion rates. A structural substrate may be used, as necessary, to provide mechanical strength to the thin dies. Hybrid bonding and wafer-level processing of the metallization layers enables a very fine interconnect pitch. Device density can be improved by sharing metallization layers amongst dies and interconnecting dies between metallization layers above and below dies. Other device interconnections can be included in a metallization die. More dies and metallization layers can be stacked by providing device interconnections on backside metallization layers. Vias can be used for routing power and signals to the backside device interconnects.
First die 110 is coupled to at least the uppermost metallization layer 101A of the stack of metallization layers 101 at an interface 105. In some embodiments, first die 110 is hybrid bonded to the uppermost layer of the stack of metallization layers 101, and interface 105 is a hybrid-bond interface. In some such embodiments, a bond pad on a surface of first die 110 is bonded to a bond pad on a surface of metallization layers 101. In some embodiments, a metallization structure, e.g., via V4, at the bottom of the stack of metallization layers 101 contacts a metallization structure, e.g., an M4 line, at the top of first die 110. In some such embodiments, there is no bond pad (or a single bond pad) at interface 105 between first die 110 and metallization layers 101. Second die 120 is over first die 110 and coupled to first die 110 at their overlap. In the embodiment of
First and second dies 110, 120 may include passive and/or active devices and multiple intradie metallization layers. Intradie metallization layers, like those within first and second dies 110, 120, do not extend laterally outside a die footprint. Interdie metallization layers, in contrast, extend laterally beyond one or more edges of a die and outside a die footprint. Metallization layers 101 coupled to first die 110 are intradevice metallization layers within multichip composite device 100 but may include interdie metallization layers, layers that are for more than a single die. Such interdie metallization layers can extend laterally beyond one or more edges of multiple dies and between multiple die footprints. Intradevice metallization layers do not extend laterally outside a device footprint, but may be interdie metallization layers. In some embodiments, metallization layers 101 include metallization layers only needed or used by, e.g., first die 110. In some embodiments, metallization layers 101 include metallization layers shared by first and second dies 110, 120. For example, power or signal lines can route from the bottom of first die 110 through metallization layers 101 and first-level TDVs 103 to second die 120. In some embodiments, power or signal lines can route from the top of first die 110 through hybrid-bond interface 115 to second die 120. Power or signals can route from off-device to first or second dies 110, 120 through metallization layers 101.
Metallization layers 101 extend beyond first and second dies 110, 120 in both the x and y directions. First and second dies 110, 120 are fully within the area of multichip composite device 100 spanned by metallization layers 101. For example, metallization layers 101 may have an area within multichip composite device 100 defined by a width W and a length L. The length of first die 110 is less than, and completely included within, the length L of metallization layers 101. The width of first die 110 is less than, and completely included within, the width W of metallization layers 101. Likewise, the length of second die 120 is less than, and completely included within, the length L of metallization layers 101, and the width of second die 120 is less than, and completely included within, the width W of metallization layers 101. In some embodiments, first and second dies 110, 120 are arranged entirely within the defined area such that no edge of first and second dies 110, 120 extends beyond the edges of metallization layers 101. In other embodiments, first or second dies 110, 120 extend beyond the area of metallization layers 101 (W×L). In some embodiments, metallization layers 101 substantially occupy the area of multichip composite device 100, and the area of metallization layers 101 (W×L) defines the area of multichip composite device 100. In some embodiments, structural substrate 155 also shares the area (W×L) such that edges of metallization layers 101 and the edges of structural substrate 155 are substantially vertically aligned.
Metallization layers 101 may have some similarities with IC dies. For example, metallization layers 101 may resemble the upper metallization layers in a typical IC die. In some embodiments, metallization layers 101 include layers of thick metal interspersed within one or more insulator materials. In some such embodiments, the metal is copper. In other embodiments, the metal is aluminum. In some embodiments, more than one metal is used.
As shown in
In some embodiments, similar to many IC dies, metallization layers 101 are a stack of layers where the uppermost layer is the thickest, the lowermost layer is the thinnest, and each layer is as thick or thicker than the layer below. In some embodiments, metallization layer pitches for individual metallization layers 101 are 0.5 μm thick and thicker. Metallization layer dimensions can be defined by at least a couple of parameters. A metal line thickness, tm, is defined as the vertical distance from a bottom to a top of the substantially horizontal metal line. A via length, Lv, is defined as the vertical distance spanned by a via between vertically adjacent metal lines, i.e., from a bottom of a substantially horizontal metal line to a top of the substantially horizontal metal line below. A metallization layer pitch is defined as the vertical distance from a top of a substantially horizontal metal line to a top of the substantially horizontal metal line below, i.e., for a given metallization layer, the metal line thickness, tm, plus the via length, Lv. For example, a metallization layer, e.g., M10 in metallization layers 101, might have a metal line thickness (tm) of 4 μm, a via length (Lv) of 2 μm, and a metallization layer pitch of 6 μm.
As shown in
In many IC dies, most of a die's thickness comes from the thickest metallization layers. In some embodiments, first or second dies 110, 120 are less than 10 μm thick. In some embodiments, first or second dies 110, 120 are less than 4 μm thick. In some embodiments, the thickest intradie metal line thickness (tm) of first or second dies 110, 120 is less than 2 μm. Removing the thickest metallization layers from first or second dies 110, 120 can enable yet thinner first and second dies 110, 120. In some embodiments, first or second dies 110, 120 are less than 2 μm thick. In some embodiments, the thickest intradie metal line thickness (tm) of first or second dies 110, 120 is less than 1 μm. In some embodiments, the thickest intradie metal line thickness (tm) of first or second dies 110, 120 is less than 750 nm or less than 500 nm. In some embodiments, first or second dies 110, 120 are less than 1 μm thick. In some embodiments, the thinnest metal line thickness (tm) within stack of metallization layers 101 is thicker than the thickest intradie metal line thickness (tm) of first or second dies 110, 120. In some embodiments, the thinnest metal line thickness (tm) of metallization layers 101 is 1 μm. In some embodiments, the thinnest metal line thickness (tm) of metallization layers 101 is 500 nm or 750 nm. More of the metallization layers can be removed from first or second dies 110, 120 and deployed in metallization layers 101 to minimize thicknesses of first or second dies 110, 120. In some embodiments, first or second dies 110, 120 are less than 750 nm thick. In some embodiments, first or second dies 110, 120 are less than 500 nm thick.
Returning to
Structural substrate 155 may be coupled to multichip composite device 100 by any suitable means. In some embodiments, structural substrate 155 is coupled by a bond, such as a surface-activated bond, to inorganic dielectric material 102 over second die 120 (as shown). In some embodiments, inorganic dielectric material 102 is laterally adjacent to, but not over, second die 120. In some such embodiments, structural substrate 155 is bonded, such as direct or fusion bonded, directly to second die 120. In some such embodiments, second die 120 is predominantly silicon and is surface-activated bonded to structural substrate 155 of predominantly silicon, silicon carbide, gallium arsenide, or aluminum oxide. In some such embodiments, second die 120 is predominantly gallium arsenide and is surface-activated bonded to structural substrate 155 of predominantly silicon carbide. In some such embodiments, second die 120 is predominantly gallium arsenide or aluminum oxide and is surface-activated bonded to structural substrate 155 of predominantly silicon. In some such embodiments, second die 120 is predominantly aluminum oxide and is surface-activated bonded to structural substrate 155 of predominantly aluminum oxide. In some embodiments, with or without inorganic dielectric material 102 over second die 120, structural substrate 155 is coupled to multichip composite device 100 with an intermediate bonding layer. An intermediate bonding layer may include any suitable materials. In some embodiments, an intermediate bonding layer includes copper, silicon, or silicon nitride. Other materials may be used.
Inorganic dielectric material 102 may be any suitable material or combination of materials. An inorganic dielectric material is a dielectric material that lacks carbon-hydrogen bonds. Multiple materials may be used, e.g., to tune characteristics to sufficient or more desirable values. One or more materials may be used at one level, e.g., laterally adjacent first die 110, and one or more different materials may be used at a second level, e.g., laterally adjacent second die 120. Many inorganic materials have benefits relative to organic alternatives, e.g., higher thermal conductivity and moisture resistance. Advantageously (e.g., relative to a packaging material or mold compound), inorganic dielectric material 102 can withstand high temperatures and be conveniently formed. In some embodiments, inorganic dielectric material 102 includes a crystalline material. In some embodiments, inorganic dielectric material 102 includes silicon and oxygen. In some such embodiments, inorganic dielectric material 102 is predominantly silicon dioxide, which is a material convenient for many semiconductor manufactures and which can handle high temperatures. Unlike many organic materials, e.g., plastic mold compounds, many inorganic materials are able to withstand high-temperatures. Such materials can be present, e.g., when processing or adding metallization structures in or to multichip composite device 100 and when annealing, e.g., for direct bonding an additional die or substrate to multichip composite device 100. Advantageously, inorganic dielectric material 102 has good strength. In some embodiments, inorganic dielectric material 102 includes silicon and nitrogen. In some such embodiments, inorganic dielectric material 102 is predominantly silicon nitride, which is another convenient material with very high strength and which can handle extremely high temperatures. In some embodiments, inorganic dielectric material 102 includes combinations of dielectric materials. In some such embodiments, inorganic dielectric material 102 includes silicon dioxide and silicon nitride, e.g., in alternating layers. Other materials may be used.
Hybrid bonds may include direct (or fusion) bonds, e.g., of metallization structures to other metallization structures, such as of copper to copper. Hybrid bonds may include direct bonds between crystalline or other materials, e.g., of silicon to silicon. Hybrid bonds may include direct or surface-activated bonds between other materials, including dissimilar materials, such as of silicon to silicon dioxide. In some embodiments, hybrid bonds between structures include bonds between metallization structures and between crystalline materials. For example, in some such embodiments, hybrid bonds between, e.g., first and second dies 110, 120 include direct copper-copper and silicon-silicon bonds.
Device-level interconnect interfaces 108 may be any of various suitable structures. In some embodiments, device-level interconnect interfaces 108 are exposed metal portions of metallization layers 101, e.g., the top (or bottom) of a thick metal layer, and are substantially flush with an underside of metallization layers 101. Device-level interconnect interfaces 108 may be terminations of substantially vertical metallization structures extending from metallization structures extending horizontally through metallization layers 101, e.g., the end of a via connection extending vertically from a thick metal layer. In some embodiments, device-level interconnect interfaces 108 are, e.g., metal pads on such terminations, such as bond pads. In some embodiments, device-level interconnect interfaces 108 include materials, e.g., solder, for forming bonds with, e.g., system substrate 199. Device-level interconnect interfaces 108 may be planarized surfaces for hybrid bonding. In some embodiments, device-level interconnect interfaces 108 have fine pitches and other dimensions at a scale smaller than, e.g., conventional package substrates.
In the example of
In some embodiments, metallization layers 101 spans multiple upper-level dies, e.g., second and fourth dies 120A, 120B, that overlap a portion of a lower-level die, e.g., first die 110A. In some such embodiments, upper-level dies extend beyond the lower-level die in both lateral dimensions. In this way, e.g., four memory dies may be over, and coupled to, e.g., a central processor die. In other embodiments, metallization layers 101 spans multiple lower-level dies, e.g., first and third dies 110A, 110B, that overlap a portion of an upper-level die, e.g., fourth die 120B. In this way, e.g., a central processor die may be over, and coupled to, e.g., four memory dies.
In the example of
Multichip composite device 100 has a perimeter 200, e.g., as defined by structural substrate 155 (not shown), which encircles an area greater than the area of metallization layers 101 (W×L). Second and fourth dies 120A, 120B extend beyond metallization layers 101 in the y direction. Second and fourth dies 120A, 120B are not fully within the area of multichip composite device 100 spanned by metallization layers 101. Second and fourth dies 120A, 120B are coupled to a fifth die 110D (on the first level), which is coupled to an additional stack of metallization layers 101D. A sixth die 120D is coupled to first and third dies 110A, 110B, but extends beyond metallization layers 101 in the y direction.
In some embodiments, in addition to providing mechanical strength, structural substrate 155 helps remove heat from multichip composite device 100, e.g., to a heat spreader, etc. Having more lateral area, e.g., more than metallization layers 101, can help structural substrate 155 dissipate heat from multichip composite device 100. Rather than being substantially vertically aligned with metallization layers 101, structural substrate 155 may define a larger perimeter 200 of multichip composite device 100 for at least this reason.
Upper metallization layers 301 enable further thinning of second die 120 and provide additional available interconnections, which allows for increased routing flexibility. A thinner second die 120 results in thinner inorganic dielectric material 102 above first die 110 and shorter second-level TDVs 303. Thinner inorganic dielectric material 102 means less processing time, including dielectric deposition time and etching time to form second-level TDVs 303. Shorter second-level TDVs 303 mean reduced electrical resistances and less processing time, e.g., less etching time and less deposition time. Electrical routing flexibility is provided as the upper side of second die 120 can now be accessed through second-level TDVs 303 and upper metallization layers 301 (instead of only through second die 120), which allows for more efficient use of the area and volume of second die 120.
Upper device-level interconnect interfaces 408 may couple multichip composite device 100 to other dies, metallization layers, or substrates and may deliver power or signals to or from multichip composite device 100. The additional interconnections may provide routing flexibility, as well as more power or signal density.
Some vias are shown as having a circular cross-section, e.g., as substantially cylindrical, but vias may any suitable shape.
Returning to
The metallization layers may be formed by any suitable means and with any suitable materials. In some embodiments, the metallization layers include copper or aluminum. The metallization layers may be formed much as metallization layers are formed, e.g., in IC dies. For example, some embodiments use damascene, dual-damascene, and other deposition processes. Physical vapor deposition (PVD) or sputter may be used. In some embodiments, PVD is used to form a layer, e.g., a seed layer, of a metal. Electroplating may be used. In some embodiments, electroplating is use to form a metal, e.g., copper, over a seed layer of the metal. One or more barrier layers, e.g., a relatively thin layer of titanium or tantalum, may be used before depositing a bulk conductor, e.g., copper. In some embodiments, metallization layers are formed in inorganic dielectric material and over substrates of semiconductor materials, such as silicon. The use of such materials and techniques provides benefits relative to the materials and techniques typically used for the manufacture of, e.g., interposers and package substrates. Fine-pitch interconnects can be manufactured, e.g., at the die level, that do not require larger pitches, e.g., for soldering. Inorganic dielectric material allows for tightly (e.g., hermetically) sealed, multichip composite devices to be formed without the use of, e.g., organic mold compounds. For example, many packaging compounds have limitations related to, e.g., high temperatures and moisture resistance. A stack of metallization layers may be formed without these compounds, e.g., using inorganic dielectric material over and between metallization layers. In some embodiments, silicon dioxide or silicon nitride are used as insulators to form a stack of metallization layers.
Structural substrate 155 may also be received. In some embodiments, upper metallization layers 301 are received coupled, e.g., hybrid bonded, to structural substrate 155, which can be used as a handle die or carrier. Base interconnect interfaces 606 are on a top surface of lower metallization layers 101, and may be used for hybrid bonding first die 110 to lower metallization layers 101. Base interconnect interfaces 606 may be, e.g., bond pads. Base interconnect interfaces 606 may be similar to device-level interconnect interfaces 108 and may be any suitable structures. In some embodiments, lower metallization layers 101 are received without base interconnect interfaces 606. In some embodiments, bond pads are formed on lower metallization layers 101 after receipt.
First and second dies 110, 120 are within the area spanned by lower metallization layers 101. Dotted lines show the eventual positions (e.g., footprints) and relative alignments of first and second dies 110, 120 over lower metallization layers 101. Structural substrate 155 and upper metallization layers 301 span the entire area of the device and are vertically aligned with lower metallization layers 101.
Returning to
Coupling the first die and metallization layers may involve multiple operations. As an example, hybrid bonding may include, e.g., cleaning, polishing, planarizing, surface activation, and annealing. Hybrid bonding may include joining surfaces at elevated pressure and/or temperature, e.g., thermocompression. At least some of these operations may be performed before receiving the dies and metallization layers. Coupling between clean, activated, and substantially planar surfaces may be advantageous. Planarizing may include etching, grinding, and polishing (e.g., chemical mechanical polishing (CMP)). Some operations may perform multiple functions. For example, CMP may help clean and planarize surfaces, and some cleaning and surface-activation operations may overlap. Some operations, e.g., certain chemical cleans, may be more beneficial or may be altered for certain material or bond types, e.g., copper-copper or silicon-silicon bonds.
Various or multiple cleaning procedures may be used. Deionized water may be used, e.g., in a high-pressure water cleaning operation, before other chemical cleaning operations. In some embodiments, a plasma clearance operation is used before or after chemical cleaning operations. Multiple chemical solutions may be used to target particular contaminants. For example, a mixture of sulfuric acid and hydrogen peroxide may remove organic residues. In some embodiments, aqueous ammonia is mixed with hydrogen peroxide instead of sulfuric acid. In some embodiments, both mixtures are used sequentially. Other cleaning procedures use a first clean to remove particles and organic contaminants before a second clean removes metallic contaminants. The first clean may use a mixture of aqueous ammonia and aqueous hydrogen peroxide (in deionized water), and the second clean may use a mixture of aqueous hydrochloric acid and aqueous hydrogen peroxide. Some such embodiments employ a brief bath in a dilute solution of hydrofluoric acid between the first and second cleans. Advantageously, the substrate may be cleaned before an operation activating the substrate surface.
Surface activation may prepare die and metallization layer surfaces for bonding, e.g., direct bonding. Surface activation before bonding may improve bond strength or, if annealing to strengthen the bond, enable a reduced anneal temperature and length. Surface preparation increases the surface energy for bonding the surfaces, including bonding of their respective interconnect interfaces. Surface activation may be dry cleaning and can be used to remove, e.g., native oxides and adsorbed contaminants. Surface activation may be by, e.g., UV/ozone cleaning, fast-atom bombardment, or plasma treatments, etc. Plasma activation uses high-voltage and high-frequency stimulation of selected process gases to form a plasma and bombard the substrate surface, often with ions.
With sufficiently cleaned, activated, and planarized surfaces, bonding may begin as soon as the die and metallization layer surfaces are brought into contact, even at room temperature. After contact, even at room temperature, bond strength increases as more bonds form at the atomic level. Because the bonding begins immediately after contact, coupling operation 520 may include aligning the respective surfaces and structures, e.g., interconnect interfaces, before contact is made between the surfaces.
Bond strength may be improved by annealing. As with cleaning, annealing techniques may be influenced by embodiment parameters (e.g., the materials bonded, surface preparations used, etc.) in previous operations. Certain anneal operations may be paired with particular cleaning or activation operations. Annealing may be performed following other operations, and anneal temperatures may be limited by the material used in, or the structures formed on and within, the die and metallization layers. As such, the use of high-temperature capable inorganic dielectric material, e.g., instead of organic mold compounds, can be beneficial.
Inorganic dielectric material is formed over the composite device in operation 530. Inorganic dielectric material may be formed over the composite device multiple times, e.g., after coupling the metallization layers to the first die and after coupling the second die to the composite device. Inorganic dielectric material may be formed over inorganic dielectric material, e.g., when using multiple materials, such as in alternating layers. In some embodiments, a single inorganic dielectric material is deposited in successive applications, e.g., to form a sufficient thickness of inorganic dielectric material or with a satisfactory topography.
Inorganic dielectric material may be formed by any suitable means. Some inorganic dielectric materials are well-known and may be formed in well-controlled layers or at relatively high rates. In some embodiments, silicon dioxide is formed over the composite device by chemical vapor deposition (CVD). In some embodiments, silicon nitride is formed by low-pressure CVD (LPCVD). In some embodiments, silicon dioxide and silicon nitride are deposited in alternating layers, e.g., to control certain bulk characteristics for the composite dielectric material. Well-controlled oxide layers, e.g., of silicon dioxide, may be thermally grown. Wet (with H2O) or dry oxidation (O2) may be used. In some embodiments, plasma-enhanced CVD (PECVD) is used to form inorganic dielectric material layers of silicon dioxide. Other materials and methods may be used.
Operation 530 may include planarizing the inorganic dielectric material. For example, when forming inorganic dielectric material quickly or conformally, inorganic dielectric material may have an exposed surface that needs to be prepared, e.g., planarized, before further processing, e.g., bonding. Inorganic dielectric material may be removed by, e.g., grinding or CMP. In some embodiments, excess inorganic dielectric material is removed by plasma etching. In some embodiments, excess inorganic dielectric material is removed by wet etching. In some such embodiments, excess inorganic dielectric material is removed by a combination of laser exposure and wet etching.
First die 110 is shown with first-die interconnect interfaces 616, which may be similar to, e.g., base interconnect interfaces 606. In some embodiments, first-die interconnect interfaces 616 are bond pads. In some embodiments, first die 110 is received with first-die interconnect interfaces 616. In other embodiments, first-die interconnect interfaces 616 are formed on first die 110, e.g., over metallization structures, such as via connections.
Returning to
Vias of various heights and depths may be formed. In some embodiments, vias are formed through inorganic dielectric material laterally adjacent to a first-level die and over a base stack of metallization layers. A second-level die can then be coupled to the base stack of metallization layers by coupling to the vias. In some embodiments, vias are formed through inorganic dielectric material at a second level and over a first-level die. An upper stack of metallization layers can then be coupled to a first-level die by coupling to the vias. In some embodiments, tall vias are formed through inorganic dielectric material laterally adjacent to first- and second-level dies and over a base stack of metallization layers. In some such embodiments, tall vias are formed through two levels concurrently. In some embodiments, tall vias are formed by joining two single-level vias that were formed through each level separately. In other embodiments, tall vias are formed by forming vias through inorganic dielectric material on a second level over vias through inorganic dielectric material on a first level. An upper stack of metallization layers can be coupled to the base stack of metallization layers by coupling to the vias.
Returning to
As before, the surfaces to be coupled will advantageously be clean, activated, and substantially planar surfaces. Accordingly, operation 550 may include some or all of cleaning, polishing, planarizing, and surface activation of one or both surfaces (e.g., of the first and second dies, or of the second die and inorganic dielectric material and tops of TDVs), as well as annealing to strengthen formed bonds. Such an anneal strengthens, e.g., copper-copper bonds between second-die interconnect interfaces and TDVs, by improving the metal grain structures, e.g., by diffusion across the bonded interface. Other, e.g., SiO2—SiO2, bonding, also benefits from diffusion, etc. caused by a high-temperature anneal. Such an anneal may benefit from, or be enabled by, the use of an inorganic dielectric material (e.g., instead of an organic dielectric incapable of sufficiently high anneal temperatures).
Second die 120 is shown with second-die interconnect interfaces 626, which may be similar to, e.g., base interconnect interfaces 606 or first-die interconnect interfaces 616. In some embodiments, second-die interconnect interfaces 626 are bond pads. In some embodiments, second die 120 is received with second-die interconnect interfaces 626. In other embodiments, second-die interconnect interfaces 626 are formed on second die 120, e.g., over metallization structures, such as via connections.
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In some embodiments, the second group of metallization layers may be coupled, e.g., hybrid bonded, to the second die before the second die is coupled to the composite device. For example, the second die may be hybrid bonded to the second group of metallization layers in the same manner as the first die may be hybrid bonded to the first group of metallization layers. Inorganic dielectric material could then be formed over the second group of metallization layers (and planarized), and vias could be formed through the inorganic dielectric material as if it were a first level of inorganic dielectric material. The first die (and inorganic dielectric material and vias) over the first group of metallization layers could then be coupled to the second die (and inorganic dielectric material and vias) over the second group of metallization layers. The second group of metallization layers can act as a handle die or carrier for the second die just as the first group of metallization layers can act as a handle die or carrier for the first die. In some such embodiments, tall (two-level) vias are formed by coupling two single-level vias.
Upper metallization layers 301 are shown with upper interconnect interfaces 636, which may be used, e.g., to make electrical connections above multichip composite device 100 to, e.g., a power supply or second multichip composite device 100. Such electrical connections may be through structural substrate 155. Upper interconnect interfaces 636 may be similar to device-level interconnect interfaces 108 or base interconnect interfaces 606. Upper interconnect interfaces 636 may be any suitable structures. Upper interconnect interfaces 636 may be bond pads. In some embodiments, upper metallization layers 301 are received with upper interconnect interfaces 636. In other embodiments, upper interconnect interfaces 636 are formed on upper metallization layers 301, e.g., over metallization structures, such as via connections. In other embodiments, connections are made to metallization structures on a top surface of upper metallization layers 301, such as the uppermost of upper metallization layers 301 or the tops of via connections. In yet other embodiments, upper metallization layers 301 connect metallization structures only on its underside, e.g., metallization structures on a top surface of second die 120 (e.g., second-die interconnect interfaces 626) to other such metallization structures (e.g., on a top surface of second die 120 or second-level TDVs 303 or tall TDVs 603).
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Operation 570 may include operation 572. In operation 572, TSV are formed through the structural substrate. The vias may be formed by any suitable means. Voids in the substrate may be formed by, e.g., RIE or DRIE. In some embodiments, wet etches are used. Conventional metallization processes may be used, e.g., damascene and other deposition processes. In some embodiments, no vias are needed for connecting to the composite device on the side of the structural substrate. In some such embodiments, there is no second group of metallization layers. In other embodiments, there is a second group of metallization layers, but with no, e.g., electrical connections needed on the side of the second group of metallization layers. In some embodiments, device-level interconnect interfaces, e.g., bond pads are formed over the vias.
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Notably, heat removal layer 807 is made of a material or materials having a greater thermal conductivity than structural substrate 155 and having a thickness t1 less than a thickness t2 of structural substrate 155. In some embodiments, structural substrate 155 has a thickness t2 in the range of 60 to 120 μm, and a thickness of multichip composite device 100 (including heat removal layer 807, from the bottom of metallization layers 101 to the top of structural substrate 155) is in the range of about 150 to 200 microns. Other structural substrate 155 thicknesses may be used, such as thicknesses t2 in the range of 80 to 100 μm, or a thickness t2 of not less than 50 μm. Notably, depending on the mechanical properties required, structural substrate 155 thickness t2, the modulus of structural substrate 155, and other properties may be adjusted to meet the needs of the application of multichip composite device 100 and microelectronic device assembly 800. Such needs differ depending on the sizes of the dies or the package, and other characteristics of the application.
Heat removal layer 807 is a relatively thin layer coupled to, or formed on, structural substrate 155. A relatively thin layer may be deployed because of the high thermal conductivity of heat removal layer 807. In some embodiments, heat removal layer 807 has a thickness t1 in the range of 0.5 to 20 μm. In some embodiments, heat removal layer 807 has a thickness t1 of not more than 20 μm, not more than 10 μm, or not more than 5 μm. Heat removal layer 807 may include any material or materials having a greater thermal conductivity than that of structural substrate 155. In some embodiments, the material or composite of materials of heat removal layer 807 has a thermal conductivity of not less than twice the thermal conductivity of structural substrate 155. In some embodiments, the material or composite of materials of heat removal layer 807 has a thermal conductivity of not less than five times the thermal conductivity of structural substrate 155. In some embodiments, the material or composite of materials of heat removal layer 807 has a thermal conductivity of not less than seven times the thermal conductivity of structural substrate 155.
As discussed, in some embodiments, structural substrate 155 is crystalline silicon, which has a thermal conductivity of about 140 W/m-K. Heat removal layer 807, due to its high thermal conductivity, spreads heat from first and second dies 110, 120 more effectively than, for example, a silicon die. In some embodiments, heat removal layer 807 is or includes crystalline or polycrystalline diamond. In some embodiments, heat removal layer 807 is or includes crystalline or polycrystalline diamond having a thermal conductivity of not less than 400 W/m-K. In some embodiments, heat removal layer 807 is or includes crystalline or polycrystalline diamond having a thermal conductivity of not less than 1,000 W/m-K. In some embodiments, heat removal layer 807 is or includes copper. In some embodiments, heat removal layer 807 is or includes copper having a thermal conductivity of not less than 300 W/m-K. In some embodiments, heat removal layer 807 is or includes boron and nitrogen (e.g., a compound including boron and nitrogen, boron nitride). In some embodiments, heat removal layer 807 is or includes boron and nitrogen having a thermal conductivity of not less than 250 W/m-K. In some embodiments, heat removal layer 807 is or includes boron and arsenic (e.g., a compound including boron and arsenic, boron arsenide). In some embodiments, heat removal layer 807 is or includes boron and arsenic having a thermal conductivity of not less than 300 W/m-K. In some embodiments, heat removal layer 807 is or includes silicon and carbon (e.g., a compound including silicon and carbon, silicon carbide). In some embodiments, heat removal layer 807 is or includes silicon and carbon having a thermal conductivity of not less than 300 W/m-K. In some embodiments, heat removal layer 807 is or includes aluminum and nitrogen (e.g., a compound including aluminum and nitrogen, aluminum nitride). In some embodiments, heat removal layer 807 is or includes aluminum and nitrogen having a thermal conductivity of not less than 250 W/m-K. In some embodiments, heat removal layer 807 includes a combination of two or more of such materials. Other high thermal conductivity material layers may be used.
Microelectronic device assembly 800 further includes a thermal interface material (TIM) 801 disposed on a top surface of structural substrate 155. TIM 801 may include any suitable thermal interface material and may be characterized as TIM 1. Integrated heat spreader 802 having a surface on TIM 801 extends over multichip composite device 100, and is mounted to substrate 899 or to a motherboard (not shown) on which substrate 899 is mounted. Microelectronic device assembly 800 further includes TIM 803 disposed on a top surface of integrated heat spreader 802. TIM 803 may include any suitable thermal interface material and may be characterized as TIM 2. TIM 801 and TIM 803 may be the same materials or they may be different. Heat sink 804 (e.g., an exemplary heat dissipation device or thermal solution) is on TIM 803 and dissipates heat generated by first and second dies 110, 120. Although illustrated with respect to microelectronic device assembly 800, the heat removal enhancement discussed herein may be deployed in any suitable architecture and form factor. For example, microelectronic device assembly 800 may be used in desktop and server form factors. In other contexts, a heat solution such as a heat pipe or heat spreader may be mounted directly on TIM 801. Such assemblies may be used in smaller form factor devices. Other heat dissipation devices may be used in concert with the heat removal enhancement structures discussed herein.
Also as shown, server machine 906 includes a battery and/or power supply 915 to provide power to devices 950, and to provide, in some embodiments, power delivery functions such as power regulation. Devices 950 may be deployed as part of a package-level integrated system 910. Integrated system 910 is further illustrated in the expanded view 920. In the exemplary embodiment, devices 950 (labeled “Memory/Processor”) includes at least one memory chip (e.g., RAM), and/or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or graphics processor, or the like) having the characteristics discussed herein. In an embodiment, device 950 is a microprocessor including an SRAM cache memory. As shown, device 950 may be a multichip composite system employing one or more IC dies with inorganic dielectric material and split metallization layers, as discussed herein. Device 950 may be further coupled to (e.g., communicatively coupled to) a board, an interposer, or system substrate 199 along with, one or more of a power management IC (PMIC) 930, RF (wireless) IC (RFIC) 925, including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further comprises a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller 935 thereof. In some embodiments, RFIC 925, PMIC 930, controller 935, and device 950 include IC dies having inorganic dielectric material and split metallization layers on system substrate 199 in a multichip composite system.
Computing device 1000 may include a processing device 1001 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” indicates a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory (e.g., SRAM). Processing device 1001 may include a memory 1021, a communication device 1022, a refrigeration device 1023, a battery/power regulation device 1024, logic 1025, interconnects 1026 (i.e., optionally including redistribution layers (RDL) or metal-insulator-metal (MIM) devices), a heat regulation device 1027, and a hardware security device 1028.
Processing device 1001 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
Computing device 1000 may include a memory 1002, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, memory 1002 includes memory that shares a die with processing device 1001. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-M RAM).
Computing device 1000 may include a heat regulation/refrigeration device 1006. Heat regulation/refrigeration device 1006 may maintain processing device 1001 (and/or other components of computing device 1000) at a predetermined low temperature during operation.
In some embodiments, computing device 1000 may include a communication chip 1007 (e.g., one or more communication chips). For example, the communication chip 1007 may be configured for managing wireless communications for the transfer of data to and from computing device 1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
Communication chip 1007 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. Communication chip 1007 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. Communication chip 1007 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 1007 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Communication chip 1007 may operate in accordance with other wireless protocols in other embodiments. Computing device 1000 may include an antenna 1013 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, communication chip 1007 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, communication chip 1007 may include multiple communication chips. For instance, a first communication chip 1007 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1007 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1007 may be dedicated to wireless communications, and a second communication chip 1007 may be dedicated to wired communications.
Computing device 1000 may include battery/power circuitry 1008. Battery/power circuitry 1008 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of computing device 1000 to an energy source separate from computing device 1000 (e.g., AC line power).
Computing device 1000 may include a display device 1003 (or corresponding interface circuitry, as discussed above). Display device 1003 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
Computing device 1000 may include an audio output device 1004 (or corresponding interface circuitry, as discussed above). Audio output device 1004 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
Computing device 1000 may include an audio input device 1010 (or corresponding interface circuitry, as discussed above). Audio input device 1010 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
Computing device 1000 may include a GPS device 1009 (or corresponding interface circuitry, as discussed above). GPS device 1009 may be in communication with a satellite-based system and may receive a location of computing device 1000, as known in the art.
Computing device 1000 may include other output device 1005 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1005 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
Computing device 1000 may include other input device 1011 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1011 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
Computing device 1000 may include a security interface device 1012. Security interface device 1012 may include any device that provides security measures for computing device 1000 such as intrusion detection, biometric validation, security encode or decode, access list management, malware detection, or spyware detection.
Computing device 1000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
The subject matter of the present description is not necessarily limited to specific applications illustrated in
The following examples pertain to further embodiments, and specifics in the examples may be used anywhere in one or more embodiments.
In one or more first embodiments, a multichip composite device includes a plurality of intradevice metallization layers spanning an area of the device, a first die coupled to an uppermost one of the intradevice metallization layers, wherein the first die is fully within the area of the device, an inorganic dielectric material laterally adjacent the first die and over a portion of the intradevice metallization layers, a second die hybrid bonded to the first die, wherein the second die is over a portion of the first die and over a portion of the inorganic dielectric material, and one or more first vias extending through the inorganic dielectric material within the area of the device, and coupling the second die to the intradevice metallization layers.
In one or more second embodiments, further to the first embodiments, individual ones of the intradevice metallization layers have a thickness of at least 1 μm.
In one or more third embodiments, further to the first or second embodiments, the first die includes a plurality of intradie metallization layers, and a thickest one of the intradie metallization layers has a thickness less than that of a thinnest one of the intradevice metallization layers.
In one or more fourth embodiments, further to the first through third embodiments, a structural substrate is over the second die, and the inorganic dielectric material is between the structural substrate and the first die.
In one or more fifth embodiments, further to the first through fourth embodiments, the structural substrate includes a crystalline material of silicon and carbon, aluminum and oxygen, a III-V material, or predominantly silicon.
In one or more sixth embodiments, further to the first through fifth embodiments, the plurality of intradevice metallization layers is a plurality of first intradevice metallization layers, a plurality of second intradevice metallization layers is over the second die, the second die is hybrid bonded to a lowermost one of the second intradevice metallization layers, the second die is fully within an area of the second intradevice metallization layers, and the plurality of second intradevice metallization layers is coupled to the first die by one or more second vias extending through the inorganic dielectric material within the area of the device.
In one or more seventh embodiments, further to the first through sixth embodiments, a plurality of upper interconnect interfaces is over the plurality of second intradevice metallization layers.
In one or more eighth embodiments, further to the first through seventh embodiments, the plurality of intradevice metallization layers includes a plurality of lower interconnect interfaces on a side opposite the first die.
In one or more ninth embodiments, further to the first through eighth embodiments, a third die is coupled to and over the plurality of intradevice metallization layers and laterally adjacent the inorganic dielectric material.
In one or more tenth embodiments, further to the first through ninth embodiments, a fourth die is hybrid bonded to the third die, wherein the fourth die is over a portion of the third die.
In one or more eleventh embodiments, further to the first through tenth embodiments, the second die or the fourth die is hybrid bonded to both the first die and the third die.
In one or more twelfth embodiments, a multichip system includes a plurality of intradevice metallization layers coupled to a substrate, wherein one of the plurality of intradevice metallization layers is coupled to a power supply through the substrate, an inorganic dielectric material over the intradevice metallization layers, a first die adjacent the inorganic dielectric material and coupled to the plurality of intradevice metallization layers, wherein the first die is within an area of the intradevice metallization layers, and a second die hybrid bonded to the first die and coupled to the intradevice metallization layers by one or more first vias extending through the inorganic dielectric material within the area of the intradevice metallization layers.
In one or more thirteenth embodiments, further to the twelfth embodiments, individual ones of the intradevice metallization layers have a thickness of at least 1 μm.
In one or more fourteenth embodiments, further to the twelfth or thirteenth embodiments, the first die includes a plurality of intradie metallization layers, and a thickest one of the intradie metallization layers has a thickness less than a thinnest one of the intradevice metallization layers.
In one or more fifteenth embodiments, further to the twelfth through fourteenth embodiments, a structural substrate is over the second die, wherein the structural substrate spans the area of the intradevice metallization layers, and the inorganic dielectric material is between the structural substrate and the first die.
In one or more sixteenth embodiments, further to the twelfth through fifteenth embodiments, the plurality of intradevice metallization layers is a plurality of first intradevice metallization layers, a plurality of second intradevice metallization layers is hybrid bonded to, and over, the second die, and the second die is fully within an area of the second intradevice metallization layers.
In one or more seventeenth embodiments, further to the twelfth through sixteenth embodiments, a plurality of upper interconnect interfaces and a structural substrate are over the plurality of second intradevice metallization layers, wherein the structural substrate spans the area of the second intradevice metallization layers, and the second intradevice metallization layers are coupled to the upper interconnect interfaces by one or more upper vias extending through the structural substrate.
In one or more eighteenth embodiments, a method includes receiving a plurality of metallization layers, a first die, and a second die, forming a composite device by coupling the first die to the plurality of metallization layers, wherein the first die is within an area of the metallization layers, forming an inorganic dielectric material over the composite device, hybrid bonding the second die to the composite device, and forming a plurality of lower interconnect interfaces on a side of the metallization layers opposite the first die.
In one or more nineteenth embodiments, further to the eighteenth embodiments, the method also includes coupling a structural substrate to the composite device.
In one or more twentieth embodiments, further to the eighteenth or nineteenth embodiments, hybrid bonding the second die to the composite device includes forming one or more first vias through the inorganic dielectric material, and hybrid bonding the second die to the first die and the first vias.
In one or more twenty-first embodiments, further to the eighteenth through twentieth embodiments, the plurality of metallization layers is a plurality of first metallization layers, and the method also includes receiving a plurality of second metallization layers, hybrid bonding the plurality of second metallization layers to the second die, forming the inorganic dielectric material over a portion of the first die and laterally adjacent the second die, and forming one or more second vias through the inorganic dielectric material, and coupling the plurality of second metallization layers to the second vias.
In one or more twenty-second embodiments, further to the eighteenth through twenty-first embodiments, the method also includes attaching a structural substrate over the plurality of second metallization layers, forming upper vias through the structural substrate, and forming a plurality of upper interconnect interfaces on a side of the structural substrate opposite the plurality of second metallization layers, wherein the upper vias couple the upper interconnect interfaces to the plurality of second metallization layers.
The disclosure can be practiced with modification and alteration, and the scope of the appended claims is not limited to the embodiments so described. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limiting in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the patent rights should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
