Patent Application
20090046441
The present invention relates to a wiring board for mounting semiconductor device, a manufacturing method of the same, and a wiring board assembly using the wiring board, and in particular, relates to a wiring board for mounting semiconductor device, which can provide a high performance and high reliability wiring board assembly and module, and a manufacturing method of the same, and a wiring board assembly using the wiring board.
Recently, as semiconductor devices get higher integrated, higher performance, and larger number of functions, the number of the terminals increases and the pitch between the terminals becomes narrower. As for a wiring board for mounting such semiconductor devices, it is required to mount semiconductor devices at a higher density and higher accuracy, and to be more excellent in reliability than before. Examples of the wiring board for mounting semiconductor devices often used currently include a build-up board which is prepared by forming wiring layers of high density on a printed board as core by using a sequential stacking method and a simultaneously-stacked multilayer wiring board which is formed by simultaneously stacking wiring layers and resin sheets in which vias are formed. Japanese Laid Open Patent Application (JP-P2001-284783A) discloses an example of the build-up board. Japanese Laid Open Patent Application (JP-P2003-347738A) discloses an example of the simultaneously-stacked multilayer wiring board.
On the other hand,
Such a simultaneously-stacked multilayer wiring board has a problem that the attenuation of fine pitch is difficult since every via portion depends on filled paste by printing. Moreover, in order to provide a thinner board, the resin sheet is required to be thin. In this case, there is a problem that the entire board 114 has undulating shape depending on the arrangement of the vias after the press in the simultaneous stacking.
These conventional build-up board and simultaneously-stacked multilayer wiring board have structures in which a conductor wiring layer is formed on a dielectric film and an electrode pad for mounting a semiconductor device is formed on the dielectric film. Recently, as wiring of such wiring board becomes denser and finer, the forming method of the conductor wiring layers 102, 106 and 112 is changing from a subtractive method in which copper foil is etched to an additive method in which an electrode is provided to pattern a resist and an electrolytic plated layer is deposited and stacked.
However, electrode pads formed by the additive method have defects that their heights greatly vary each other and the top surfaces of the electrode pads are not flat-shaped but convex-shaped. Therefore, it is difficult to mount a semiconductor device having large number of pins with narrower pitch on the electrode pads. In addition, the solder resist layer 107 is often formed on the electrode pads. The great variation in the heights of the electrode pads makes it extremely difficult to achieve precisely the desired thickness of the solder resist layer and the desired diameter of the opening in the solder resist layer. Further more, as the electrode pads become finer, the adhesion area between the electrode pad and the dielectric film is reduced. Therefore, the adhesion force between the electrode pad and the dielectric film is reduced and the problem is caused that the electrode pad is stripped off the dielectric film especially in the semiconductor device mounting process at high temperature in which lead-free solder is used.
In order to solve the various problems mentioned above, the applicant(s) has(have) proposed a method in which a wiring structure is formed on a supporting body composed of a flat metal plate, electrode pads are formed on the supporting body, and a semiconductor device is mounted on the electrode pads. This method is disclosed in Japanese Laid Open Patent Application (JP-P2002-83893A).
However, following the recent remarkable progress in the performance and increase in the number of functions of mobile devices and the like, there is an increasing demand for mounting semiconductor devices on both the front and back surfaces of a wiring board in order to mount the semiconductor devices at a high density. In the case of the conventional wiring board disclosed in Japanese Laid Open Patent Application (JP-P2002-83893A) mentioned above, it is possible to mount semiconductor devices on a single side but it is difficult to mount semiconductor devices on both sides at a high density.
In addition, it is desirable that interlayer dielectric films of a wiring board for mounting semiconductor devices includes an interlayer dielectric film having a low thermal expansion coefficient or low elastic modulus in order to achieving the high reliability of a wiring board assembly. However, when a dielectric film with a different physical property value is applied in the case of the above-mentioned conventional wiring board, there is a problem that deterioration in reliability is caused due to the structure.
Consequently, various methods are disclosed about a wiring board which is formed by stacking dielectrics each having a wiring layer at the surface.
Japanese Laid Open Patent Application (JP-A-Heisei 10-084186) discloses a method to obtain a wiring board, in which wiring layers are formed on both the surfaces of an adhesive dielectric with holes provided at the positions corresponding to a wiring pattern of a wiring layer and buried with conductors and via connections are formed at the same time by transferring a conductive wiring pattern formed on the surface of a releasable supporting plate to each of both the surfaces of the adhesive dielectric by pressing, and then the releasable supporting plate is removed. In this method, stacking is performed by arranging a wiring board between two both side wiring boards each having printed wirings connected by via, by putting a removable supporting plate with a conductive wiring pattern formed on the surface on each of the two both side wiring boards and by applying heat and pressure to the removable supporting boards for a determined time at predetermined temperature and pressure with a vacuum pressing machine.
Japanese Laid Open Patent Application (JP-P2003-60348A) discloses a method to form a printed board, in which a plurality of resin films formed of the same thermoplastic resin and including a resin film with a wiring pattern formed on only the single side are staked and then pressurized and heated to be stuck to each other. In the method, a conductor pattern is formed on only the single side of a resin film. Then, a single-side conductor pattern film with a via hole filled with conductive paste and another single-side conductor pattern film formed by the same method with a conductor pattern including only electrode portions are stacked, and applied with pressure and heat. Thus, a printed board with only the electrode portions exposed at the surface is formed without forming a solder resist layer.
Japanese Laid Open Patent Application (JP-P2003-188536A) discloses a method in which, a laminate made of ceramic material, having a conductor pattern made of copper or the like on the surface and being provided with via holes filled with epoxy resin, metal paste or the like, and a laminate made of organic material, having a conductor pattern made of copper or the like on the surface and being provided with via holes filled with epoxy resin, metal paste or the like, are stuck together through an interlayer dielectric layer including a photosensitive resin sheet obtained by providing photosensitivity to an insulating sheet material containing mainly thermosetting resin such as epoxy in a partially thermoset state. A dielectric film such as solder resist film is formed on the sticking surface to provide flatness.
Japanese Laid Open Patent Application (JP-P2004-228165A) discloses a structure in which a conductor layer of a single-side wiring circuit-provided resin base material having the conductor layer on the single side of a dielectric base material is electrically connected through a conductor such as conductive paste in inner via hole formed in the single-side wiring circuit-provided resin base material to a conductor layer of a motherboard printed board which is made of a flexible resin such as polyimide and provided with conductor layers on both the front and back surface. This enables that a multilayer portion (partial wiring board) for mounting electric device is provided at the desired position on the surface of the motherboard printed wiring hoard while reducing unnecessary multilayer portions.
Japanese Laid Open Patent Application (JP-A-Heisei 5-335747) discloses a ceramic multilayer board provided with a semiconductor element directly connected to the ceramic multilayer board through solder bumps. Wiring electrodes are not provided to at least vias for flip-chip mounting among the vias in the uppermost and lowermost layers of the ceramic multilayer board and only the vias for flip-chip mounting are formed of Cu material not including Al2O3. Other vias provided in intermediate layers are formed of composite material including 10 wt % to 20 wt % Al2O3 and Cu for the rest. The vias for flip-chip mounting have depressions since Cu contracts greater than glass ceramic as the base material. These vias themselves are takeout electrodes corresponding to the solder bumps. Therefore, the solder bumps are fixed in the depressions and are not likely to be deformed. Consequently, reflow of the solder bumps is improved.
Japanese Laid Open Patent Application (JP-P2005-123332A) discloses a circuit board having a multilayer board and an electronic part. As for the multilayer board, a plurality of conductor patterns are arranged in the form of multiple layers in an insulating board. The conductor patterns are electrically connected to each other through a plurality of interlayer connecting materials respectively filled in a plurality of via holes. The plurality of conductor patterns include a conductor pattern serving as a land provided on the surface of the multilayer board. The electronic part is electrically connected to the land through joining material. The plurality of interlayer connecting materials are electrically connected to the land. The plurality of via holes are provided such that at least a part thereof is shifted by a given amount from the same position in a stacking direction to a planar direction of the multilayer board. For this reason, the insulating board and the interlayer connecting materials are dispersed to some extent. Therefore, stress (stress caused based on the difference between coefficients of linear thermal expansion of the insulating board and the interlayer connecting materials) acting in the stacking direction on joining portions (joining portion between the land and the joining material and joining portion between the joining material and the electronic part) can be smaller compared with a case in which all the plurality of via holes are formed in succession at the same position in the stacking direction. That is to say, occurrence of stripping at the joining sections can be suppressed and the circuit board can be improved in the reliability of connection.
Japanese Laid Open Patent Application (JP-P2005-39044A) discloses a printed board in which a plurality of conductor patterns are arranged in the form of multiple layers in thermoplastic resin. The conductor patterns are electrically connected to each other through a plurality of interlayer connecting materials respectively filled in a plurality of via holes. The plurality of via holes include a first via hole which penetrates one of the plurality of conductor patterns and a second via hole having an opening portion facing to an opening portion of the penetrated conductor pattern and the surrounding of the opening portion. The interlayer connecting material filled in the second via hole is joined to the interlayer connecting material filled in the first via hole and to the surrounding of the opening portion of the penetrated conductor pattern. In the case of this printed board, since a conductor pattern is provided in the surrounding of the joining portion between the interlayer joining materials in the first and second via holes, the joining between the joining materials is secured even when misalignment occurs between the first via hole and the second via hole. That is to say, this printed board is improved in the reliability of connection.
Japanese Laid Open Patent Application JP-P2004-22670A discloses a manufacturing method of a multilayer ceramic board. This manufacturing method includes a step for manufacturing a first green sheet and a second green sheet different from each other in thermal contraction coefficient, a step for forming a via hole for adjusting the thermal contraction coefficient in the second green sheet, a step for burying material for adjusting the thermal contraction coefficient in the via hole for adjusting the thermal contraction coefficient, and then a step for converting the first green sheet into a first ceramic dielectric layer and converting the second green sheet into a second ceramic dielectric layer by stacking the first green sheet and the second green sheet and baking them. According to this manufacturing method, the difference between thermal contractions of the first green sheet and the second green sheet is reduced by adjusting the thermal contraction of entire the second green sheet based on the thermal contraction of the material for adjusting the thermal contraction coefficient. Consequently, cracks and delamination in the first and second ceramic dielectric layers are prevented and the quality of the multilayer ceramic board is improved.
Japanese Laid Open Patent Application (JP-P2003-318322A) discloses an interposer board for mounting a semiconductor chip on the front surface. The interposer board has a plurality of wiring boards. The plurality of wiring boards are stacked such that stress relaxation layers are positioned between adjacent wiring boards, and adjacent wiring boards are electrically connected to each other to form a circuit. Each of the plurality of wiring boards is a double-sided board or a multilayer board. In at least one of combinations of the adjacent wiring boards, the wiring boards have areas different from each other and one of the wiring boards is positioned on the side closer to the front surface without protruding from the other. According to this interposer board, stress concentration is relaxed when a semiconductor chip is mounted face down on the interposer board.
However, as for the method disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-084186), there is a problem that fine pitch is difficult, since it is necessary to consider the alignment between the positions of the wiring pattern and the holes in which conductors buried. In addition, although it is described that not only conductive paste but also metal bodies such as solder balls and gold balls can be used as the conductors forming vias, it is actually difficult to fill the metal bodies into the fine-pitch and small via holes only by using a printing method. Moreover, when metal balls with a diameter of 100 μm or below are arrayed, there is a problem that short circuits between vias are likely to be caused since the metal balls pull each other due to electrostatic force. There is also a problem that an open fault due to the removal of the metal balls is likely to be caused.
According to Japanese Laid Open Patent Application (JP-P2003-60348A), resin layers with conductor patterns formed on the respective single sides are stacked to form a printed board and vias are filled only with conductive paste. For this reason, there is a problem that via formation has to depend on a printing method and formation of fine-pitch wirings is difficult. Moreover, since entire the resin layers are formed of the same material, there is also a problem that destruction of a flip-chip bump, destruction of resin inside the board and the like may be caused due to the difference in thermal expansion coefficient between silicon and adhering resin in the case of flip-chip connection of an LSI chip and the like to the board.
According to the method disclosed in Japanese Laid Open Patent Application (JP-P2003-188536A), a large number of processes such as supply of a dielectric layer and flattening are necessary since the structure requires that the dielectric layer be provided in a place without a conductor pattern in a sticking surface for stacking and the whole surface be flattened, leading to increase in costs as a result. There is also a problem that since this dielectric layer is arranged between an adhesion layer and a stacked plate, a larger number of interface between different materials present than usual and reliability at the adhesion surface is deteriorated. In addition, resin with an excellent mechanical property cannot be used when photosensitive resin is used. When an organic board and an inorganic board are stuck together, there is a problem that the difference in thermal expansion coefficient is large and reliability cannot be obtained. There is also a problem that fine pitch is difficult only by stacking double-sided wiring boards.
In the method disclosed in Japanese Laid Open Patent Application (JP-P2004-228165A), there is a problem that since a mounting section for electronic parts and a motherboard printed board are formed of the same resin, reliability can be deteriorated depending on the parts to be mounted. There is also a problem that material cost is high because all dielectric layers are formed of thermoplastic polyimide. Moreover, there is a problem that an electricity cost for heating is high because high temperature is required in sticking. In addition, since all vias are filled with conductive paste and a hole for the escape of air is provided in a conductive layer, there are problems that a process for providing this hole is necessary and a defect such as crack from the hole is likely to be caused. In addition, since a supporting plate is not used for the connection when boards with different external shapes are stuck, high pressure is required to stick the thin boards with different external shapes together in an island form and there is also a problem that a circuit board may have low reliability due to damage to insulating layers and conductive layers.
The present invention was achieved in view of the above problems. An object of the present invention is to provide a wiring board for mounting semiconductor device, which is effective for an increase in terminals and finer pitch of terminal intervals due to an improvement in integration, performance or multi-function of semiconductor devices, can mount semiconductor devices especially on both sides of the board at a high density and high accuracy, and is excellent in reliability; a manufacturing method of the same; and a wiring board assembly.
A wiring board for mounting semiconductor device according to the present invention includes a dielectric film, wirings formed in the dielectric film, a plurality of electrode pads provided at front and back surfaces of the dielectric film with their surfaces being exposed and with at least portions of lateral sides of them being buried into the dielectric film, and vias connecting the wirings and the electrode pads. At least one via connecting each other the wirings formed in the dielectric film includes second material different from first material forming the vias connecting the wiring and the electrode pads. Since the electrode pads at both front and back sides of the wiring board are buried in the dielectric film, variation in the heights of the electrode pads can be suppressed at both the front and back sides and semiconductor devices can be mounted on both sides of the wiring board at a high density and high accuracy. In addition, since the lateral sides of the electrode pads are buried in the dielectric film, a wiring board for mounting semiconductor device can be obtained which has improved adhesion between the electrode pads and the dielectric film and is excellent in reliability for connection to semiconductor devices.
It is preferable that the dielectric film includes a first dielectric layer positioned at a front surface of the wiring board, a second dielectric layer positioned at a back surface of the wiring board and one or a plurality of third dielectric layers positioned inside the wiring board. In this case, a plurality of wirings buried in both surfaces of the third dielectric layers and vias connecting the plurality of wirings are provided to the third dielectric layers. The electrode pads are provided with surfaces thereof being exposed at a surface of the first dielectric layer at a front surface side of the wiring board and at a surface of the second dielectric layer at a back surface side of the wiring board, and at least the portions of the lateral sides of the electrode pads are buried in the first dielectric layer or the second dielectric layer. At least one via connecting the plurality of wirings buried at the both surfaces of the third dielectric layers includes second material different from first material forming vias formed in the first dielectric layer and the second dielectric layer.
The wiring board for mounting semiconductor device has a structure in which the vias are provided and the wirings are buried at the front and back surfaces of the third dielectric layer positioned inside the wiring board for mounting semiconductor device, the first dielectric layer is formed at the front side of the third dielectric layer and the second dielectric layer is formed at the back side of the third dielectric layer. Therefore, it is possible to prevent a problem of stripping at each interlayer interface of the dielectric film and further improve reliability of the wiring board for mounting semiconductor device, even when a heat load and a bias due to the operation of a semiconductor device is repeatedly applied. This solves a problem that because a conventional wiring board has a structure in which wirings are provided to the front and back surfaces of a dielectric film positioned inside, stripping at the interface of the dielectric film develops especially in the case of a highly-multilayered structure when stress to strip the interface of the dielectric film is generated due to a heat load caused by the operation of a semiconductor device.
As mentioned above, the wiring board for mounting semiconductor device according to the present invention has an advantage that since each interlayer interface of the dielectric film will not be stripped due to the structure, dielectric films with different physical properties can be combined and the wiring board for mounting semiconductor device can be optimized in accordance with a use. In particular, even when a fourth dielectric layer having a wiring and a via is formed between the first dielectric layer and the third dielectric layer or between the second dielectric layer and the third dielectric layer, reliability in practical use can be secured because stripping at the Interlayer interface between the third dielectric layer and the fourth dielectric layer is prevented due to the structure.
In addition, it is preferable that the vias connecting the plurality of wirings buried in the both surfaces of the third dielectric layers includes a via which connects wirings most remote from the first dielectric layer and the second dielectric layer and includes second material different from first material forming the rest vias.
For example, the second material may be conductive paste or solder paste, and also may be conductive paste or solder paste including two or more kinds of powder particles.
In addition, it is preferable that the second material should include at least one kind of powder particles of tin, bismuth, indium, copper, silver, zinc, gold, nickel, antimony, copper coated with silver, zinc coated with silver, organic filler coated with silver, and organic filler coated with tin in conductive paste or solder paste. Although there is disadvantage in some cases in terms of heat resistance when the solder paste is formed of metal with a low melting point, mixing these powder particles into the paste can improve the reliability of the via for connection.
In addition, the second material can includes at least one kind of powder particles including as a parent phase at least one kind of alloy selected from a group of tin-bismuth binary alloy, tin-indium binary alloy, tin-zinc binary alloy, tin-silver binary alloy, tin-copper binary alloy, tin-gold binary alloy, tin-antimony binary alloy, and tin-nickel binary alloy in conductive paste or solder paste. An optimum alloy can be selected depending on a press temperature below heat resistant temperature of resin forming the wiring board.
It is preferable that the inside portion of the via formed of the second material should include a portion of a shape of a bulk and the bulk includes at least one kind of element selected from a group of tin, bismuth, indium, copper, silver, zinc, gold and nickel.
Furthermore, it is preferable that the powder particles form a metal joining layer in the via formed of the second material.
Additionally, the first material can includes at least one kind of metal selected from a group of copper, nickel and gold.
Among the first dielectric layer, the second dielectric layer and the third dielectric layer, at least the first dielectric layer and the second dielectric layer may be formed of different materials. Concerning to specific effects of combining different dielectric layers, in the case that at least one of the first dielectric layer and the second dielectric layer is formed of material having film strength higher than the third and fourth dielectric layers, it is possible to prevent the occurrence of crack from the surface of the wiring board due to the difference in thermal expansion coefficient during mounting a semiconductor device. Additionally, when at least one of the first dielectric layer and the second dielectric layer is formed of material having a thermal expansion coefficient lower than those of the third and fourth dielectric layers, or when at least one of the first dielectric layer and the second dielectric layer is formed of material having an elastic modulus lower than those of the third and fourth dielectric layers, it is possible to reduce stress to the mounted semiconductor device and a motherboard mounting the wiring board for mounting semiconductor device according to the present invention, and improve reliability of entire module equipment.
Furthermore, it is possible to apply different materials to the first dielectric layer and the second dielectric layer, and easily combine the best dielectric layers in terms of reliability according to a use. For example, material with film strength higher than those of the third and fourth dielectric layers is applied to the first dielectric layer in order to prevent the occurrence of crack from the surface of the wiring board due to difference in thermal expansion coefficient during mounting a semiconductor device, and material with an elastic modulus lower than those of the third and fourth dielectric layers is applied to the second dielectric layer in order to reduce stress to the motherboard.
In addition, it is also possible to provide at least one layer of a fourth dielectric layer including a wiring and a via at least one of positions between the first dielectric layer and the third dielectric layer and between the second dielectric layer and the third dielectric layer.
Additionally, an external shape of at least one dielectric layer of a dielectric layer at an upper side of the third dielectric layer and a dielectric layer at a lower side of the third dielectric layer is different from an external shape of the third dielectric layer.
The external shape of one dielectric layer of the dielectric layer at the upper side of the third dielectric layer and the dielectric layer at the lower side of the third dielectric layer may be the same as the external shape of the third dielectric layer, and the external shape of the other dielectric layer of the dielectric layer at the upper side of the third dielectric layer and the dielectric layer at the lower side of the third dielectric layer may be smaller than the external shape of the third dielectric layer. Consequently, a reduction in the volume of the board is possible even when a place necessary to be multilayered and a place unnecessary to be multilayered are present.
It is also possible to further provide, on a surface of the third dielectric layer, which comes into contact with the other dielectric layer, at least one layer of the other dielectric layer.
It is preferable that at least one dielectric layer of the first, second, and fourth dielectric layers include a wiring layer of inorganic material and the third dielectric layer be formed of organic material.
The third dielectric layer may include epoxy resin.
The third dielectric layer may include polyimide resin.
The third dielectric layer may include acrylic resin.
The third dielectric layer may include glass cloth.
The third dielectric layer may include silica filler.
The third dielectric layer may include aramid nonwoven fabric.
The third dielectric layer may include thermosetting resin.
The third dielectric layer may include thermoplastic resin.
The third dielectric layer may include photosensitive resin. The third dielectric layer in which the via filled with conductive paste or solder paste also serves as an adhesion layer in the pressing. For this reason, when considering the reliability after cure, material of the third dielectric layer can be selected from epoxy resin, polyimide resin, acrylic resin, acrylic resin, resin including glass cloth, resin including silica filler, and resin including aramid nonwoven fabric, depending on press temperature. In view of properties too, it is possible to select any of thermosetting resin and thermoplastic resin depending on the process. Furthermore, photosensitive resin can be used when the via hole is required to be formed by a method which is independent on laser or a drill.
An exposed surface of at least one of the plurality of electrode pads may be arranged at the same level of the front surface or the back surface of the dielectric film. According to this structure, when semiconductor devices are electrically connected through gold bumps or the like, a wiring board assembly is provided in which the connections of finer pitch and higher accuracy are achieved.
In addition, an exposed surface of at least one of the plurality of electrode pads may be depressed from the front surface or the back surface of the dielectric film. According to this structure, when semiconductor devices are mounted by using wire bonding or solder, a wiring board assembly is provided in which connections of finer pitch and higher accuracy are achieved.
Additionally, an exposed surface of at least one of the plurality of electrode pads may protrude from the front surface or the back surface of the dielectric film. According to this structure, breaking cracks of solder balls can be prevented and a wiring board assembly with further excellent reliability can be provided when the solder balls are mounted on the protruding surface and a motherboard mounts the board.
A surface of at least one of said plurality of electrode pads may be partially covered by the dielectric film. In the wiring board for mounting semiconductor device having the structure, since almost all portions of the pad is buried in resin, crack is not likely to occur from the end of the pad and the board is excellent in reliability. In addition, since the dielectric layer after the formation of an opening serves as a solder resist, the solder resist layer can be formed which is stable due to good adhesion with metal forming the pad and the wiring compared with a method to form a solder resist after the etching of a supporting body. Furthermore, the opening can be formed above the pad with high precision in position since the opening can be formed above the pad after checking the position of the pad.
It is also possible to provide a supporting body on at least a portion of the front surface or the back surface of the dielectric film.
It is also possible to provide a solder resist layer on at least one of the front surface or the back surface of the dielectric film.
A semiconductor device according to the present invention is provided by mounting semiconductor elements on the above-mentioned wiring board for mounting semiconductor device.
A manufacturing method of wiring board for mounting semiconductor device according to the present invention includes a step for forming a first wiring board, a step for forming a second wiring board and a step for sticking a dielectric layer forming an uppermost surface of the first wiring board and a dielectric layer forming an uppermost surface of the second wiring board together face to face after the formation of the first wiring board and the second wiring board. The step for forming the first wiring board includes a first step for forming a conductive layer to be an electrode pad, a second step for forming a dielectric layer on the conductive layer, a third step for forming a via in the dielectric layer, a forth step for forming a wiring layer on the dielectric layer, a fifth step for forming another dielectric layer on the wiring layer, and a sixth step for repeating the third to fifth steps for one or plurality of times as necessary. The step for forming the second wiring board includes a first step for forming a conductive layer to be an electrode pad, a second step for forming a dielectric layer on the conductive layer, a third step for forming a via in the dielectric layer, a forth step for forming a wiring layer on the dielectric layer, a fifth step for forming another dielectric layer on the wiring layer, a sixth step for repeating the third to fifth steps for one or plurality of times as necessary, a seventh step for forming a via in the dielectric layer forming the uppermost surface and burying a conductor therein. The manufacturing method of wiring board for mounting semiconductor device according to the present invention includes a step for burying first material into vias in dielectric layers of the first and second wiring boards and a step for filling second material different from the first material in the step for forming the dielectric layer forming the uppermost surface of the second dielectric layer.
Additionally, a step for forming the first wiring board can includes a seventh step for forming a via in the dielectric layer forming the uppermost surface and burying a conductor therein.
The step for forming the first wiring board and/or the step for forming the second wiring board can include a step for forming the conductive layer to be the electrode pad on a supporting base and a step for removing the supporting base entirely or partially can be performed after the step for sticking.
The step for forming the dielectric layer forming the uppermost layer preferably includes a step for filling conductive paste or solder paste in a via.
The step for forming the dielectric layer forming the uppermost layer may include a step for filling conductive paste or solder paste in a via by using a printing method.
The step for forming the dielectric layer forming the uppermost layer preferably includes a step for forming a via by using laser or a drill in a resin sheet to be a portion of the dielectric layer.
The step for forming the dielectric layer forming the uppermost layer may include a step for forming a via in the dielectric layer by using development by exposure.
Various shapes can be selected for vias included in the wiring board and the wiring board assembly according to the present invention. Examples are a cylindrical shaped via with the front-surface and back-surface sides of the same size, a potbelly shaped via with the front-surface and back-surface sides of the same size and the swelled middle, a hourglass shaped via with the narrowed middle, and a conical shaped via. The cylindrical shaped via has an advantage that the via is easily formed by using a drill or the like. The potbelly shaped via has advantages that electrical resistance is small due to the swelled middle and a wiring density in a wiring portion can be higher compared with the case of cylindrical via because of the smaller size at the ends of the via than at the middle. The hourglass shaped via with the narrowed middle has an advantage that reliability is improved due to the wider areas at the ends of the via, which are connecting portions with wirings. Generally, the connection at the connecting portions is likely to be week. Concerning to a laser via formed by using laser and a photo via formed by using light, the diameter of the via is tend to be large at the side of incidence of laser or light. The shapes of them can be controlled to some extent by selecting material, irradiation conditions of laser and light, exposure condition and the like.
The step for sticking the dielectric layers forming the uppermost surfaces together face to face can include a step for having metal powder particles metal-joined in the conductive paste or solder paste.
When the conductive paste or solder paste includes a metal powder with melting temperature below press temperature, metal joining is possible as a result of melting of the metal powder and elemental diffusion to the adjacent metal powder during the pressing in which load and temperature is applied. When all the metal powders inside the via have melting points below press temperature, a bulk shape is formed in the via. At this time, wettability between the powders differs depend on the activity of binder and flux used in the conductive paste or solder paste In the case of poor wettability, metal joining partly occurs at the interface between the metal particles as a result of elemental diffusion.
A via filled with conductive paste or solder paste and coming into contact with wiring layers of two boards with supporting plates to be stuck together also serves to remove oxide films formed at the surfaces of the wiring layers of the boards. The thickness of the intermetallic compound layer such as Cu—Sn, Sn—An, Au—Zn or Cu—Zn formed between the powder and the electrode is different due to the activity of binder and flux used in the conductive paste or solder paste. Even when the activities of binder and flux are low, an oxide film can be destructed by the pressing forces between the powders and between the powder and the electrode during the pressing. In this way, via connection with high reliability is possible.
When all the metal powders in the conductive paste or solder paste have melting temperatures above press temperature, the metal powders do not melt during the pressing in which load and temperature are applied. However, metal joining is possible at the interface of the metal particle as a result of elemental diffusion between adjacent metal powders. Even when the activities of binder and flux are low, an oxide film can be destructed by the pressing forces between the powders and between the powder and the electrode during the pressing, and thus the elemental diffusion is facilitated. In this way, via connection with high reliability is possible.
Another manufacturing method of wiring board for mounting semiconductor device according to the present invention, includes a step for forming two wiring boards by performing a first step for forming a conductive layer to be an electrode pad, a second step for forming a dielectric layer on the conductive layer, a third step for forming a via in the dielectric layer, a forth step for forming a wiring layer on the dielectric layer and a fifth step for forming a wiring layer as an uppermost layer by repeating the second step to the forth step for one or a plurality of times as necessary; a sixth step for forming a via in another dielectric layer by using laser or a drill; and a seventh step for sticking the wiring layer as the uppermost layer of each of the two wiring boards with the via formed in the other dielectric layer together such that the other dielectric layer is put between the two wiring boards face to face.
The step for forming the two wiring boards can also includes a step for forming the conductive layer to be the electrode pad on a supporting base for at least one of the boards. A step for removing the supporting base entirely or partially can be included after the step for sticking. In this case, the supporting base can be a metal plate. The electrode pads are formed on the first and second supporting bases such as metal plates and the first and second dielectric films are formed on the electrode pads on the first and second supporting bases respectively. After that, the first and second dielectric films are stuck together, and then a dielectric film is formed by removing the first and second supporting plates. In this cases since the electrode pads are formed on the first and second supporting base with excellent flatness, exposed surfaces of the electrode pads are positioned accurately and densification is facilitated.
Additionally, since the two wiring boards formed on the supporting bases are stuck together face to face, the wiring board for mounting semiconductor device can be formed which is more accurate in alignment in the sticking, and more excellent in densification and reliability compared with a conventional simultaneously-stacked multilayer wiring board formed by simultaneously stacking a plurality of resin sheets. There is also an advantage that the number of layers can be increased in a short period of time compared with a conventional build-up board.
When stacking is performed at too high temperature and too high pressure in the sticking the two wiring boards formed on the supporting bases together face to face, there is a problem that reliability is deteriorated as a result of the occurrence of distortion of the wiring boards formed in advance on the supporting bases. In the case of the wiring board for mounting semiconductor device according to the present invention, the flatness is achieved by forming the dielectric layers at the uppermost layers, conductors such as conductive paste or solder paste are buried in the vias formed in the dielectric layers, and thus the vias in which the conductors are buried is stacked to obtain an electrical connection. Since flat surfaces are stuck together, the two wiring boards formed on the supporting bases can be stuck together face to face even at the condition of low temperature and low pressure, and thus the wiring board for mounting semiconductor device can be obtained which is excellent in accuracy and reliability.
It is also possible to manufacture a board with supporting plate and connect it to a conventional inorganic or organic circuit board by pressing. As a result, it is possible to add a circuit necessary due to a circuit design to a commercially-available circuit board.
According to the present invention, since a multilayer circuit board on a supporting plate, which include a via formed by a plating method, dielectric resin and an electrode is used and connection for conductive portions are obtained by filling conductive paste or solder paste in the via portion, a multilayer board is formed which enables the formation of circuit wiring with finer pitch therein, is more excellent in electrical properties at high speed and high frequency, is thinner, and has larger number of layers compared with a simultaneously-stacked board. Additionally, when a circuit board having a number of layers is formed, a tact time is shortened and a yield is improved by manufacturing circuit boards each having the half number of layers at the same time, sticking the circuit boards through a resin dielectric layer and a via filled with conductive paste or solder paste.
Exemplary embodiments of the present invention will be described in detail below with reference to the attached drawings. First, a first exemplary embodiment of the present invention will be described with reference to
The dielectric film 1 is formed by stacking a plurality of dielectric layers (see dielectric layers 67a and 67b in
Materials of the dielectric layers included in the dielectric film 1 are the same. The material of the dielectric film 1 is not limited to a specific material, if the material is excellent in heat resistance in soldering, high chemical resistance and so forth, but preferably is heat-resistant resin, such as epoxy resins polyimide, and liquid crystal polymer, which has high glass transition temperature and is excellent in mechanical properties such as film strength and elongation at break. When considering that costs, working temperature, and reliability are important, it is also possible to use epoxy resin, acrylic resin, polyimide, and so forth. When the thickness of the dielectric film 1 is 0.3 mm or below, it is preferable to use as the material of the dielectric film 1, a material with a high bending modulus such as impregnated glass cloth, impregnated aramid nonwoven fabric and so forth for the purpose of improved handling during mounting the semiconductor device.
Concerning the wiring board for mounting semiconductor device, 5 according to the present invention, since the electrode pads 4 on both the front and back surfaces of the board 5 are buried in the dielectric film 1, variations in the heights of the electrode pads 4 can be reduced at both the front and back surfaces of the board 5 and semiconductor devices can be mounted at high density and high accuracy on the both sides of the wiring board for mounting semiconductor device, 5. Furthermore, since the lateral sides of the electrode pads 4 are buried into the dielectric film 1, adhesion between the electrode pads 4 and the dielectric film 1 is improved and the wiring board for mounting semiconductor device, 5 having high connection reliability with the semiconductor devices can be obtained.
In addition, since the via 3 is formed by using the plating method, a work for arraying metal balls or the like is not required and fine patterns can be formed. Therefore, the vias can be arranged at fine pitch and a circuit board having a high wiring capacity can be formed compared with the cases of the boards disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-084186), Japanese Laid Open Patent Application (JP-P2003-60348A), and Japanese Laid Open Patent Application (JP-P2004-228165A). Additionally, different from the disclosure in Japanese Laid Open Patent Application JP-P2004-228165A, it is not necessary to form a hole for the escape of air in the conductive layer in burying conductive paste or solder paste into the via hole, and thus the number of processes is reduced. Furthermore, since there is no hole for the escape of air, defects such as cracks from the hole are not occurred.
When a semiconductor device is mounted by using gold bumps on the electrode pads 4a with their exposed surfaces at the same level as the front surface or the back surface of the dielectric film 1 as shown in
Next, printed wiring assemblies according to a second exemplary embodiment of the present invention will be described.
The electrode pad 4 provided at a place on which the semiconductor device 11 is mounted is either the electrode pad 4a of
Additionally, it is also possible as necessary, to form a molding 15 to cover the wire 10, the electrode pad 4 and the semiconductor device 11 connected through the wire 10 as shown in
A wiring board assembly 20 shown in
Next, wiring boards for mounting semiconductor device according to a third exemplary embodiment of the present invention will be described.
A conventional wiring board has a structure in which wirings are provided on the front and back surfaces of a dielectric layer arranged inside. Therefore, when the wiring board is formed by stacking dielectric layers formed of different material from the case of the dielectric layer arranged inside, stress to strip the interface of the dielectric layers from each other is caused due to the difference in thermal expansion coefficient and so forth as a result of a heat load caused by the operation of a semiconductor device, and stripping at the interface of dielectric layers may develop from a wiring end at which adhesion is weak due to the structure. On the other hand, the wiring board for mounting semiconductor device, 29 according to the present invention has a structure that the wirings 25 are buried at the front and back surfaces of the third dielectric layer 23 arranged inside. Therefore, even when the first dielectric layer 21 and the second dielectric layer 22 are formed of material different from the case of the third dielectric layer 23 to form the dielectric film 24, stripping at the interface of dielectric layers with a wiring end as the starting point can completely be prevented since stripping stress caused by repeated application of a heat load and bias due to the operation of a semiconductor device are received by the whole surface of the third dielectric layer 23.
Therefore, concerning the wiring board for mounting semiconductor device, 29 according to the present exemplary embodiment, materials of desired physical properties in accordance with purposes are selected for the first dielectric layer 21 at the front surface, the second dielectric layer 22 at the back surface and the third dielectric layer 23 inside. Consequently, it is possible to solve problems that since material of a board is limited to a single kind, which is thermoplastic polyimide, as disclosed in Japanese Laid Open Patent Application (JP-P2004-228165A), reliability may be deteriorated depending on parts to be mounted, that the material cost is high, and that the electricity cost for heating is high because high temperature is required for sticking.
The wiring board for mounting semiconductor device, 29 according to the present exemplary embodiment can have a multilayer wiring structure as shown in
Furthermore, the wiring board assembly 14 and 20 can be formed in the same way as in the case of the above-mentioned wiring board for mounting semiconductor device, 5 even by using the wiring board for mounting semiconductor device, 29 according to the present exemplary embodiment. When semiconductor devices are mounted on both sides of the wiring board for mounting semiconductor device, 29, for example, a rigid material with high elastic modulus is selected for the third dielectric layer 23 for the purpose of improving handling, and the same material but with higher film strength or lower thermal expansion coefficient than the case of the third dielectric layer 23 is applied to the first dielectric layer 21 and the second dielectric layer 22. Thus, it is prevented that cracks occur from the surface of the wiring board for mounting semiconductor device, 29 due to difference in thermal expansion coefficients during mounting semiconductor devices When a semiconductor device is mounted on the side of the first dielectric layer 21 of the wiring board for mounting semiconductor device, 29, not only a semiconductor device but also a solder ball are provided on the side of the second dielectric layer 22 of the wiring board for mounting semiconductor device, 29 and the wiring board for mounting semiconductor device, 29 is mounted on a motherboard; different materials are applied to all the dielectric layers, and thus the wiring board for mounting semiconductor device, 29 is formed with optimized reliability. For example, a rigid material with high elastic modulus is selected for the third dielectric layer 23 for the purpose of improving handling, a material with higher film strength or lower thermal expansion coefficient than the case of the third dielectric layer 23 is applied to the first dielectric layer 21 and a material with lower elastic modulus than the case of the third dielectric layer 23 is applied to the second dielectric layer 22.
Next, a fourth exemplary embodiment of the present invention will be described.
The wiring board for mounting semiconductor device, 52 according to the present invention has a structure in which the wirings 48 are buried at the front and back surfaces of the third dielectric layer 43 positioned inside and the wiring 44 is buried into the fourth dielectric layer 46. For this reason, even when the dielectric film 47 is formed by applying different materials to all the dielectric layers, stripping at the interface of the dielectric layers with a wiring end as the starting point can completely be prevented since stripping stress caused by repeated application of a heat load and bias due to the operation of a semiconductor device are received by the whole surfaces of the third dielectric layer 43 and the forth dielectric layer 46.
It is possible to form the wiring board assembly 14 and the wiring board assembly 20 by using the wiring board for mounting semiconductor device, 52 according to the present exemplary embodiment in the same way as the above-mentioned wiring board for mounting semiconductor device, 5 and the wiring board for mounting semiconductor device, 29. Here, when semiconductor devices are mounted on both sides of the wiring board for mounting semiconductor device, 52, it is preferable to select a material with high elastic modulus for the third dielectric layer 43 for the purpose of improving handling, apply, for example, a material with lower elastic modulus to the forth dielectric layer 46 for the purpose of stress relaxation and apply a material with higher film strength or lower thermal expansion coefficient than the cases of the third dielectric layer 43 and the forth dielectric layer 46 to the first dielectric layer 41 and the second dielectric layer 42. As a result, it is possible to prevent occurrence of cracks from the surface of the wiring board for mounting semiconductor device, 52 due to difference in thermal expansion coefficient during mounting a semiconductor device and form the wiring board for mounting semiconductor device, 52 having a stress relaxation function. For this reason, it is possible to form a circuit board with high reliability as a wiring board assembly, compared with the board obtained by the method disclosed in Japanese Laid Open Patent Application (JP-P2003-60348A).
Additionally, when a semiconductor device is mounted on the side of the first dielectric layer 41 of the wiring board for mounting semiconductor device, 52, not only a semiconductor device but also a solder ball are provided on the side of the second dielectric layer 42 of the wiring board for mounting semiconductor device, 52 and the wiring board for mounting semiconductor device, 52 is mounted on a motherboard; different materials are applied to all the dielectric layers and the wiring board for mounting semiconductor device, 52 is formed with optimized reliability. For example, a rigid material with high elastic modulus is selected for the third dielectric layer 23 for the purpose of improving handling, a material with lower thermal expansion coefficient is applied to the forth dielectric layer 42, a material with higher film strength than the cases of the third dielectric layer 43 and the forth dielectric layer 46 is applied to the first dielectric layer 41 and a material with lower elastic modulus than the cases of the third dielectric layer 43 and the forth dielectric layer 46 is applied to the second dielectric layer 43.
Next, a fifth exemplary embodiment of the present invention will be described.
Additionally, when the shape of via is a circular truncated cone, the above-mentioned via size denotes the diameter at the upper portion or the lower portion of the via. The shape of via is not a circular shape in some case, and in this case, an appropriate value such as perimeter can be defined as the size.
Next, a sixth exemplary embodiment of the present invention will be described.
Additionally, the relationship between the size of the front surface side of the via and the size of the back surface side thereof may be the opposite relationship shown in
Because the via is different in sizes at the front surface side and at the back surface side as mentioned above, wiring densities at both sides of the via can be different each other. At this time, it is desirable that the size at the side in which high wiring density is required be smaller. In the case of a laser via formed by using laser and a photo via formed by using light, a via diameter at the side of incidence of laser and light tends to be larger in general. Therefore, the relationships between the size of the front surface side and the size of the back surface side can be controlled to be the opposite relationships by making an incident direction of laser beam or light for the formation in the first dielectric layer 96 opposite to an incident direction of laser beam or light for the formation in the second dielectric layer 97.
Furthermore, it is desirable that via sizes at the front surface side and the back surface side for mounting semiconductor elements be small, since as for high-performance semiconductor elements, intervals between pads as connecting portions to a wiring board are extremely narrow and expected to be further narrower in future. The wiring board for mounting semiconductor device according to the present invention can mount semiconductor elements on both sides, and thus it is especially desirable that the front-surface-side size of the via formed in the first dielectric layer 96 should be smaller than the back-surface-side size and the back-surface-side size of the via formed in the second dielectric layer 97 should be smaller than the front-surface-side size.
Next, a manufacturing method of a wiring board for mounting semiconductor device according to the present invention will be described.
Next, as shown in
Next, as shown in
Next, as shown in
Alternatively, as shown in
According to the present invention, fine pitch between vias can be maintained by forming the via 68b using a plating method. Furthermore, by filling the vias 68c to contact each other, namely the vias to be stuck together, with adhesive material, e.g. conductive paste or solder paste, adhesion between the vias can be improved. According to the present invention therefore, it is possible to provide a high-density and highly-reliable wiring board. In particular, when using conductive paste or solder paste containing metal powder particles, metal joining between the powder particles is formed, and thus the vias adhere together strongly.
Alternatively, as shown in
Alternatively, as shown in
Although there is no specific limitation on the material of the supporting base 61, a material superior in workability is preferable when considering that the supporting base 61 is removed finally. As a specific example for the supporting base 61, metal such as copper, copper alloy, stainless steel or aluminum, or material such as glass or silicon is preferable.
For instance, when the supporting base is a metal supporting base including a thin-film metal layer and a supporting metal layer thicker than the thin-film metal layer, only the thicker supporting metal layer can be stripped while leaving only the thin-film metal layer on the board when removing the supporting base. As a result, the metal layer required to be removed later by etching or the like, is very thin.
It is also possible when forming an opening to the dielectric layer with laser or the like, to form the opening with laser in the state of the above-mentioned thin-film metal layer being left and perform desmear process or the like thereafter. In this method, since the other portions other than the via opening are covered with the thin-film metal layer during the desmear process, there is no damage to resin due to desmear solution or the like and the contamination of the desmear solution can be reduced.
It is preferable that the conductor materials formed of conductive paste or solder paste provided in the vias 68c certainly fuse to be connected by heating and pressing when the wiring boards with supporting base, 73 are stuck together. More in detail, conductive paste in which metal particles are dispersed in resin, solder or the like is preferable. Additionally, the dielectric layers 67a and 67b are required to be heat resistant and chemical resistant in the manufacturing process. When there is no problem in this respect, any material can be selected for the dielectric layers 67a and 67b.
In the manufacturing method of the wiring board for mounting semiconductor device according to the first exemplary embodiment of the present invention mentioned above, as shown in
Furthermore, since both surfaces to be stuck together face to face are flattened by forming the dielectric layer 67b on the wiring 69a, the dielectric layer 67b is not required to be deformed by heating and pressing for the sticking, an uniform load distribution is possible in the pressing regardless of the arrangement of the vias, and both the surfaces can be stuck together at extremely low temperature and week pressing force. For this reason, no distortion occurs in the whole wiring board with supporting base, 73 when sticking. Therefore, it is possible to obtain the highly-reliable wiring board for mounting semiconductor device, 75 with less damage to the wirings and the dielectric layers. Furthermore, it is also possible to form the circuit board with excellent flatness after removing the supporting base such as copper plate after the pressing, since rigid resin including aramid cloth, glass cloth or the like is used as the adhesion layer for the sticking. This makes it possible to cut the process of forming a dielectric layer for the purpose of flatness required in the method disclosed in Japanese Laid Open Patent Application (JP-P2003-188536A), and reduce the interface between different materials, which may cause a failure, since this dielectric layer is not present.
In addition, when the concave portions 63 are formed in advance to the supporting base 61 through etching and the electrode pads 64 are formed by burying the conductive layer into the concave portions 63 as shown in
On the other hand, when the barrier layer 65 is provided in advance on the supporting base 61 and the conductive layer is stacked on the barrier layer 65 to form the electrode pad 66 as shown in
Next, another manufacturing method of the wiring board for mounting semiconductor device according to the present invention will be described.
Next, a dielectric layer 83 is formed on the supporting base 81 as shown in
Next, a wiring 85 is formed on the dielectric layer 83 as shown in
If necessary, as shown in
Next, as shown in
As a result, a wiring board with supporting base, 90 having the via 84a is obtained.
Next, as shown in
Finally, as shown in
If necessary, as shown in
According to the above-mentioned manufacturing method of the wiring board for mounting semiconductor device according to the first exemplary embodiment of the present invention, since the surface of the wiring board with supporting base, 86 is not flat, accuracy is not so good in the sticking. However, this manufacturing method has advantages that the manufacturing process is shortened and cost down is achieved since it is enough to form the dielectric layer 87 to only one of the wiring boards with supporting base, 90 to be stuck together face to face and the via 84a filled with conductive paste or solder paste in the dielectric layer 87.
However, the property of the dielectric layer 87 is important to stick face to face the wiring board with supporting base, 86 to the wiring board with supporting base, 90 having the via 84a filled with conductive paste or solder paste under the appropriate conditions of low temperature and low pressure. It is preferable that thermosetting resin which is lower than the dielectric layer 83 in curing temperature and easily flows by heating and pressing in the stacking is applied to dielectric layer. More specifically, epoxy resin and modified polyimide are raised as examples and epoxy resin including elastomer components is preferable. By applying these materials to the dielectric layer 87, a low-cost wiring board for mounting semiconductor device, 92 having high reliability is obtained.
Next, still another manufacturing method of the wiring board for mounting semiconductor device according to the present invention will be described.
Since the dielectric layer 93 is firstly formed on the supporting base 61 and the metal layer such as the pad is formed thereafter in the manufacturing method, the dielectric layer 93 on the supporting base 61 serves as a strong etching barrier layer. For this reason, a pad section and a wiring section are less likely to be damaged by etching solution during the etching the copper plate, and a reliable board for a wiring board assembly is obtained. Additionally, the dielectric layer 93 after the formation of the opening serves as a solder resist. The dielectric layer 93 after the formation of the opening is superior in adhesion with metals forming the pad and the wiring compared with a solder resist formed after etching the supporting body, and thus serves as a stable solder resist layer. Furthermore, the opening can be formed above the pad at high accuracy in position since the opening can be formed above the pad after checking the position of the pad.
Next, still another manufacturing method of the wiring board for mounting semiconductor device according to the present invention will be described.
In the following process, the supporting plates 121 formed at both sides are removed by etching or by applying stress, heat, ultraviolet rays or the like, as shown in
In order to form the via hole to the resin sheet 123 as the third dielectric layer, it is possible to use a method using a drill, a formation method using development by exposure, a formation method using laser, and so forth. In the case of the formation using the drill, the third dielectric layer 123 does not cure before the pressing for sticking since heat is not applied to the resin sheet. Therefore, since almost all portions of the resin sheet cure for the first time in the sticking, there is an advantage that stronger adhesion can be achieved. When the via hole is formed using development by exposure, there is an advantage that accuracies in the shape and the position of the via can be improved. When using laser, there is an advantage that formation of a smaller via is possible. When using the drill or laser, photosensitive resin with poor mechanical properties does not need to be used to the substrate to be the adhesion layer, and the material can be selected by attaching importance to mechanical strength. As a result, it is possible to form a board with higher reliability than a board with a via hole which is formed using development by exposure in the manufacturing process.
In
After that, as shown in
In
After that, as shown in
Next, a seventh exemplary embodiment of the present invention will be described.
After that, the supporting plates 121 are removed by etching or by applying stress, heat, ultraviolet rays or the like, as shown in
Next, an eighth exemplary embodiment of the present invention will be described.
After that, as shown in
Next, a ninth exemplary embodiment of the present invention will be described.
As shown in
Since there are two or more places to be stuck in this case, when heights of the boards are different, it is also possible to perform a cure of resin in the process after a temporal connection using a flip-chip mounter or the like is performed for each of the places to be stuck. Furthermore, sticking to conventional build-up board and printed board is possible with uniform heating and uniform load distribution by using the board with the supporting plate 121.
After that, as shown in
Furthermore, it is also possible to form a high-performance board by sticking to a board including the fifth dielectric layer as a substrate of inorganic material when functions such as an inductor L, a capacitor C, and resistor R are added to inside a wiring of the inorganic board. Additionally, due to this structure, an area is provided on the dielectric layer on which the dielectric layer with a smaller external shape is mounted. The area can effectively be utilized by mounting other semiconductor elements or the like on the area in accordance with purposes, and a high-density wiring board suitable for various purposes can be provided. It is also possible to obtain a board with the same shape as a board to which a counter bore is provided after pressing by providing area to one of the boards each with supporting plate to be stuck together.
Next, a tenth exemplary embodiment of the present invention will be described.
After that, as shown in
Here,
Furthermore, required heat resistance cannot be satisfied in some cases when all these solder pastes are metals with low melting points. It is possible to improve the reliability in connection of the via by mixing one or more kinds of powders from the group of tin, bismuth, indium, copper, silver, zinc, gold, nickel, antimony, copper coated with silver and so forth, zinc coated with silver, organic filler coated with silver, and organic filler coated with tin, into the solder paste.
These powder particles in the conductive paste or solder paste are in a state of separation from each other like a powder particle A130 and a powder particle B131 as shown in
Also in this state, structural strength inside the via can be maintained by providing paste binder with strength. When metal powders with melting temperatures below the temperature at the pressing are partially included, as shown in
In addition, metal joining due to elemental diffusion partly occurs at the interface between the metal particles also when the filling ratio of the powder particles inside the via is low or when the force of pressing is weak. When all the metal powders in the paste have melting temperatures above the temperature at the pressing, the metal powders do not melt but the adjacent metal particles can be metal-joined in the interface due to elementary diffusion to be the state of
As described in detail above, the present invention makes it possible to obtain a new wiring board for mounting semiconductor device, which is effective for an increase in terminals and finer pitch of terminal intervals due to an improvement in integration, performance or multi-function of semiconductor devices, can mount semiconductor devices especially on both sides of the board at a high density and high accuracy, and further more, is excellent in reliability as well.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-001921 | Jan 2006 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2006/325348 | 12/20/2006 | WO | 00 | 7/7/2008 |
