Claims
- 1. A semiconductor device comprising:a base substrate comprised of flexible film and having a first surface and a second surface that is opposed to said first surface; a plurality of electric conductor layers formed on said first surface of said base substrate; a semiconductor chip mounted through an adhesive material on said first surface of said base substrate and arranged over said plurality of electric conductor layers, said semiconductor chip having a plurality of semiconductor elements and a plurality of external terminals formed on its main surface; a first insulation layer formed between said electric conductor layers and said semiconductor chip; a plurality of bonding wires to which said external terminals and said electric conductor layers are electrically connected, respectively; a plurality of bump electrodes arranged on said second surface and electrically connected with said electric conductor layers, and a resin member sealing said semiconductor chip, said electric conductor layers and said bonding wires; wherein the semiconductor device further comprises a plurality of electric conductor layers for plating formed at the peripheral area of said semiconductor chip, wherein each of said electric conductor layers for plating extends continuous with one of said electric conductor layers and reaches to a side of said base substrate; and a second insulation layer formed on said first surface of said base substrate and at the outside of resin member, so as to cover said plurality of electric conductor layers for plating; wherein said second insulation layer is separated from said first insulation layer in a plane view; and wherein an insulation layer made of the same material as said first insulation layer is not formed on the second surface of the base substrate.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-204534 |
Jul 1997 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of Ser. No. 09/596,045, filed Jun. 16, 2000; which is a continuation of grandparent Ser. No. 09/126,438, filed Jul. 30, 1998, now U.S. Pat. No. 6,232,650 the entire disclosures of which are hereby incorporated by reference.
US Referenced Citations (10)
Foreign Referenced Citations (2)
Number |
Date |
Country |
0702404 |
Sep 1995 |
EP |
0694965 |
Jan 1996 |
FR |
Non-Patent Literature Citations (1)
Entry |
“Various Types of BGA Packages that Seal 100-MHz LSIs” Nikkei Electronics, Feb. 28, 1994, No. 602, pp. 111-117. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
09/596045 |
Jun 2000 |
US |
Child |
10/059338 |
|
US |
Parent |
09/126438 |
Jul 1998 |
US |
Child |
09/596045 |
|
US |