Patent Application
20120080220
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-223298, filed on Sep. 30, 2010, the entire contents of which are incorporated herein by reference.
The embodiment discussed herein is related to an electronic device in which an electronic component is flip-chip mounted on a circuit board, a circuit board, and a manufacturing method of the electronic device.
As electronic devices become smaller, thinner, and denser, the pitch of electrode pads formed on a circuit board becomes finer. As the pitch becomes finer, the electrode pad itself becomes narrower, and when an electronic component is flip-chip mounted on a circuit board, it becomes difficult to reliably mount terminals of the electronic component on the electrode pads on the circuit board. To solve the problem, for example, a technique is known in which an opening (concave portion) is formed in the electrode pad of the circuit board and a terminal of a semiconductor element is introduced into the opening while being slid along the inner edge of the opening.
Japanese Laid-open Patent Publication No. 2008-21751 and Japanese Laid-open Patent Publication No. 2005-353854 are examples of related art.
To form an opening in the electrode pad, it is necessary to form a wall portion that defines the opening in the electrode pad. Therefore, the electrode pad needs to be widened by at least the width of the wall portion. This prevents the pitch of the electrode pads from becoming finer.
According to an aspect of the invention, an electronic device includes a circuit board including a first electrode and a second electrode; and an electronic component including a first terminal and a second terminal, wherein the first electrode includes a first pad portion to which the first terminal is connected and a first protrusion portion disposed in a first direction in parallel with a straight line passing through the first electrode and the second electrode with respect to the first pad portion and being into contact with the first terminal, the second electrode includes a second pad portion to which the second terminal is connected and a second protrusion portion disposed in a second direction opposite to the first direction with respect to the second pad portion and being into contact with the second terminal, a central axis of the first terminal is disposed on a side of the first pad portion with respect to the first protrusion portion, and a central axis of the second terminal is disposed on a side of the second pad portion with respect to the second protrusion portion.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
Hereinafter, a first embodiment will be described with reference to
Configuration of Semiconductor Device
First, a configuration of a semiconductor device will be described with reference to
As illustrated in
Configuration of Semiconductor Chip
The semiconductor chip 100 is assumed to be a chip formed by forming a plurality of element areas on a semiconductor wafer and dicing the semiconductor wafer into chips. However, the present embodiment is not limited to a semiconductor chip, but other electronic components may be used.
As illustrated in
The chip main body 110 is formed into a substantially rectangular shape in a plan view, and includes a first chip edge 110a, a second chip edge 110b, a third chip edge 110c, and a fourth chip edge 110d. The first chip edge 110a and the second chip edge 110b are disposed on the sides opposite to each other with respect to the center C1 of the semiconductor chip 100 and extend in parallel with each other. The third chip edge 110c and the fourth chip edge 110d are disposed on the sides opposite to each other with respect to the center C1 of the semiconductor chip 100 and extend in parallel with each other and perpendicular to the first chip edge 110a and the second chip edge 110b.
The lengths of the first to the fourth chip edges 110a to 110d are all set to 4 mm. The thickness of the chip main body 110 is set to about 0.2 mm. However the present embodiment is not limited to the above. For example, the chip main body 110 may have a rectangular solid shape, a triangular shape, a pentagonal shape, other polygonal more than pentagonal shapes, a circular shape, or an elliptical shape in a plan view.
The plurality of bumps 120 are classified into first bumps 120a, second bumps 120b, third bumps 120c, and fourth bumps 120d. The first to the fourth bumps 120a to 120d have the same number of bumps and the same pitch, and are respectively arranged along the first to the fourth chip edges 110a to 110d. The first to the fourth bumps 120a to 120d are arranged so that the distance between the first bumps 120a and the second bumps 120b is the same as the distance between the third bumps 120c and the fourth bumps 120d.
The first to the fourth bumps 120a to 120d respectively include first portions 121a to 121d connected to the chip main body 110 and second portions 122a to 122d connected to the first portions 121a to 121d.
The first portions 121a to 121d are formed into a substantially cylindrical shape, and first to fourth maximum diameter portions 123a to 123d are respectively formed at middle positions thereof in the cylindrical axis direction. The second portions 122a to 122d are formed so that the diameter thereof decreases as the distance from the chip main body 110 increases, in other words, formed into a taper shape. The second portions 122a to 122d respectively include first to fourth lost portions 124a to 124d on the outer side of the chip main body 110, in other words, on the sides of the first to the fourth chip edges 110a to 110d. The first to the fourth lost portions 124a to 124d are formed when the semiconductor chip 100 is mounted on a circuit board 200 described below, and respectively have shapes corresponding to first to fourth top surface electrodes 223a to 223d of a circuit board 200 described below, in other words, shapes corresponding to first to fourth protrusion portions 226a to 226d.
The first portions 121a to 121d and the second portions 122a to 122d are formed of the same material. As a material of the first to the fourth bumps 120a to 120d, for example, a metal such as gold is used. As a manufacturing method of the first to the fourth bumps 120a to 120d, for example, a ball bonding may be used.
In the present embodiment, the numbers of the first to the fourth bumps 120a to 120d are all the same. However the present embodiment is not limited to this. For example, if the number of the first bumps 120a is the same as the number of the second bumps 120b and the number of the third bumps 120c is the same as the number of the fourth bumps 120d, it is not necessary that the numbers of the first to the fourth bumps 120a to 120d are all the same.
In the present embodiment, the first to the fourth bumps 120a to 120d are all arranged at the same pitch. However the present embodiment is not limited to this. For example, if the first bumps 120a and the second bumps 120b are arranged at the same pitch and the third bumps 120c and the fourth bumps 120d are arranged at the same pitch, it is not necessary that the first to the fourth bumps 120a to 120d are all arranged at the same pitch.
Further, in the present embodiment, the first to the fourth bumps 120a to 120d are arranged so that the distance between the first bumps 120a and the second bumps 120b is the same as the distance between the third bumps 120c and the fourth bumps 120d. However the present embodiment is not limited to this. For example, according to the shape and the design of the semiconductor chip 100, the first to the fourth bumps 120a to 120d may be arranged so that the distance between the first bumps 120a and the second bumps 120b is different from the distance between the third bumps 120c and the fourth bumps 120d.
Configuration of Circuit Board
The circuit board 200 is a so-called glass epoxy board. However, the present embodiment is not limited to this, but other printed boards, for example, a glass composite board and a ceramic board may be used.
As illustrated in
The core member 210 is, for example, a glass cloth impregnated with an epoxy resin. The core member 210 is formed into a substantially rectangular shape in a plan view, and includes a first board edge 210a, a second board edge 210b, a third board edge 210c, and a fourth board edge 210d. The first board edge 210a and the second board edge 210b are disposed on the sides opposite to each other with respect to the center C2 of the circuit board 200 and extend in parallel with each other. The third board edge 210c and the fourth board edge 210d are disposed on the sides opposite to each other with respect to the center C2 of the circuit board 200 and extend in parallel with each other and perpendicular to the first board edge 210a and the second board edge 210b.
A plurality of through holes 211 are formed at predetermined positions in the core member 210. The through hole 211 vertically penetrates the core member 210, and a via 212 is buried inside the through hole 211. The via 212 includes a conductive film 213 formed on inner surface of the through hole 211 and an insulating member 214 filled inside the insulating film 213. The conductive film 213 connects the top surface wiring layer 220 and the bottom surface wiring layer 230 with each other so that the both wiring layers are electrically connected with each other. As a material of the conductive layer 213, for example, Cu may be used. As a material of the insulating member 214, for example, a polyimide system resin or an epoxy system resin may be used.
The top surface wiring layer 220 is formed on the top surface of the core member 210, that is, a surface facing the semiconductor chip 100, and includes a top surface wiring pattern 221, a top surface insulating film 222, and a plurality of top surface electrodes 223 in the order from the core member 210.
The top surface wiring pattern 221 is formed on the top surface of the core member 210. As a material of the top surface wiring pattern 221, for example, a metal such as Cu is used. The manufacturing method of the top surface wiring pattern 221 is not particularly limited. For example, after a metal foil such as a Cu foil is formed on the entire top surface of the core member 210, a resist pattern is formed by a photolithography technique, and the metal foil may be etched by using the resist pattern as a mask.
The top surface insulating film 222 is formed between the top surface wiring pattern 221 and a layer of the top surface electrodes 223. As a material of the top surface insulating film 222, for example, an epoxy system resin or a polyimide system resin may be used. A plurality of vias 224 are buried at predetermined positions in the top surface insulating film 222. The via 224 vertically penetrates the top surface insulating film 222 and electrically connects the top surface wiring pattern 221 with the top surface electrode 223. As a material of the via 224, for example, a metal such as Cu may be used.
The plurality of top surface electrodes 223 are classified into first top surface electrodes 223a, second top surface electrodes 223b, third top surface electrodes 223c, and fourth top surface electrodes 223d. The number and the pitch of the first to the fourth top surface electrodes 223a to 223d are the same as those of the first to the fourth bumps 120a to 120d of the semiconductor chip 100, and are respectively arranged along the first to the fourth board edges 210a to 210d. The first to the fourth top surface electrodes 223a to 223d are arranged so that the distance between the first top surface electrodes 223a and the second top surface electrodes 223b is the same as the distance between the third top surface electrodes 223c and the fourth top surface electrodes 223d.
The first to the fourth top surface electrodes 223a to 223d respectively include first to fourth pad portions 225a to 225d and first to fourth protrusion portions 226a to 226d arranged on the first to the fourth pad portions 225a to 225d. In
The first to the fourth pad portions 225a to 225d are formed into a rectangle shape and respectively arranged to be perpendicular to the first to the fourth board edges 210a to 210d. As a material of the first to the fourth pad portions 225a to 225d, an electrically conductive material, for example, a metal such as Cu may be used.
The first to the fourth protrusion portions 226a to 226d are respectively arranged in a middle position in the longitudinal direction of the first to the fourth pad portions 225a to 225d, and define first to fourth mounting portions 227a to 227d and first to fourth extending portions 228a to 228d on the first to the fourth pad portions 225a to 225d. As a material of the first to the fourth protrusion portions 226a to 226d, an electrically conductive material or an insulating material having rigidity higher than that of the first to the fourth bumps 120a to 120d of the semiconductor chip 100 is used. As the electrically conductive material, for example, a metal such as Cu may be used. As the insulating material, for example, a resin such as an epoxy resin may be used.
The first to the fourth mounting portions 227a to 227d are areas on which the first to the fourth bumps 120a to 120d of the semiconductor chip 100 are mounted, and are arranged on the inner side of the circuit board 200 with respect to the first to the fourth protrusion portions 226a to 226d, respectively. The first to the fourth extending portions 228a to 228d are arranged on the outer side of the circuit board 200 with respect to the first to the fourth protrusion portions 226a to 226d, respectively.
The first to the fourth protrusion portions 226a to 226d respectively include first to fourth restriction surfaces 229a to 229d at portions facing the inner side of the circuit board 200. The first to the fourth restriction surfaces 229a to 229d respectively extend in parallel with the first to the fourth board edges 210a to 210d, and restrict the first to the fourth bumps 120a to 120d of the semiconductor chip 100 from moving in a direction parallel with the mounting surface of the circuit board 200.
The first to the fourth protrusion portions 226a to 226d are arranged so that the distance between the first restriction surfaces 229a and the second restriction surfaces 229b is the same as the distance between the third restriction surfaces 229c and the fourth restriction surfaces 229d.
The first to the fourth bumps 120a to 120d of the semiconductor chip 100 are arranged to be mounted from the inner side to the outer side of the circuit board 200 with respect to the first to the fourth restriction surfaces 229a to 229d respectively, and connected to the first to the fourth mounting portions 227a to 227d and the first to the fourth protrusion portions 226a to 226d.
Therefore, the distance G1 between the first restriction surface 229a and the second restriction surface 229b is greater than the distance G2 between the first bump 120a and the second bump 120b, and smaller than the distance G3 obtained by adding two times the diameter d of the first and the second bumps 120a and 120b (=2d) to the distance G2 between the first bump 120a and the second bump 120b. Similarly, the distance G1 between the third restriction surface 229c and the fourth restriction surface 229d is greater than the distance G2 between the third bump 120c and the fourth bump 120d, and smaller than the distance G3 obtained by adding two times the diameter d of the third and the fourth bumps 120c and 120d (=2d) to the distance G2 between the third bump 120c and the fourth bump 120d.
Further, the first to the fourth bumps 120a to 120d are arranged so that the central axes Oa to Od thereof are located on the inner side of the circuit board 200 with respect to the first to the fourth regulation surfaces 229a to 229d respectively.
Therefore, the distance G1 between the first restriction surface 229a and the second restriction surface 229b is greater than the distance G4 between the central axis Oa of the first bump 120a and the central axis Ob of the second bump 120b. Although not illustrated in the drawings, the distance G1 between the third restriction surface 229c and the fourth restriction surface 229d is greater than the distance G4 between the central axis Oc of the third bump 120c and the central axis Od of the fourth axis 120d.
The bottom surface wiring layer 230 is formed on the bottom surface of the core member 210, that is, a surface on which the solder balls 400 are attached, and includes a bottom surface wiring pattern 231, a bottom surface insulating film 232, and a plurality of bottom surface electrodes 233 in the order from the core member 210.
The bottom surface wiring pattern 231 is formed on the bottom surface of the core member 210. As a material of the bottom surface wiring pattern 231, for example, a metal such as Cu may be used. The manufacturing method of the bottom surface wiring pattern 231 is not particularly limited. For example, after a metal foil such as a Cu foil is formed on the entire bottom surface of the core member 210, a resist pattern is formed by a photolithography technique, and the metal foil may be etched by using the resist pattern as a mask.
The bottom surface insulating film 232 is formed between the bottom surface wiring pattern 231 and a layer of the bottom surface electrodes 233. As a material of the bottom surface insulating film 232, for example, an epoxy system resin or a polyimide system resin may be used. A plurality of vias 234 are buried at predetermined positions in the bottom surface insulating film 232. The via 234 vertically penetrates the bottom surface insulating film 232 and electrically connects the bottom surface wiring pattern 231 with the bottom surface electrode 233. As a material of the via 234, for example, a metal such as Cu may be used.
The plurality of bottom surface electrodes 233 are arranged in a matrix form on the entire bottom surface of the circuit board 200. The solder balls 400 are respectively attached to the bottom surface electrodes 233. The solder balls 400 function as external connection terminals when the semiconductor device is mounted on another mounting board (mother board).
As illustrated in
Manufacturing Method of Semiconductor Device
Next, a manufacturing method of the semiconductor device will be described with reference to
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
When the first to the fourth bumps 120a to 120d come into contact with the first to the fourth top surface electrodes 223a to 223d, the semiconductor chip 100 is started to be pressed onto the circuit board 200. The pressure weight at this time is set to, for example, 2 kgf to 8 kgf even though it depends on the size of the semiconductor chip 100, the size of the first to the fourth bumps 120a to 120d, and the number of the first to the fourth bumps 120a to 120d. In this way, the first to the fourth bumps 120a to 120d are accurately positioned with respect to the first to the fourth top surface electrodes 223a to 223d through a positioning process described below. When the first to the fourth bumps 120a to 120d are accurately positioned, the semiconductor chip 100 is also accurately positioned with respect to the circuit board 200.
Then, the semiconductor chip 100 is further pressed, and the first to the fourth bumps 120a to 120d are respectively connected to the first to the fourth protrusion portions 226a to 226d and the first to the fourth mounting portions 227a to 227d. At this time, the first to the fourth bumps 120a to 120d are deformed according to the shapes of the first to the fourth protrusion portions 226a to 226d and the first to the fourth mounting portions 227a to 227d. Thereby the sharp top end portions of the first to the fourth bumps 120a to 120d are flattened and the first to the fourth lost portions 124a to 124d are formed on the inner side of the semiconductor chip 100.
When the first to the fourth bumps 120a to 120d are respectively connected to the first to the fourth protrusion portions 226a to 226d and the first to the fourth mounting portions 227a to 227d, the semiconductor chip 100 is heated by a heater (not illustrated in the drawings) provided in the pressure head H to solidify the epoxy system resin L in the gap between the semiconductor chip 100 and the circuit board 200. Thereby the epoxy system resin L contracts, and the semiconductor chip 100 and the circuit board 200 are bonded together.
Next, as illustrated in
Positioning Process of Semiconductor Chip
Next, the positioning process of the semiconductor chip 100 will be described with reference to
First, as illustrated in
Next, the pressure head H is lowered and the semiconductor chip 100 is moved closer to the circuit board 200. At this time, if the semiconductor chip 100 is shifted toward the first board edge 210a (toward the left side in
When the first bump 120a comes into contact with the first protrusion portion 226a, the semiconductor chip 100 is started to be pressed onto the circuit board 200. When the semiconductor chip 100 is pressed onto the circuit board 200, a first reaction force Fla in parallel with the mounting surface of the circuit board 200 is applied from the first protrusion portion 226a to the first bump 120a. Thereby the semiconductor chip 100 moves toward the second board edge 210b of the circuit board 200 (toward the right side in
As illustrated in
In this way, when the semiconductor chip 100 is accurately positioned in the X direction of the circuit board 200, as illustrated in
Although here, it is assumed that the semiconductor chip 100 is slightly shifted toward the first board edge 210a (toward the left side in
When the semiconductor chip 100 is accurately positioned in the X direction of the circuit board 200, the semiconductor chip 100 is further pressed onto the circuit board 200. Then, the first and the second bumps 120a and 120b plastically flows into the inside of the first and the second protrusion portions 226a and 226b, and as illustrated in
Although the cooperation between the first and the second bumps 120a and 120b and the first and the second top surface electrodes 223a and 223b has been focused and described, this is the same for the cooperation between the third and the fourth bumps 120c and 120d and the third and the fourth top surface electrodes 223c and 223d.
For example, if the semiconductor chip 100 is shifted toward the third board edge 210c in the Y direction of the circuit board 200, in the process for moving the semiconductor chip 100 toward the circuit board 200, the third bump 120c first comes into contact with the third protrusion portion 226c. When the semiconductor chip 100 is started to be pressed onto the circuit board 200, a third reaction force F1c in parallel with the mounting surface of the circuit board 200 is applied from the third protrusion portion 226c to the third bump 120c. Thereby the semiconductor chip 100 moves toward the fourth board edge 210d of the circuit board 200 along with the first to the fourth bumps 120a to 120d. Then, when the fourth bump 120d comes into contact with the fourth protrusion portion 226d, a fourth reaction force F1d that offsets the third reaction force F1c is applied from the fourth protrusion portion 226d to the fourth bump 120d to stop the movement of the semiconductor chip 100. In this way, the third and the fourth bumps 120c and 120d are accurately positioned in the longitudinal direction of the third and the fourth top surface electrodes 223c and 223d, that is, the Y direction of the circuit board 200. When the third and the fourth bumps 120c to 120d are accurately positioned in the Y direction of the circuit board 200, the semiconductor chip 100 is also accurately positioned in the Y direction of the circuit board 200.
In this way, when the semiconductor chip 100 is accurately positioned in the Y direction of the circuit board 200, as illustrated in
Although here, it is assumed that the semiconductor chip 100 is slightly shifted toward the third board edge 210c in the Y direction of the circuit board 200, if the semiconductor chip 100 is slightly shifted toward the fourth board edge 210d in the Y direction of the circuit board 200, the positioning operation can be performed in the same manner as described above.
When the semiconductor chip 100 is accurately positioned in the Y direction of the circuit board 200, the semiconductor chip 100 is further pressed onto the circuit board 200. Then, the third and the fourth bumps 120c and 120d plastically flows into the inside of the third and the fourth protrusion portions 226d and 226d, and the third and the fourth bumps 120c and 120d are connected to the third and the fourth protrusion portions 226c and 226d and the third and the fourth mounting portions 227c and 227d. At this time, the third and the fourth bumps 120c and 120d are respectively held inside the third and the fourth protrusion portions 226c and 226d. In other words, the third and the fourth reaction forces F1c and F1d are respectively applied to the third and the fourth bumps 120c and 120d. Therefore, while the semiconductor chip 100 is being pressed onto the circuit board 200, the position of the semiconductor chip 100 is not shifted in the Y direction of the circuit board 200. Therefore, in the process for mounting the semiconductor chip 100 on the circuit board 200, the first and the second bumps 120a and 120b do not drop out of the first and the second top surface electrodes 223a and 223b.
Although the positioning in the X direction and the positioning in the Y direction of the semiconductor chip 100 are separately described, the positioning in the X direction and the positioning in the Y direction of the semiconductor chip 100 progress simultaneously.
As described above, in the present embodiment, even when the semiconductor chip 100 is slightly shifted in the X direction or the Y direction of the circuit board 200, in the process for moving the semiconductor chip 100 closer to the circuit board 200, the position of the semiconductor chip 100 is gradually corrected and the semiconductor chip 100 is accurately positioned. Specifically, when the semiconductor chip 100 is moved closer to the circuit board 200, the first to the fourth bumps 120a to 120d automatically approach the correct positions thereof and the semiconductor chip 100 is accurately positioned. Further, the first to the fourth bumps 120a to 120d are held by the first to the fourth restriction surfaces 229a to 229d, so the semiconductor chip 100 does not shift in the process for pressing the semiconductor chip 100 onto the circuit board 200. As a result, the first to the fourth bumps 120a to 120d do not drop out of the first to the fourth top surface electrodes 223a to 223d.
According to the present embodiment, the semiconductor chip 100 can be accurately positioned by only forming the first to the fourth protrusion portions 226a to 226d on the first to the fourth pad portions 225a to 225d. Therefore, the first to the fourth top surface electrodes formed on the circuit board 200 need not be widened. Therefore, it is possible to make the electrode pitch of the semiconductor chip 100 much finer.
Although, in the present embodiment, all the first top surface electrodes 223a include the first protrusion portion 226a, the present embodiment is not limited to this. For example, at least one of the first top surface electrodes 223a only has to include the first protrusion portion 226a. This is the same for the second to the fourth top surface electrodes 223b to 223d.
Hereinafter, a modified example of the first embodiment will be described with reference to
First to fourth top surface electrodes 523a to 523d respectively include first to fourth protrusion portions 526a to 526d. Although the first to the fourth protrusion portions 526a to 526d are arranged on the first to the fourth pad portions 225a to 225d, the first to the fourth protrusion portions 526a to 526d are arranged inner than the first to the fourth protrusion portions 226a to 226d according to the first embodiment on the circuit board 200.
The first to the fourth protrusion portions 526a to 526d respectively define first to fourth mounting portions 527a to 527d and first to fourth extending portions 528a to 528d on the first to the fourth pad portions 225a to 225d. However, the first to the fourth mounting portions 527a to 527d are arranged on the side opposite to the first to the fourth mounting portions 227a to 227d according to the first embodiment, that is, on the outer side of the circuit board 200 with respect to the first to the fourth protrusion portions 526a to 526d. The extending portions 528a to 528d are arranged on the side opposite to the first to the fourth extending portions 228a to 228d according to the first embodiment, that is, on the inner side of the circuit board 200 with respect to the first to the fourth protrusion portions 526a to 526d.
The first to the fourth protrusion portions 526a to 526d respectively include first to fourth restriction surfaces 529a to 529d at portions facing the outside of the circuit board 200. The first to the fourth restriction surfaces 529a to 529d respectively extend in parallel with the first to the fourth board edges 210a to 210d, and restrict the first to the fourth bumps 120a to 120d of the semiconductor chip 100 from moving in a direction parallel with the mounting surface of the circuit board 200. Although the first to the fourth restriction surfaces 529a to 529d are formed on the first to the fourth protrusion portions 526a to 526d, the first to the fourth restriction surfaces 529a to 529d are located on the side opposite to the first to the fourth restriction surfaces 229a to 229d.
The first to the fourth protrusion portions 526a to 526d are arranged so that the distance between the first restriction surfaces 529a and the second restriction surfaces 529b is the same as the distance between the third restriction surfaces 529c and the fourth restriction surfaces 529d.
The first to the fourth bumps 120a to 120d of the semiconductor chip 100 are arranged to be mounted from the outer side to the inner side of the circuit board 200 with respect to the first to the fourth restriction surfaces 529a to 529d respectively, and connected to the first to the fourth mounting portions 527a to 527d and the first to the fourth protrusion portions 526a to 526d.
Therefore, the distance G1 between the first restriction surface 529a and the second restriction surface 529b is greater than the distance G2 between the first bump 120a and the second bump 120b, and smaller than the distance G3 obtained by adding two times the diameter d of the first and the second bumps 120a and 120b (=2d) to the distance G2 between the first bump 120a and the second bump 120b. Similarly, the distance G1 between the third restriction surface 529c and the fourth restriction surface 529d is greater than the distance G2 between the third bump 120c and the fourth bump 120d, and smaller than the distance G3 obtained by adding two times the diameter d of the third and the fourth bumps 120c and 120d (=2d) to the distance G2 between the third bump 120c and the fourth bump 120d.
Further, the first to the fourth bumps 120a to 120d are arranged so that the central axes Oa to Od thereof are located on the outer side of the circuit board 200 with respect to the first to the fourth regulation surfaces 529a to 529d respectively.
Therefore, the distance G1 between the first restriction surface 529a and the second restriction surface 529b is smaller than the distance G4 between the central axis Oa of the first bump 120a and the central axis Ob of the second bump 120b. Similarly, the distance G1 between the third restriction surface 529c and the fourth restriction surface 529d is smaller than the distance G4 between the central axis Oc of the third bump 120c and the central axis Od of the fourth axis 120d.
As described in the modified example, the first to the fourth restriction surfaces 529a to 529d may be respectively formed on the first to the fourth protrusion portions 526a to 526d at the portions facing the outside of the circuit board 200. When employing the modified example, if the semiconductor chip 100 is positioned so that the central axes Oa to Od of the first to the fourth bumps 120a to 120d are located on the outer side of the circuit board 200 with respect to the first to the fourth regulation surfaces 529a to 529d, and the semiconductor chip 100 is pressed onto the circuit board 200, the semiconductor chip 100 can be accurately positioned as described above. However, the first to the fourth regulation surfaces 529a to 529d are arranged to face a direction opposite to a direction faced by the first to the fourth regulation surfaces 229a to 229d according to the first embodiment, so the first to the fourth reaction forces according to the modified example are applied in directions opposite to the directions of the first to the fourth reaction forces according to the first embodiment.
Hereinafter, a second embodiment will be described with reference to
Configuration of Semiconductor Device
First, a configuration of a semiconductor device will be described with reference to
As illustrated in
Configuration of Circuit Board
Although the first to the fourth protrusion portions 626a to 626d are arranged on first to fourth pad portions 625a to 625d, different from the first to the fourth pad portions 225a to 225d according to the first embodiment, the first to the fourth protrusion portions 626a to 626d are arranged along the longitudinal direction of the first to the fourth pad portions 625a to 625d.
The first to the fourth protrusion portions 626a to 626d respectively define first to fourth mounting portions 627a to 627d on the first to the fourth pad portions 625a to 625d. The width of the first to the fourth protrusion portions 626a to 626d, that is, the length in the direction perpendicular to the longitudinal direction is set to substantially a half of the width of the first to the fourth pad portions 625a to 625d, that is, substantially a half of the length in the direction perpendicular to the longitudinal direction.
The positions of the first to the fourth protrusion portions 626a to 626d on the first to the fourth pad portions 625a to 625d are different from each other for each of the first to the fourth pad portions 625a to 625d.
For example, the first protrusion portion 626a is located on the end portion of the first pad portion 625a facing the fourth board edge 210d, and a first restriction surface 629a is formed on a portion of the first protrusion portion 626a facing the third board edge 210c. The second protrusion portion 626b is located on the end portion of the second pad portion 625b facing the third board edge 210c, and a second restriction surface 629b is formed on a portion of the second protrusion portion 626b facing the fourth board edge 210d. The third protrusion portion 626c is located on the end portion of the third pad portion 625c facing the second board edge 210b, and a third restriction surface 629c is formed on a portion of the third protrusion portion 626c facing the first board edge 210a. The fourth protrusion portion 626d is located on the end portion of the fourth pad portion 625d facing the first board edge 210a, and a fourth restriction surface 629d is formed on a portion of the fourth protrusion portion 626d facing the second board edge 210b.
Although the first to the fourth restriction surfaces 629a to 629d face directions different from each other, all of them restrict the first to the fourth bumps 120a to 120d of the semiconductor chip 100 from moving in a direction parallel with the mounting surface of the circuit board 200.
The first and the second top surface electrodes 623a and 623b are arranged so that the first restriction surface 629a is located nearer to the fourth board edge 210d than the second restriction surface 629b. Therefore, the distance between the first top surface electrode 623a according to the present embodiment and the fourth board edge 210d (or the third board edge 210c) of the circuit board 200 is not the same as the distance between the second top surface electrode 623b according to the present embodiment and the fourth board edge 210d (or the third board edge 210c) of the circuit board 200. The third and the fourth top surface electrodes 623c and 623d are arranged so that the third restriction surface 629c is located nearer to the second board edge 210b than the fourth restriction surface 629d. Therefore, the distance between the third top surface electrode 623c and the second board edge 210b (or the first board edge 210a) of the circuit board 200 is not the same as the distance between the fourth top surface electrode 623d and the second board edge 210b (or the first board edge 210a) of the circuit board 200. By arranging the first to the fourth top surface electrodes 623a to 623d as described above, when the semiconductor chip 100 is moved closer to the circuit board 200, the first to the fourth bumps 120a to 120d can come into contact with the first to the fourth restriction surfaces 629a to 629d.
Positioning Process of Semiconductor Chip
Next, the positioning process of the semiconductor chip 100 will be described with reference to
First, the pressure head H that absorbs the semiconductor chip 100 is driven to position the semiconductor chip 100 so that the central axes Oa to Od of the first to the fourth bumps 120a to 120d are respectively located on the first to the fourth mounting portions 627a to 627d as illustrated in
At this time, if the semiconductor chip 100 is shifted toward the fourth board edge 210d (toward the bottom in
When the first bump 120a comes into contact with the first protrusion portion 626a, the pressure head H starts pressing the semiconductor chip 100 onto the circuit board 200. When the semiconductor chip 100 is pressed onto the circuit board 200, a first reaction force F2a in parallel with the mounting surface of the circuit board 200 is applied from the first protrusion portion 626a to the first bump 120a. Thereby the semiconductor chip 100 moves in the direction of arrow B along with the first to the fourth bumps 120a to 120d.
At this time, if the semiconductor chip 100 does not rotate but moves, as illustrated in
When the second bump 120b comes into contact with the second protrusion portion 626b, a second reaction force F2b that offsets the first reaction force F2a is applied from the second protrusion portion 626b to the second bump 120b to stop the movement of the semiconductor chip 100. When the third and the fourth bumps 120c and 120d respectively come into contact with the third and the fourth protrusion portions 626c and 626d, a third and a fourth reaction forces F2c and F2d, which are in parallel with the mounting surface of the circuit board 200 and offset each other, are respectively applied from the third and the fourth protrusion portions 626c and 626d to the third and the fourth bump 120c and 120d. The third and the fourth reaction forces F2c and F2d offset rotation moment due to the first and the second reaction forces F2a and F2b, so the semiconductor chip 100 is not rotated by the first to the fourth reaction forces F2a and F2d. In this way, when the first to the fourth bumps 120a to 120d come into contact with the first to the fourth protrusion portions 626a to 626d, the movement and the rotation of the first to the fourth bumps 120a to 120d are restricted and the semiconductor chip 100 comes to rest. In this way, the first to the fourth bumps 120a to 120d are accurately positioned with respect to the first to the fourth top surface electrodes 623a to 623d. When the first to the fourth bumps 120a to 120d are accurately positioned, the semiconductor chip 100 is also accurately positioned with respect to the circuit board 200.
Although a case in which the semiconductor chip 100 moves without rotating has been described, the semiconductor chip 100 may move while rotating depending on the absorption force and the static friction coefficient of the pressure head H. For example, as illustrated in
Therefore, even if the width of the first to the fourth top surface electrodes 623a to 623d decreases as the electrode pitch of the semiconductor chip 100 becomes finer, it is possible to accurately position the first to the fourth bumps 120a to 120d with respect to the first to the fourth top surface electrodes 623a and 623d. Further, when the semiconductor chip 100 is started to be pressed, the central axes Oa to Od of the first to the fourth bumps 120a to 120d only have to be arranged on the first to the fourth mounting portions 627a to 627d. Thus the positioning operation is not difficult.
When the semiconductor chip 100 is accurately positioned, the semiconductor chip 100 is further pressed onto the circuit board 200. Then, the first to the fourth bumps 120a to 120d plastically flows from the first to the fourth protrusion portions 626a to 626d to the first to the fourth mounting portions 627a to 627d, and as illustrated in
As described above, in the present embodiment, even when the semiconductor chip 100 is slightly shifted with respect to the circuit board 200, in the process for moving the semiconductor chip 100 closer to the circuit board 200, the positions of the first to the fourth bumps 120a to 120d are gradually corrected and the semiconductor chip 100 is accurately positioned. Specifically, when the semiconductor chip 100 is moved closer to the circuit board 200, the first to the fourth bumps 120a to 120d automatically approach the correct positions thereof and the semiconductor chip 100 is accurately positioned. Further, the first to the fourth bumps 120a to 120d are held by the first to the fourth restriction surfaces 629a to 629d, so the semiconductor chip 100 does not shift in the process for pressing the semiconductor chip 100 onto the circuit board 200. As a result, the first to the fourth bumps 120a to 120d do not drop out of the first to the fourth top surface electrodes 623a to 623d.
According to the present embodiment, the semiconductor chip 100 can be accurately positioned by only forming the first to the fourth protrusion portions 626a to 626d on the first to the fourth pad portions 625a to 625d. Therefore, the first to the fourth top surface electrodes formed on the circuit board 200 need not be widened. Therefore, it is possible to make the electrode pitch of the semiconductor chip 100 much finer.
In the present embodiment, all the first top surface electrodes 623a include the first protrusion portion 626a. However the present embodiment is not limited to this. For example, at least one of the first top surface electrodes 623a only has to include the first protrusion portion 626a. This is the same for the second to the fourth top surface electrodes 623b to 623d.
In the present embodiment, the first top surface electrode 623a is located nearer to the fourth board edge 210d than the second top surface electrode 623b. However the present embodiment is not limited to this. If the first restriction surface 629a is located nearer to the fourth board edge 210d than the second restriction surface 629b, the locations and the shapes of the first and the second top surface electrodes 623a and 623b are not particularly limited. For example, it is possible to locate the first and the second top surface electrodes 623a and 623b at the same distance from the fourth board edge 210d and set the width of the first and the second protrusion portions 626a and 626b smaller than one half of the width of the first and the second pad portions 625a and 625b. In this way, the first restriction surface 629a can also be located nearer to the fourth board edge 210d than the second restriction surface 629b. This is the same for the third and the fourth top surface electrodes 623c to 623d.
Hereinafter, a modified example 1 of the second embodiment will be described with reference to
Assuming that the semiconductor chip 100 do not include the third and the fourth bumps 120c and 120d, as illustrated in
The numbers and the pitches of the first top surface electrodes 723a included in the first type T1 and the first top surface electrodes 723a included in the second type T2 are the same. In the same manner, the numbers and the pitches of the second top surface electrodes 723b included in the first type T1 and the second top surface electrodes 723b included in the second type T2 are the same.
In the first type T1, the first and the second protrusion portions 726a and 726b are respectively provided on the end portions of the first and the second pad portions 725a and 725b facing the third board edge 210c, and first and second restriction surfaces 729a and 729b are formed on surfaces of the first and the second protrusion portions 726a and 726b facing the fourth board edge 210d. The first and the second protrusion portions 726a and 726b according to the first type T1 respectively define first and second mounting portions 727a and 727b in an area nearer to the fourth board edge 210d on the first and the second pad portions 725a and 725b.
In the second type T2, the first and the second protrusion portions 726a and 726b are respectively provided on the end portions of the first and second pad portions 725a and 725b facing the fourth board edge 210d, and the first and the second restriction surfaces 729a and 729b are formed on surfaces of the first and the second protrusion portions 726a and 726b facing the third board edge 210c. The first and the second protrusion portions 726a and 726b according to the second type T2 respectively define the first and the second mounting portions 727a and 727b in an area nearer to the third board edge 210c on the first and the second pad portions 725a and 725b.
As a result, the first restriction surface 729a of the first type T1 faces a direction opposite to that faced by the first restriction surface 729a of the second type T2. In the same manner, the second restriction surface 729b of the first type T1 faces a direction opposite to that faced by the second restriction surface 729b of the second type T2. The position of the first mounting portion 727a of the first type T1 is opposite to the position of the first mounting portion 727a of the second type T2. In the same manner, the position of the second mounting portion 727b of the first type T1 is opposite to the position of the second mounting portion 727b of the second type T2.
At boundary portions between the first type T1 and the second type T2 of the first top surface electrodes 723a and the second top surface electrodes 723b, there are gaps larger than the pitches of the electrodes, that is, sections Ra and Rb in which no top surface electrode is formed. By arranging the first and the second top surface electrodes 723a and 723b as described above, when the semiconductor chip 100 is moved closer to the circuit board 200, the central axes Oa and Ob of the first and the second bumps 120a and 120b are respectively arranged on the first and the second mounting portions 727a and 727b and the first and the second bumps 120a and 120b can respectively come into contact with the first and the second restriction surfaces 729a and 729b.
When employing the present modified example, if the semiconductor chip 100 is positioned so that the central axes Oa and Ob of the first and the second bumps 120a and 120b are located on the first and the second mounting portions 727a and 727b of the circuit board 200, and the semiconductor chip 100 is pressed onto the circuit board 200, the semiconductor chip 100 can be accurately positioned as described above.
However, the first and the second top surface electrodes 723a and 723b according to the present modified example are different from those in the second embodiment, so the reaction forces applied to the first and the second bumps 120a and 120b when the semiconductor chip 100 is pressed onto the circuit board 200 are different from the first and the second reaction forces F1a and F2b according to the second embodiment.
For example, when the semiconductor chip 100 is pressed onto the circuit board 200, in the first type T1, a first reaction force Ft1a in parallel with the mounting surface of the circuit board 200 is applied from the first protrusion portions 726a of the first top surface electrodes 723a to the first bumps 120a. A third reaction force Ft1b in parallel with the mounting surface of the circuit board 200 is applied from the second protrusion portions 726b of the second top surface electrodes 723b to the second bumps 120a. In the second type T2, a second reaction force Ft2a that offsets the first reaction force Ft1a is applied from the first protrusion portions 726a of the first top surface electrodes 723a to the first bumps 120a. A fourth reaction force Ft2b that offsets the third reaction force Ft1b is applied from the second protrusion portions 726b of the second top surface electrodes 723b to the second bumps 120a.
Although the present modified example assumes that the semiconductor chip 100 does not include the third and the fourth bumps 120c and 120d, it is not limited to this. For example, the semiconductor chip 100 may include the first to the fourth bumps 120a to 120d. In this case, the shapes of the third and the fourth top surface electrodes (not illustrated in
Hereinafter, a modified example 2 of the second embodiment will be described with reference to
As illustrated in
Although, in the present modified example, the positions of the first type T1 and the second type T2 of the second top surface electrodes 723b are reversed from those in the modified example 1, it is not limited to this, but the positions of the first type T1 and the second type T2 of either or both of the first and the second top surface electrodes 723a and 723b may be reversed from those in the modified example 1.
Hereinafter, a third embodiment will be described with reference to
Configuration of Semiconductor Device
First, a configuration of a semiconductor device will be described with reference to
Configuration of Circuit Board
As illustrated in
Further, the circuit board 200 according to the third embodiment includes the deformation absorption film 821 that covers the first to the fourth internal wiring patterns 225a to 225d and the top surface insulating film 222. As a material of the deformation absorption film 821, a material having rigidity lower than that of the first to the fourth internal wiring patterns 225a to 225d and the top surface insulating film 222, for example, an epoxy resin or a phenol resin is used. The film thickness of the deformation absorption film 821 is, for example, about 20 μm to 40 μm.
The deformation absorption film 821 is formed on the first to the fourth internal wiring patterns 225a to 225d and the top surface insulating film 222, and first to fourth post portions 822a to 822d are respectively buried at positions corresponding to the first to the fourth internal wiring patterns 225a to 225d. The first to the fourth post portions 822a to 822d are formed over the entire width of the first to the fourth internal wiring patterns 225a to 225d and respectively connected to the first to the fourth internal wiring patterns 225a to 225d. As a material of the first to the fourth post portions 822a to 822d, an electrically conductive material having rigidity higher than that of the deformation absorption film 821, for example, a metal such as Cu is used. The film thickness of the first to the fourth post portions 822a to 822d is substantially the same as the film thickness of the deformation absorption film 821.
The first to the fourth top surface electrodes 823a to 823d according to the third embodiment are arranged corresponding to the first to the fourth internal wiring patterns 225a to 225d, and respectively include first to fourth fixed portions 824a to 824d and first to fourth flexible beam portions 825a to 825d.
The first to the fourth fixed portions 824a to 824d are respectively arranged on the first to the fourth post portions 822a to 822d and electrically connected to the first to the fourth post portions 822a to 822d. The first to the fourth flexible beam portions 825a to 825d are respectively arranged on the deformation absorption film 821, and bend closer to the core member 210 as the distance from the first to the fourth post portions 822a to 822d of the circuit board 200 increases.
The first to the fourth bumps 120a to 120d of the semiconductor chip 100 are respectively connected to the first to the fourth flexible beam portions 825a to 825d. Therefore, the distance G1 between the first post portion 822a and the second post portion 822b is set to be greater than the distance G4 between the central axis Oa of the first bump 120a and the central axis Ob of the second bump 120b. More preferably, the distance G1 between the first post portion 822a and the second post portion 822b is set to be greater than the distance G3 obtained by adding two times the diameter d of the first and the second bumps 120a and 120b (=2d) to the distance G2 between the first bump 120a and the second bump 120b. When employing the above distances, the entire portions of the first and the second bumps 120a and 120b can be connected to the first and the second flexible beam portions 825a and 825b. Specifically, the semiconductor chip 100 can be positioned so that the first and the second bumps 120a and 120b are not connected to the first and the second fixed portions 824a and 824b. Similarly, the distance G1 between the third post portion 822c and the fourth post portion 822d is set to be greater than the distance G4 between the central axis Oc of the third bump 120c and the central axis Od of the fourth bump 120d. More preferably, the distance G1 between the third post portion 822c and the fourth post portion 822d is set to be greater than the distance G3 obtained by adding two times the diameter d of the third and the fourth bumps 120c and 120d (=2d) to the distance G2 between the third bump 120c and the fourth bump 120d. When employing the above distances, the entire portions of the third and the fourth bumps 120c and 120d can be connected to the third and the fourth flexible beam portions 825c and 825d. Specifically, the semiconductor chip 100 can be positioned so that the third and the fourth bumps 120c and 120d are not connected to the third and the fourth fixed portions 824c and 824d.
Manufacturing Method of Circuit Board
Next, a manufacturing method of the circuit board will be described with reference to
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
In this way, the circuit board 200 according to the third embodiment is completed. As described above, the circuit board 200 can be easily manufactured by only performing film formation and etching on a glass epoxy board used in ordinary semiconductor devices.
Manufacturing Method of Semiconductor Device
Next, a manufacturing method of the semiconductor device will be described with reference to
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
When the first to the fourth bumps 120a to 120d come into contact with the first to the fourth flexible beam portions 825a to 825d, the semiconductor chip 100 is started to be pressed onto the circuit board 200. Then, the first to the fourth flexible beam portions 825a to 825d are pressed by the first to the fourth bumps 120a to 120d and bend closer to the core member 210. Thereby the first to the fourth bumps 120a to 120d are accurately positioned with respect to the first to the fourth top surface electrodes 823a to 823d through a positioning process described below. When the first to the fourth bumps 120a to 120d are accurately positioned, the semiconductor chip 100 is also accurately positioned with respect to the circuit board 200.
Then, the semiconductor chip 100 is further pressed to respectively connect the first to the fourth bumps 120a to 120d to the first to the fourth flexible beam portions 825a to 825d. At this time, the first to the fourth bumps 120a to 120d are deformed according to the shapes of the first to the fourth flexible beam portions 825a to 825d. Thereby the sharp top end portions of the first to the fourth bumps 120a to 120d are flattened.
When the first to the fourth bumps 120a to 120d are respectively connected to the first to the fourth flexible beam portions 825a to 825d, while the semiconductor chip 100 is still pressed onto the circuit board 200, the semiconductor chip 100 is heated by a heater (not illustrated in the drawings) provided in the pressure head H to solidify the epoxy system resin L in the gap between the semiconductor chip 100 and the circuit board 200. Thereby the epoxy system resin L contracts, and the semiconductor chip 100 and the circuit board 200 are bonded together. As described above, the semiconductor chip 100 is bonded to the circuit board 200 while the semiconductor chip 100 is pressed onto the circuit board 200, so the first to the fourth flexible beam portions 825a to 825d bend toward the core member 210 also in the completed semiconductor device.
Next, as illustrated in
Positioning Process of Semiconductor Chip
Next, the positioning process of the semiconductor chip 100 will be described with reference to
First, as illustrated in
Next, the pressure head H is lowered and the semiconductor chip 100 is moved closer to the circuit board 200. When the first to the fourth bumps 120a to 120d come into contact with the first to the fourth flexible beam portions 825a to 825d, the semiconductor chip 100 is started to be pressed onto the circuit board 200. Then, the first to the fourth flexible beam portions 825a to 825d bend closer to the core member 210 as the position moves to inner side of the circuit board 200. Thereby, as illustrated in
When the first and the second bumps 120a and 120b move toward the second board edge 210b, the deformations of the first and the second flexible beam portions 825a and 825b are gradually equalized. Then, as illustrated in
In this way, when the semiconductor chip 100 is accurately positioned in the X direction of the circuit board 200, in the same manner as in the first embodiment, the third and the fourth bumps 120c and 120d are also accurately positioned in the X direction of the circuit board 200. Specifically, the third and the fourth bumps 120c and 120d are accurately positioned in the width direction of the third and the fourth top surface electrodes 823c and 823d, that is, the direction perpendicular to the longitudinal direction. Therefore, even if the width of the third and the fourth top surface electrodes 823c and 823d decreases as the electrode pitch of the semiconductor chip 100 becomes finer, it is possible to reliably mount the third and the fourth bumps 120c and 120d on the third and the fourth top surface electrodes 823c and 823d. Further, when the semiconductor chip 100 is started to be pressed, the first and the second bumps 120a and 120b only have to be arranged on the first and the second flexible beam portions 825a and 825b. Thus the positioning operation is not difficult.
Although here, it is assumed that the semiconductor chip 100 is shifted toward the first board edge 210a (toward the left side in
When the semiconductor chip 100 is accurately positioned in the X direction of the circuit board 200, the semiconductor chip 100 is further pressed onto the circuit board 200. Then the sharp top end portions of the first and the second bumps 120a and 120b are flattened and connected to the first and the second flexible beam portions 825a and 825b. At this time, the first and the second bumps 120a and 120b are respectively held on the tilted top surfaces of the first and the second flexible beam portions 825a and 825b. In other words, the first and the second reaction forces F3a and F3b are respectively applied to the first and the second bumps 120a and 120b. Therefore, while the semiconductor chip 100 is being pressed onto the circuit board 200, the position of the semiconductor chip 100 is not shifted in the X direction of the circuit board 200. Therefore, in the process for mounting the semiconductor chip 100 on the circuit board 200, the third and the fourth bumps 120c and 120d do not drop out of the third and the fourth flexible beam portions 825c and 825d.
Although the cooperation between the first and the second bumps 120a and 120b and the first and the second top surface electrodes 823a and 823b has been focused and described, this is the same for the cooperation between the third and the fourth bumps 120c and 120d and the third and the fourth top surface electrodes 823c and 823d.
For example, if the semiconductor chip 100 is shifted toward the third board edge 210c in the Y direction of the circuit board 200, the third reaction force F3c applied from the third flexible beam portion 825c to the third bump 120c is larger than the fourth reaction force F3d applied from the fourth flexible beam portion 825d to the fourth bump 120d. Thereby the third and the fourth bumps 120c and 120d move toward the fourth board edge 210d while sliding on the third and the fourth flexible beam portions 825c and 825d by a resultant force of the third and the fourth reaction forces F3c and F3d.
When the third and the fourth bumps 120c and 120d move toward the fourth board edge 210d, the deformations of the third and the fourth flexible beam portions 825c and 825d are gradually equalized. Then, when the distance from the third bump 120c to the third post portion 822c becomes the same as the distance from the fourth bump 120d to the fourth post portion 822d, the deformations of the third and the fourth flexible beam portions 825c and 825d become the same. Then, the third and the fourth reaction forces F3c and F3d applied to the third and the fourth bumps 120c and 120d are balanced and offset each other, so that the movement of the semiconductor chip 100 stops. In this way, the third and the fourth bumps 120c and 120d are accurately positioned in the longitudinal direction of the third and the fourth flexible beam portions 825c and 825d, that is, the Y direction of the circuit board 200. When the third and the fourth bumps 120c to 120d are positioned in the Y direction of the circuit board 200, the semiconductor chip 100 is also accurately positioned in the Y direction of the circuit board 200.
In this way, when the semiconductor chip 100 is accurately positioned in the Y direction of the circuit board 200, in the same manner as in the first embodiment, the first and the second bumps 120a and 120b are also accurately positioned in the Y direction of the circuit board 200. Specifically, the first and the second bumps 120a and 120b are accurately positioned in the width direction of the first and the second top surface electrodes 823a and 823b, that is, the direction perpendicular to the longitudinal direction. Therefore, even if the width of the first and the second top surface electrodes 823a and 823b decreases as the electrode pitch of the semiconductor chip 100 becomes finer, it is possible to reliably mount the first and the second bumps 120a and 120b on the first and the second top surface electrodes 823a and 823b. Further, when the semiconductor chip 100 is started to be pressed, the third and the fourth bumps 120c and 120d only have to be arranged on the third and the fourth flexible beam portions 825c and 825d. Thus the positioning operation is not difficult.
Although here, it is assumed that the semiconductor chip 100 is shifted toward the third board edge 210c in the Y direction of the circuit board 200, if the semiconductor chip 100 is slightly shifted toward the fourth board edge 210d in the Y direction of the circuit board 200, the positioning operation can be performed in the same manner as described above.
When the semiconductor chip 100 is accurately positioned in the Y direction of the circuit board 200, the semiconductor chip 100 is further pressed onto the circuit board 200. Then the sharp top end portions of the third and the fourth bumps 120c and 120d are flattened and connected to the third and the fourth flexible beam portions 825c and 825d. At this time, the third and the fourth bumps 120c and 120d are respectively held on the tilted top surfaces of the third and the fourth flexible beam portions 825c and 825d. In other words, the third and the fourth reaction forces F3c and F3d are respectively applied to the third and the fourth bumps 120c and 120d. Therefore, while the semiconductor chip 100 is being pressed onto the circuit board 200, the position of the semiconductor chip 100 is not shifted in the Y direction of the circuit board 200. Therefore, in the process for mounting the semiconductor chip 100 on the circuit board 200, the first and the second bumps 120a and 120b do not drop out of the first and the second flexible beam portions 825a and 825b.
Although here the positioning in the X direction and the positioning in the Y direction of the semiconductor chip 100 are separately described, the positioning in the X direction and the positioning in the Y direction of the semiconductor chip 100 progress simultaneously.
As described above, in the present embodiment, even when the semiconductor chip 100 is slightly shifted in the X direction or the Y direction of the circuit board 200, in the process for moving the semiconductor chip 100 closer to the circuit board 200, the position of the semiconductor chip 100 is gradually corrected and the semiconductor chip 100 is accurately positioned. Specifically, when the semiconductor chip 100 is moved closer to the circuit board 200, the first to the fourth bumps 120a to 120d automatically approach the correct positions thereof and the semiconductor chip 100 is accurately positioned. Further, the first to the fourth bumps 120a to 120d are held on the tilted top surfaces of the first to the fourth flexible beam portions 825a to 825d, so the semiconductor chip 100 does not shift in the process for pressing the semiconductor chip 100 onto the circuit board 200. As a result, the first to the fourth bumps 120a to 120d do not drop out of the first to the fourth flexible beam portions 825a to 825d.
According to the present embodiment, the semiconductor chip 100 can be accurately positioned only by providing the first to the fourth fixed portions 824a to 824d arranged on the first to the fourth post portions 822a to 822d and the first to the fourth flexible beam portions 825a to 825d arranged on the deformation absorption film 821 to the first to the fourth top surface electrodes 823a to 823d. Therefore, the first to the fourth top surface electrodes 823a to 823d formed on the circuit board 200 need not be widened. Therefore, it is possible to make the electrode pitch of the semiconductor chip 100 much finer.
In the present embodiment, as a material of the deformation absorption film 821, a material having rigidity lower than that of the first to the fourth post portions 822a to 822d is used. However, the material needs to have rigidity lower than that of the first to the fourth post portions 822a to 822d only when the semiconductor chip 100 is mounted. For example, if a thermoplastic resin is used as the material of the deformation absorption film 821, the thermoplastic resin softens when the semiconductor chip 100 is heated, so the first to the fourth flexible beam portions 825a to 825d bend more easily. Further, when the temperature of the deformation absorption film 821 drops after the heating of the semiconductor chip 100, the deformation absorption film 821 automatically hardens, so it is possible to provide desired strength to the circuit board 200 even after the completion of the semiconductor device. However, the material needs to be selected so that the deformation absorption film 821 does not soften or liquefy by the heat generated when the semiconductor device is actually used. If a B-stage resin is used as the material of the deformation absorption film 821, the deformation absorption film 821 transitions to a B-stage resin and softens when the semiconductor chip 100 is heated, so the first to the fourth flexible beam portions 825a to 825d bend more easily. In addition, when the semiconductor chip 100 is further heated, the deformation absorption film 821 transitions to C-stage and hardens naturally, so it is possible to provide desired strength to the circuit board 200 even after the completion of the semiconductor device. However, the material needs to be selected so that the heating temperature of the semiconductor chip 100 corresponds to the temperature at which the deformation absorption film 821 transitions to B-stage, that is, the B-stage temperature.
Hereinafter, a modified example of the third embodiment will be described with reference to
First to fourth top surface electrodes 923a to 923d according to the present modified example extend toward the opposite side of those in the third embodiment with respect to first to fourth post portions 922a to 922d, that is, toward the outside of the circuit board 200. Specifically, the first to the fourth top surface electrodes 923a to 923d include first to fourth fixed portions 924a to 924d arranged on the first to the fourth post portions 922a to 922d and first to fourth flexible beam portions 925a to 925d which are arranged on the deformation absorption film 821 and extend from the first to the fourth fixed portions 924a to 924d toward the outside of the circuit board 200.
The first to the fourth bumps 120a to 120d of the semiconductor chip 100 are respectively mounted on the first to the fourth flexible beam portions 925a to 925d. Therefore, the distance G1 between the outer side surface of the first post portion 922a and the outer side surface of the second post portion 922b is set to be smaller than the distance G4 between the central axis Oa of the first bump 120a and the central axis Ob of the second bump 120b. More preferably, the distance G1 between the outer side surface of the first post portion 922a and the outer side surface of the second post portion 922b is set to be smaller than the distance G2 between the first bump 120a and the second bump 120b. When employing the above distances, the entire portions of the first and the second bumps 120a and 120b can be connected to the first and the second flexible beam portions 925a and 925b. Specifically, the semiconductor chip 100 can be positioned so that the first and the second bumps 120a and 120b are not connected to the first and the second fixed portions 924a and 924b. Similarly, the distance G1 between the outer side surface of the third post portion 922c and the outer side surface of the fourth post portion 922d is set to be smaller than the distance G4 between the central axis Oc of the third bump 120c and the central axis Od of the fourth bump 120d. More preferably, the distance G1 between the outer side surface of the third post portion 922c and the outer side surface of the fourth post portion 922d is set to be smaller than the distance G2 between the third bump 120c and the fourth bump 120d. When employing the above distances, the entire portions of the third and the fourth bumps 120c and 120d can be connected to the third and the fourth flexible beam portions 925c and 925d. Specifically, the semiconductor chip 100 can be positioned so that the third and the fourth bumps 120c and 120d are not connected to the third and the fourth fixed portions 924c and 924d.
As described in the present modified example, the first to the fourth top surface electrodes 923a to 923d may extend toward the opposite side of those in the third embodiment with respect to the first to the fourth post portions 922a to 922d. When employing the present modified example, if the semiconductor chip 100 is positioned so that the central axes Oa to Od of the first to the fourth bumps 120a to 120d are located on the first to the fourth flexible beam portions 925a to 925d, and the semiconductor chip 100 is pressed onto the circuit board 200, the semiconductor chip 100 can be accurately positioned as described above. However, the first to the fourth flexible beam portions 925a to 925d tilt in the direction opposite to that in which the first to the fourth flexible beam portions 825a to 825d according to the third embodiment tilt, so the first to the fourth reaction forces according to the present modified example are applied in directions opposite to the directions of the first to the fourth reaction forces according to the third embodiment.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-223298 | Sep 2010 | JP | national |
