Claims
- 1. A method of forming a plurality of integrated circuit chip packages, said method comprising:
providing a substrate having a plurality of sections, each of said sections having first metallizations formed on a first surface of said substrate; coupling an integrated circuit chip to a corresponding one of each of said sections of said substrate; electrically connecting each said integrated circuit chip to said first metallizations on said corresponding one of said sections; encapsulating said integrated circuit chips, said first metallizations and said first surface of said substrate with a layer of an encapsulant, wherein said layer of the encapsulant has an outer first surface overlying the integrated circuit chips; placing the first surface of the layer of the encapsulant on a surface, and immobilizing the encapsulated substrate on said surface; cutting said encapsulated substrate while on said surface along a periphery of each of said sections to form said plurality of integrated circuit chip packages.
- 2. The method of claim 1, wherein said surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.
- 3. The method of claim 1, further comprising electrically testing said packages while said packages are immobilized on said surface.
- 4. The method of claim 1, wherein each of said sections has second metallizations formed on a second surface of said substrate opposite said first surface and electrically conductive paths extending through said substrate from said first metallizations to said second metallizations.
- 5. The method of claim 4, further comprising forming interconnection balls on said second surface of said substrate at each of said sections, each of said interconnection balls being in electrical connection with one of said second metallizations.
- 6. The method of claim 1, wherein said cutting is done with a saw.
- 7. The method of claim 1, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.
- 8. A method of forming a plurality of integrated circuit chip packages, said method comprising the steps of:
providing a substrate having a first surface and a plurality of sections, each said section having an integrated circuit chip coupled to the first surface of the substrate within the respective section, wherein a layer of an encapsulant covers the first surface of the substrate and the integrated circuits, said layer of the encapsulant having an outer surface overlying the integrated circuit chips; placing the first surface of the layer of the encapsulant on a surface, and immobilizing the encapsulated substrate thereon; cutting said encapsulated substrate along a periphery of each of said sections to form said plurality of integrated circuit chip packages.
- 9. The method of claim 8, wherein said surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.
- 10. The method of claim 8, further comprising electrically testing said packages while said packages are immobilized on said surface.
- 11. The method of claim 10, further comprising forming interconnection balls on a second surface of said substrate at each of said sections, said interconnection balls being electrically coupled to the integrated circuit chip of the respective section.
- 12. The method of claim 8, wherein said cutting is done with a saw.
- 13. The method of claim 8, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.
- 14. A method of forming a plurality of integrated circuit chip packages, said method comprising the steps of:
providing a substrate having a plurality of sections, each said section having an integrated circuit chip coupled to a first surface of the substrate within the section, wherein a layer of an encapsulant covers the first surface of the substrate and the integrated circuits, said layer of the encapsulant having an outer surface overlying the integrated circuit chips; placing the first surface of the layer of the encapsulant on a surface, and immobilizing the encapsulated substrate thereon; and cutting said encapsulated substrate from the substrate through the layer of the encapsulant along a periphery of each of said sections while on said surface to form said plurality of integrated circuit chip packages.
- 13. The method of claim 14, wherein said surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.
- 16. The method of claim 15, further comprising electrically testing said packages while said packages are immobilized on said surface.
- 17. The method of claim 16, further comprising forming interconnection balls on a second surface of said substrate at each of said sections, each of said interconnection balls being in electrical connection with the integrated circuit chip of the respective section.
- 18. The method of claim 14, wherein said cutting is done with a saw.
- 19. The method of claim 14, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. patent application Ser. No. 09/585,901, filed Jun. 2, 2000, which is a division of U.S. patent application Ser. No. 09/083,524, filed May 22, 1998, which is continuation-in-part of U.S. patent application Ser. No. 08/741,797, filed Oct. 31, 1996, by Thomas P. Glenn et al., all of which applications are herein incorporated by reference in their respective entirety.
Divisions (2)
|
Number |
Date |
Country |
Parent |
09585901 |
Jun 2000 |
US |
Child |
10150400 |
May 2002 |
US |
Parent |
09083524 |
May 1998 |
US |
Child |
09585901 |
Jun 2000 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
08741797 |
Oct 1996 |
US |
Child |
09083524 |
May 1998 |
US |