Patent Application
20070023901
Integrated circuits (ICs) may include bond pads so that electrical connectors and/or conductors, such as bonding wires and/or metallic bumps, may be connected to electrical devices within the IC. Bond pads are spaced horizontally, i.e., in the same plane, from the electrical devices of the IC such that the bond pads are positioned in a periphery of the IC. Accordingly, the bond pads utilize valuable surface area and allow limited flexibility of positioning of the bond pads on the IC. It may be desirable to form a bond pad that utilizes less surface area on the IC and which allows flexibility in positioning of the bond pad on the IC.
In particular, IC 10 includes a stacked layer arrangement 36 including a device support or a substrate layer 38, such as a gallium arsenide substrate. An isolation implant layer 40 may then be formed on or within substrate 38. The isolation damage implant layer 40 may be formed of Aluminum or Boron ions or other suitable elements. One or more electrical devices 34 may then be formed on substrate 38 or on isolation implant layer 40, such that the substrate forms a first plane 42 and the electrical devices 34 form a second plane 44 positioned generally parallel to and vertically above first plane 42 in an upward direction 46. The term upward is used for ease of illustration. However, the integrated circuit may be oriented in any direction wherein the layers of the stacked arrangement are successively built on the preceding layer there beneath. A lower dielectric layer 48 may then be formed on electrical device 34, wherein lower dielectric layer 48 forms a third plane 50 positioned generally parallel to and vertically above second plane 44 as measured along direction 46. Lower dielectric layer 48 may be a BCB spin-on dielectric.
A first metal layer 52 may then be formed on lower dielectric layer 48, wherein first metal layer 52 forms a fourth plane 54 positioned generally parallel to and vertically above third plane 50 as measured along direction 46. Lower dielectric layer 48 may include vias or trenches 56 such that first metal layer 52 may extend downwardly through lower dielectric layer 48 and electrically contact one or more of electrical devices 34. A second or upper dielectric layer 58 may then be formed on first metal layer 52, wherein upper dielectric layer 58 forms a fifth plane 60 positioned generally parallel to and vertically above fourth plane 54, as measured along direction 46. A second or upper metal layer 62 may then be formed on upper dielectric layer 58, wherein upper metal layer 62 forms a sixth plane 64 positioned generally parallel to and vertically above fifth plane 60, as measured along direction 46. Upper dielectric layer 58 may include vias or trenches 65 such that second metal layer 62 may extend downwardly through upper dielectric layer 58 and electrically contact first metal layer 52.
A passivation or third dielectric layer 66 may then be formed on upper metal layer 62, wherein passivation dielectric layer 66 forms a seventh plane 68 positioned generally parallel to and vertically above sixth plane 64, as measured along direction 46. Passivation dielectric layer 66 may include a trench or a via 70 such that a portion 72 of second metal layer 62 is exposed. This exposed portion 72 of second metal layer 62 may define the bond pad 32 of integrated circuit 10. A conductive connector, such as an electrically conductive wire 74 may be bonded to exposed portion 72 of second metal layer 62.
Electrical devices 34 may be physically and thermally protected from the bonding operation, wherein wire 74 is bonded to bond pad 32, by upper dielectric layer 58. Accordingly, rather than being spaced outwardly in a horizontal direction 47 from electrical devices 34 in plane 44, bond pad 32 is spaced upwardly from electrical device 34 in a direction 46 and positioned directly above device 34, i.e., aligned with device 34 along a vertical axis 49.
Accordingly, wire 74 is bonded to bond pad 32, wherein bond pad 32 is positioned above one or more electrical devices 34. A width 76 of IC 10, therefore, may be defined by a width 78 of multiple devices 34, as measured in plane 44. In other words, second metal layer 62, which includes bond pad 32, is not positioned within plane 44, such that width 76 of IC 10 is not dependent upon, and is not increased by, width 80 of second metal layer 62. Positioning of bond pad 32 above electrical devices 34, therefore, may reduce the footprint or surface area of IC 10, which may result in increased working speeds of the IC and lower manufacturing costs. Additionally, positioning of bond pad 32 in a plane 64 different from plane 44 of electrical devices 34 allows flexibility in positioning of bond pad 32, i.e., positioning of bond pad 32 in plane 64 allows bond pad 32 to be positioned in many more positions than would be available if bond pad 32 were positioned in plane 44 with electrical devices 34.
The process variables will now be described. Lower and upper dielectric layers 48 and 58 may be formed of Benzocyclobutene (BCB) spin-on dielectrics used to electrically isolate metal interconnect layers from underlying circuitry. In one embodiment the spin-on dielectrics may be deposited as a viscous liquid onto a spinning wafer substrate. The thickness of the dielectric may be determined by the spin speed of the wafer substrate at the time of dispense. In one embodiment of the present invention, upper and lower dielectric layers 48 and 58 are 1 and 2.8 um (microns), respectively, but may be deposited in a thickness range of 1 to 10 um. The dielectric layers may be cured after deposit by heating in an oven at 300° C. The resulting dielectric layer may take on a glass-like hardness.
Via holes 56, 65 and/or 70 may be defined in their respective cured dielectric layer for the purpose of making connections between the metal interconnect layers and to the underlying circuitry. The vias are fabricated by defining a photoresist pattern on the corresponding dielectric layer and etching away the unprotected areas of dielectric material in a high density plasma etching system using, in one example embodiment, a sulfurhexafluoride plus oxygen (SF6+02) plasma or other suitable fluorine containing gas.
One or more bond pads 32 may be defined in upper metal layer 62. Both lower and upper metal layers 52 and 62 may be fabricated by electrochemical plating gold (Au) on top of a suitable field metal. The Au thicknesses used in one embodiment of layers 52 and 62 may be 2 and 4 um, respectively. In one embodiment, the field metal may be a metal stack of Titanium-Tungsten/Gold/Titanium (TiW/Au/Ti) with layer thicknesses of 500 Å (Angstroms), 1060 Å, and 1000 Å, respectively. However, other field metals and thicknesses may be utilized.
The metal interconnect features within vias 56, 65 and/or 70 may be defined by a photoresist pattern on top of the field metal. The top titanium layer of the field metal may be removed in the unprotected areas of the field metal and Au plated in the features. The top Titanium may then be removed by etching in a reactive ion etcher using a Carbontetraflouride+Nitrogentrifluoride+Argon (CF4+NF3+Ar) plasma, for example. The photoresist, used to define the interconnect features, may then be removed after the plating operation by exposing the photoresist to an oxygen plasma.
The field metal stack left between the plated Au features may then be removed by etching in a high-density plasma etching system. The top Titanium layer of the field metal may be etched in SF6 or another suitable fluorine containing gas. The gas in the plasma etching system may then be switched to Ar, for example, and the Au layer removed by sputtering. The bottom TiW layer may then be etched away by switching the gas back to SF6 or another suitable fluorine containing gas.
Other variations and modifications of the concepts described herein may be utilized and fall within the scope of the claims below.
