Patent Application
20120256193
Understanding that the drawings depict only exemplary embodiments and are not therefore to be considered limiting in scope, the exemplary embodiments will be described with additional specificity and detail through the use of the accompanying drawings, in which:
In accordance with common practice, the various described features are not drawn to scale but are drawn to emphasize specific features relevant to the exemplary embodiments. Like structures are described and shown in the drawings with like reference numbers.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific illustrative embodiments. It is to be understood that other embodiments may be utilized and that mechanical and electrical changes may be made. The following detailed description is, therefore, not to be taken in a limiting sense.
Semiconductor structures that include monolithic integrated capacitors are disclosed herein. The monolithic integrated capacitors can be implemented in various semiconductor structures that include high side devices and low side devices. For example, the monolithic integrated capacitors can be implemented in high-efficiency power converter devices. In other embodiments, the monolithic integrated capacitors can be implemented in half bridge and full bridge drivers.
In one embodiment, a power converter device comprises a conductive substrate, and a power die having an upper surface and a lower surface. The upper surface includes a monolithic integrated capacitor and the lower surface is mounted to the conductive substrate. The power die includes a voltage-in layer coupled to a drain of a device in the power die, and a ground layer coupled to a source of a device in the power die. A packaging material encapsulates the power die and at least a portion of the conductive substrate.
In another embodiment, a monolithic bypass capacitor can be integrated between a voltage input (Vin) of a lateral diffusion metal oxide semiconductor (LDMOS) drain and ground for a vertical diffusion metal oxide semiconductor (VDMOS) source, on top of a power die. The integration of bypass capacitors with the power die compensates for parasitic inductances by providing increased efficiency through reduction of the switching power losses. The monolithic integrated capacitors provide a further reduction in parasitic inductance between the capacitor electrode and switching elements, and also provide a reduced profile thickness. The integrated capacitors can be implemented with a capacitance value selected to minimize power loss of the power converter.
The present approach is particularly suitable for fabrication of DC-DC synchronous power converters. Additional benefits of the present monolithic approach include a lower cost, as there is no need to assemble a discrete capacitor, and smaller size (particularly thinner). The present monolithic approach becomes even more effective as the frequency of operation of the circuits increases, since parasitic inductance becomes more of an issue at higher frequencies, and as frequencies go up, the amount of bypass/filtering capacitance reduces.
The present power converters can be combined in a package with an optional integrated circuit (IC) die to produce a “stand alone” power converter or regulator product. The IC die can be a full featured switching modulator and converter, which generates a pulse-width modulation (PWM) signal, drives the gates of the metal oxide semiconductor field effect transistors (MOSFETs) in the power die, has over current and over voltage protection, etc. The IC die can also be a gate driver, which takes a single PWM signal and drives the gates of the MOSFETs in the power die, a switching regulator circuit, or the like. In addition, the converter/modulator circuit can be implemented using Complementary Metal Oxide Semiconductor (CMOS), BiCMOS, double-diffused MOS (DMOS), or Bipolar CMOS DMOS (BCD) technologies. The IC die can be implemented to drive a single phase power die, or multiple phases including multiple power dies.
The various embodiments described hereafter with reference to the drawings incorporate monolithic integrated capacitors in MOS structures.
The power die 201 includes a high-side output power device 204 at a first location 205 over substrate 203, and a low-side output power device 206 over substrate 203 at a second location 207 adjacent to first location 205. In one embodiment, the high-side output power device 204 can include a high performance N-channel LDMOS field effect transistor (FET), and the low-side output power device 206 can include an N-channel VDMOS FET having a trench-gate. Additionally, substrate 203 can provide a switched node (i.e., output node) for power die 201 the bottom of substrate 303. In other embodiments, the output node is not at the bottom of the substrate, but is connected using metal layers.
An epitaxial layer 208 is formed over an upper surface of substrate 203. A blanket N-type drift implant 210 can formed in epitaxial layer 208 by doping with phosphorous, for example. A patterned deep body P-type implant 212 can be formed in epitaxial layer 208 by doping with boron, for example.
A field oxide region 214 is formed over epitaxial layer 208. Individual polysilicon gate portions 216A and 216B are formed over oxide region 214, and polysilicon gate portions 216C and 216D are formed within epitaxial layer 208. The gate portions 216A and 216B form a gate of the high-side device, and gate portions 216C and 216D form portions of a gate for one of the active cells of the low-side device. Body implant regions 218A-218E are also formed in epitaxial layer 208.
Individual conductive structures 220A and 220B, such as a tungsten deep trench fill, are formed over the active region of the high-side device. Similarly, conductive structures 220C-220E, which can also be tungsten deep trench fill, are formed over the active region of the low-side device. Conductive structures 220A and 220B form gate shields to the high-side gate portions 216A and 216B. Conductive structure 220C provides a portion of a floating guard ring, and conductive structures 220D and 220E provide contact portions to the low-side source. An oxide layer 222 is formed over the top of the conductive structures 220A-220E.
A drain 224 is located on the high-side device and a gate contact 226 is located on the low-side gate. A metal barrier layer 228 is formed over oxide layer 222, and individual contact plugs 230A-230D extend from barrier layer 228 through oxide layer 222 to make various electrical contacts with underlying structures. For example, contact plugs 230A and 230D make electrical contact with drain 224 and gate contact 226, respectively.
A plurality of metal layers 232 are formed over barrier layer 228. In one embodiment, a first metal layer 232A is formed over and electrically coupled to the high-side output power device 204. The first metal layer 232A is conductively coupled to drain 224 through contact plug 230A. The first metal layer 232A can also be electrically coupled with a Vin to provide a high-side transistor drain interconnect. A second metal layer 232B is formed over and electrically coupled to the low-side output power device 206. The second metal layer 232B can be electrically coupled with ground to provide a low-side transistor source interconnect. A third metal layer 232C is coupled to gate contact 226 through contact plug 230D.
Further details related to the structure and fabrication of a power die can be found in copending U.S. patent application Ser. No. 12/471,991, filed on May 26, 2009, the disclosure of which is incorporated by reference. An exemplary power die that can be utilized in the present approach is a PowerDie device produced by Intersil.
In an alternative embodiment, the power die can be configured with two N-channel LDMOS devices. The high-side FET would have the drain on top, and the source connected to the substrate (using a conductive trench, for example), while the low-side FET would have the source on top, and the drain connected to the substrate (using a conductive trench, for example). Such a power die is described, for example, in U.S. patent application Ser. No. 12/898,664, filed on Oct. 5, 2010, the disclosure of which is incorporated by reference. The power die can also be configured with two N-channel LDMOS devices that have their source and drain electrodes connected through the top surface, using multiple layers of metal.
As shown in
The portion of metal layer 232A that forms one bottom electrode is connected to the drain of high side device 204 through contact plug 230A. The portion of metal layer 232B that forms the other bottom electrode is connected to the source of the low side device 206 through contact plug 230B. These two bottom electrodes are at different voltages and not connected to each other. Accordingly, the capacitor can be considered as a single capacitor with two terminals (plugs 230A and 230B) on one side, or as two capacitors (C1+C2; C3+C4) with metal layer 306 (floating top electrode) forming one terminal of each and also forming an ohmic connection therebetween.
During fabrication of integrated capacitor 302, the dielectric layer 304 is formed over metal layers 232A and 232B and a gap 316 therebetween. Thereafter, metal layer 306 is formed over dielectric layer 304. The dielectric layer 304 and metal layer 306 can then be etched according to standard procedures to produce a sidewall 308 adjacent to metal layer 232A and a sidewall 310 adjacent to metal layer 232B. The etched dielectric layer 304 and metal layer 306 expose a surface portion 312 of metal layer 232A and a surface portion 314 of metal layer 232B. The surface portions 312 and 314 provide connection areas for Vin and ground, respectively.
The dielectric layer 304 and metal layer 306 can be formed using various conventional deposition techniques. For example, the electrode layer can be formed using metal deposition techniques, such as sputtering, evaporation, or other techniques including plasma enhanced depositions, and the like. The dielectric layer can be formed using exemplary deposition techniques such as atomic layer deposition (ALD), plasma enhanced depositions, thermal or electron-beam evaporation, and the like.
The dielectric layer 304 can be formed of a single layer of a dielectric material or multiple layers of different dielectric materials. Exemplary dielectric materials include barium strontium titanate (BaSrTiO3), lead zirconium titanate (Pb(ZRi-xTi)O3), strontium titanate (SrTiO3), and tantalum oxide (Ta2O5). These materials provide a dielectric constant greater than about 100. Other suitable dielectric materials include hafnium silicate, zirconium silicate, zirconium dioxide, aluminum oxide, silicon dioxide, silicon nitride, silicon oxynitride, and the like. The dielectric layer can also be a multi-layer structure. The dielectric layer may also include a “seed” or “adhesion” layer to ensure a reliable interface between the dielectric material and metal electrodes on the top and bottom.
The metal layer 306 can be formed of various metal materials such as aluminum, copper, Ti, TiN, Ni, tungsten, silicides, and the like.
As shown in
As shown in
During fabrication of integrated capacitor 402, the dielectric layer 404 is formed over metal layers 232A and 232B and a gap 420 therebetween. The via 409 is then formed in dielectric layer 404 such as by a standard etching process. Thereafter, metal layer 406 is formed over dielectric layer 404. The dielectric layer 404 and metal layer 406 can then be etched according to standard procedures to produce a sidewall 408 adjacent to metal layer 232A and a sidewall 410 adjacent to metal structure 232B.
The etched dielectric layer 404 and metal layer 406 expose a surface portion 412 of metal layer 232A and surface portion 414 of metal layer 232B. The surface portions 412 and 414 provide connection areas for Vin and ground, respectively. In addition, extension area 411 provides additional connection areas in metal layer 406 at surface portions 416 and 418 for connection to the low-side output power device 206 at ground.
The dielectric layer 404 and metal layer 406 can be formed using various conventional deposition techniques, such as discussed above for
As shown in
In an alternative embodiment, the via 409 can be formed over the high side device 204, and the capacitor (C1+C2) can be formed over the low side device 206. The other structures described in
The semiconductor structure 500, such as a power converter, includes a power die 201 such as described above with respect to
As shown in
During fabrication of integrated capacitor 502, the dielectric layer 504 is formed over metal layers 232A and 232B and a gap therebetween. Thereafter, metal layer 506 is formed over dielectric layer 504. The dielectric layer 504 and metal layer 506 can then be etched according to standard procedures to produce a sidewall 510 adjacent to metal layer 232A and a sidewall 512 adjacent to metal layer 232B. The passivation layer 508 is then formed over the top surfaces of integrated capacitor 502 and power die 201. The passivation layer 508 is patterned and etched to expose a surface portion 514 of metal layer 232A and surface portion 516 of metal layer 232B. The surface portions 514 and 516 provide connection areas for Vin and ground, respectively.
The dielectric layer 504, metal layer 506, and passivation layer 508 can be formed using various conventional deposition techniques, such as those discussed above. In addition, dielectric layer 504 can be formed of a single layer of a dielectric material or multiple layers of different dielectric materials, such as with those materials described previously. The metal layer 506 can be formed of various metal materials such as described previously.
The passivation layer 508 can be formed of a single layer of a material or multiple layers of different materials, such as oxides, nitrides, silicon oxynitride, and the like. The passivation layer 508 can also be composed of polyimide or benzocyclobutene (BCB) type films, which are formed by spinning organic materials and curing the materials.
As shown in
The semiconductor structure 600 includes a power die 201 such as described above with respect to
As shown in
During fabrication of integrated capacitor 602, dielectric layer 604 is formed over metal layers 232A and 232B and a gap therebetween. The via 610 is then formed in dielectric layer 604 such as by a standard etching process. Thereafter, metal layer 606 is formed over dielectric layer 604. The dielectric layer 604 and metal layer 606 can then be etched according to standard procedures to produce a sidewall 612 adjacent to metal layer 232A and a sidewall 614 adjacent to metal layer 232B.
The passivation layer 608 is then formed over the top surfaces of integrated capacitor 602 and power die 201. The passivation layer 608 is etched to form openings that expose a surface portion 616 of metal layer 232A, a surface portion 618 of metal layer 232B, and a surface portion 620 of metal layer 606 over via 610. The surface portions 616 and 618 provide connection areas for Vin and ground, respectively. In addition, surface portion 620 provides an additional connection area for connection to the low-side output power device 206.
The dielectric layer 604, electrode layer 606, and passivation layer 608 can be formed using various conventional deposition techniques, such as those discussed above. In addition, dielectric layer 604 can be formed of a single layer of a dielectric material or multiple layers of different dielectric materials, such as with those materials described previously. The electrode layer 606 can be formed of various metal materials such as described previously. The passivation layer 608 can be formed of a single layer of a material or multiple layers of different materials, such as oxides, nitrides, polyimides, silicon oxynitride, BCB, and the like.
As shown in
In one embodiment, semiconductor substrate 703 can be a silicon substrate heavily doped to an N-type conductivity (N+++). An epitaxial layer 708 over substrate 703 can be formed as an N-type epitaxial layer to a thickness that is a function of the desired breakdown voltage of the low-side output power device 706. Additionally, substrate 703 can provide a switched node to an inductor (not shown).
A blanket N-type drift implant 712 can be formed in epitaxial layer 708 by doping with phosphorous, for example. A patterned deep body P-type implant 714 can be formed in epitaxial layer 708 by doping with boron, for example. A field oxide region 716 is formed over epitaxial layer 708. Individual polysilicon gate portions 718A and 718B are formed over oxide region 716, and polysilicon gate portions 718C and 718D are formed within epitaxial layer 708. Body implant regions 720A-720D such as P-type body implants are also formed in epitaxial layer 708.
Individual conductive structures 722A and 722B, such as a tungsten deep trench fill, are formed over the active region of the high-side output power device 704. A conductive structure 722C, which can also be tungsten deep trench fill, is formed over the active region of the low-side output power device 706.
A dielectric layer 724 is formed over the high-side output power device 704 and the low-side output power device 706, including conductive structures 722A-722C. The dielectric layer 724 can be formed of a single layer of a dielectric material or multiple layers of different dielectric materials, such as those described previously.
A plurality of laterally spaced metal layers 726 are formed on dielectric layer 724. A metal layer 726A is over a portion of the high-side output power device 704. The metal layer 726A can form a conductive drain interconnect and be electrically coupled with Vin. Another metal layer 726B is over a portion of the low-side output power device 706. The metal layer 726B can be a TDMOS source metal interconnect that is electrically coupled with ground. A third metal layer 726C can provide a TDMOS gate contact to the low-side transistor gate.
A contact plug 728A, such as a tungsten plug, connects metal layer 726A with the active region of the high-side output power device 704. Contact plugs 728B and 728C, such as tungsten plugs, connect metal layer 726B with the active region of the low-side output power device 706.
As shown in
The integrated capacitor 740 includes metal layer 732, which forms a first electrode layer of the capacitor structure, metal layer 726B, which forms a second electrode layer of the capacitor structure, and a portion of dielectric layer 724 that is between metal layer 732 and metal layer 726B. These structures of integrated capacitor 740 produce capacitance areas C1, C2, and C3.
In addition, integrated capacitor 740 includes metal layer 732, which forms the first electrode layer, contact plugs 728B and 728C, which form another electrode layer of the capacitor structure, and the dielectric material of dielectric layer 724 that is contained in apertures 733 between contact plugs 728B, 728C and metal layer 732. These structures of integrated capacitor 740 produce capacitance areas C4 and C5.
A plurality of electrical connectors 810 are coupled between an upper surface of power die 802 and outer portions 806B of the lead frame. The electrical connectors can be bond wires, conductive plates, conductive clips, and the like. The electrical connectors 810 provide conductive paths between power die 802 and the lead frame. A plurality of bond pads 818 are located on an upper surface of IC die 804. The bond pads 805 and 809 are electrically connected to respective bond pads 818 by electrical connectors 822, which provide power signals from power die 802 to IC die 804. Other bond pads 818 are electrically connected to various outer portions 806B of the lead frame by electrical connectors 824 to provide outside connections for IC die 804.
A packaging material 826, such as a polymer molding compound, encapsulates the various components of power converter 800, including power die 802 and IC die 804, to seal the components from environmental contamination. Thus, the integrated capacitor of power die 802 does not extend outside of the molded plastic package. Exemplary packaging materials include mold compounds formed of various resins including aromatic or multi-aromatic resins, phenolic resins with filler material such as silica, or other materials that improve electro-magnetic interference (EMI) shielding such as resin materials with a ferrite powder filler.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiments shown. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
This application claims the benefit of priority to U.S. Provisional Application No. 61/473,523, filed on Apr. 8, 2011, the disclosure of which is incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61473523 | Apr 2011 | US |
