Patent Application
20110294237
1. Field of the Invention
The present invention relates to a packaging method of a semiconductor device, and particularly to a packaging method of an image sensor that is capable of improving package quality of the image sensor.
2. Description of the Related Art
Image sensor is used for transforming optical signals into electrical signals, and has been mainly used in a variety of digital image electronic devices. Nowadays, the digital image electronic devices have the stream of light, thick, small, high speed and performance. In the process of manufacturing the digital image electronic devices, what is needed to be improved continuously is, for example, to cut down the package cost, to increase the component density and to reduce the component sizes. Thus, the conventional packaging method has not satisfied the demand of present digital image electronic devices.
Generally, the image sensor is packaged by a wafer level package (WLP). The wafer level package refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. In the process of the wafer level package, at first, a previous process is performed, which includes fabricating components on a surface of a wafer, disposing a conductive pattern on the surface of the wafer, and so on. Subsequently, an after process is performed, which includes packaging the whole wafer, testing the whole wafer, and so on. Afterwards, a wafer saw step is performed so as to forming a number of resulting chip packages. In the process of the wafer level package, the steps of wire bonding and filling adhesive are not necessary yet. Therefore, the resulting chip package is practically of the same size as the die.
However, because the wafer level package is base on a whole wafer to process the package, the quality of the die is not considered. Particularly, when the wafer has a poor quality, the quality of the resulting chip package will be affected. In other words, although some dies with poor quality have been found in the process of the wafer level package, the after process such as packaging is still performed. As a result, the material is wasted and the production cost is increased.
Therefore, what is needed is a packaging method of a semiconductor device to overcome the above disadvantages.
The present invention provides a packaging method of semiconductor device that is capable of improving the quality of the resulting package. The package method can use apparatus with different sizes so as to reduce the cost.
To achieve the above-mentioned advantages, the present invention provides a packaging method of semiconductor device. The packaging method of semiconductor device includes the following steps. A wafer including a number of dies is provided. The wafer has an active surface and a back surface opposite to the active surface. The active surface of the wafer adheres to a carrier. Subsequently, a number of openings through the active surface and the back surface of the wafer are formed in each of the dies. Then, an insulating layer is formed on the back surface of the wafer and on the side walls of the openings. A metal layer is formed to cover the insulating layer and the bottoms of the openings. A pattern protective layer is formed to cover the metal layer and to expose the portions of the metal layer outside the openings of each of the die. Afterwards, the carrier is removed and the wafer is sawed so as to separate the dies. Later, a transparent substrate having a number of package units is provided. A spacer is formed at peripheral of each of the package units. A number of good dies are choose from the dies and are disposed on the spacer of each of the package units.
In one embodiment provided by the present invention, the packaging method of semiconductor device further includes a wafer thinning step before the openings are formed.
In one embodiment provided by the present invention, the packaging method of semiconductor device further includes a step of testing known good die before the good dies are choose from the dies.
In one embodiment provided by the present invention, the active surface and the carrier adhere to each other by an adhesive layer disposed between the active surface and the carrier. A material of the adhesive layer is a removable adhesive material.
In one embodiment provided by the present invention, the wafer is a semiconductor wafer comprising a plurality of image sensing components or micro electro mechanical systems.
In one embodiment provided by the present invention, the pattern protective layer extends into the openings, and an interspace is formed between the pattern protective layer and the metal layer on the bottom of the corresponding opening. In one embodiment provided by the present invention, the openings are filled with the pattern protective layer.
In one embodiment provided by the present invention, the process of forming the insulating layer includes the steps of: depositing a layer of an insulating material; and removing the insulating material to remove the portions of the insulating material corresponding to the openings so as to expose the bottoms of the openings.
In one embodiment provided by the present invention, after the good dies of the dies are disposed on the spacer of each of the package units, the packaging method of semiconductor device further includes forming a conductive bump on the exposed metal layer in each of the package units so as to electrically connect the good dies to the transparent substrate; and sawing the transparent substrate so as to separate the package units.
In the packaging method of the present invention, after the through silica vias are formed, the wafer is sawed. Before packaging, the wafer is tested to choose the good dies. Therefore, the quality of the resulting package can be improved. Additionally, because the packaging method of the present invention is not base on a whole wafer to process the package, it is not necessary to use an apparatus having a packaging size identical to the size the wafer. The method can use a variety of apparatuses with different packaging sizes to package the wafer.
These and other features and advantages of the various embodiments disclosed herein will be better understood with respect to the following description and drawings, in which like numbers refer to like parts throughout, and in which:
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In the present embodiment, before the openings 106 are formed, a wafer thinning step can be selectively performed. Thus, the wafer 102 can be thinned to a suitable thickness. The wafer 102 can be thinned using a method selected from a group consisting of etching, milling, grinding and polishing.
Afterwards, referring to
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Then, referring to
In the present embodiment, during the depositing process, the protective material will be filled into the openings 106. That is, the pattern protective layer 112 is partially located in the openings 106. An interspace is formed between the pattern protective layer 112 in the opening 106 and the metal layer 110 at the bottom of the corresponding opening 106. In another embodiment, the openings 106 can be filled with the pattern protective layer 112 (not shown). No interspace is formed between the pattern protective layer 112 in the opening 106 and the metal layer 110 at the bottom of the corresponding opening 106.
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In the packaging method of the present invention, after the through silica vias are formed, the wafer is sawed and tested to choose the good dies at once. Therefore, in the after processes, only the good dies are choose to be packaged. Thus, a wafer with poor quality will not affect the quality of the resulting packages.
After the good dies 103′ are disposed on the spacers 122 of the transparent substrate 120, a conductive bump can be formed on the exposed metal layer 110 of the good die 103′ in each of the package units. The conductive bump is configured for electrically connecting the good dies 103′ to the transparent substrate 120. Then, the transparent substrate 120 can be sawed so that the package units 121 are separated to form a number of individual packages. The steps of forming the conductive bump and sawing the substrate are known by the skilled in the art, and are not described here.
In addition, because the package method of the present invention is not base on a whole wafer to process the package, it is not necessary to use an apparatus having a packaging size identical to the size the wafer. In other words, the packaging method is not limited by the size of the wafer, and the method can use a variety of apparatuses with different packaging sizes to package the wafer.
In summary, the present invention has at least the following advantageousness:
1. The quality of the resulting package can be improved, the material can be saved, and the package cost can be reduced.
2. The method can use a variety of apparatuses with different packaging sizes to package the wafer, thereby enhancing package efficiency.
The above description is given by way of example, and not limitation. Given the above disclosure, one skilled in the art could devise variations that are within the scope and spirit of the invention disclosed herein, including configurations ways of the recessed portions and materials and/or designs of the attaching structures. Further, the various features of the embodiments disclosed herein can be used alone, or in varying combinations with each other and are not intended to be limited to the specific combination described herein. Thus, the scope of the claims is not to be limited by the illustrated embodiments.
