Claims
- 1. A method of manufacturing a semiconductor device, comprising the steps of:(a) providing a semiconductor chip and a lead frame, said semiconductor chip having bonding pads formed on a main surface thereof and a rear surface opposite to said main surface, said lead frame having a die pad, supporting leads continuously formed with said die pad and a plurality of leads each having an inner lead portion and an outer lead portion continuously formed with said inner lead portion, tips of said inner lead portions of said plurality of leads being disposed to surround said die pad in a plane view, said die pad having a size which is smaller than that of said semiconductor chip; (b) mounting said semiconductor chip on said die pad, such that said semiconductor chip is bonded to said die pad and said tips of said inner lead portions of said plurality of leads are disposed to surround said semiconductor chip; (c) electrically connecting said tips of said inner lead portions of said plurality of leads with said bonding pads of said semiconductor chip by a plurality of bonding wires respectively; (d) disposing said lead frame with said semiconductor chip in a mold die having an upper die and a lower die in such a manner that said semiconductor chip, said plurality of bonding wires and said die pad are disposed in a cavity defined by said upper and lower dies of said mold die at a boundary between said inner lead portion and said outer lead portion of each of said plurality of leads, said mold die having a gate portion for injecting a mold material into said cavity, said gate portion being formed at both sides of said upper die and said lower die; (e) injecting a resin into said cavity of said mold die from said gate portion of said mold die toward one side of said semiconductor chip by a transfer molding, thereby forming a resin member sealing said semiconductor chip, said plurality of bonding wires, said inner lead portions of said plurality of leads and said die pad by said resin member.
- 2. A method of manufacturing a semiconductor device according to claim 1, wherein each of said supporting leads has an inner portion and an outer portion which is continuously formed with said inner portion, wherein said supporting leads are clamped by said upper and lower dies of said mold die at a boundary between said inner and outer portions of each of said supporting leads in the step (d), and wherein said gate portion of said mold die is positioned at one of said supporting leads.
- 3. A method of manufacturing a semiconductor device according to claim 2, wherein said resin member is formed in a tetragonal shape, wherein said outer portions of said supporting leads protrude outwardly from said resin member at four corners of said resin member, and wherein said outer lead portions of said plurality of leads protrude outwardly from said resin member at four sides of said resin member.
- 4. A method of manufacturing a semiconductor device according to claim 3, wherein said gate portion of said mold die is positioned at one of said four corners of said resin member.
- 5. A method of manufacturing a semiconductor device according to claim 4, further comprising a step, after the step (e), of forming each of said outer lead portions of said plurality of leads in a gull wing shape for a surface-mounting on a printed circuit board.
- 6. A method of manufacturing a semiconductor device according to claim 5, further comprising a step, after the step (e), of cutting said supporting leads to separate said outer portions of said supporting leads at said boundary thereof.
- 7. A method of manufacturing a semiconductor device according to claim 1, wherein said rear surface of said semiconductor chip is bonded to a surface of said die pad by an adhesive in the step (b).
- 8. A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip includes a plurality of semiconductor elements.
Parent Case Info
This application is a Divisional application of application Ser. No. 09/331,721, filed Oct. 20, 1999 now U.S. Pat. No. 6,291,273, which is a national stage application filed under 35 USC 371 of PCT/JP96/03808, filed Dec. 26, 1996.
US Referenced Citations (13)
Foreign Referenced Citations (6)
Number |
Date |
Country |
63-204753 |
Aug 1988 |
JP |
63-228631 |
Sep 1988 |
JP |
2-9142 |
Jan 1990 |
JP |
6-132446 |
May 1994 |
JP |
6-216303 |
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8-204107 |
Aug 1996 |
JP |
Provisional Applications (1)
|
Number |
Date |
Country |
|
PCT/JP96/03808 |
Dec 1996 |
US |