Patent Grant
9449904
This invention relates to a technique for semiconductor devices and more particularly, to a technique effective for application to semiconductor devices having power MISFET (metal insulator semiconductor field effect transistor).
Transistors for high-power purposes dealing with electric power of several watts (W) or over are called power transistor, and various types of structures have been studied.
Among them, power MISFET includes ones called a longitudinal type and a transverse type and are classified into a trench-type structure and a planar structure depending on the structure of a gate portion.
Such power MISFET has a multitude of (e.g. several tens of thousands of) MISFET's in fine pattern connected in parallel in order to obtain high power.
For instance, Japanese Unexamined Patent Publication No. Hei 7(1995)-249770 discloses power MISFET of the trench gate type.
We have engaged in studies and developments of power MISFET used as a high-efficiency power supply and the like.
With such power MISFET as mentioned above, it is required to reduce an ON resistance (Ron), a gate capacitance (Qg) and, particularly, a gate-drain capacitance (Qgd) A great current can be obtained by reducing the ON resistance. The reduction of the capacitance between the gate and drain leads to an improved switching switching characteristic.
Under these circumstances, studies have been made on the scale down of power MISFET and, particularly, on the reduction in width of a groove where a gate portion is formed.
More particularly, in order to reduce the ON resistance, it is necessary to increase a channel area per unit area. If the width of the groove at which a gate portion is to be formed is made small, a channel area per unit area can be increased. If the width of the groove at which a gate portion is to be formed is made small, then a counter area for a drain portion at the side of a substrate opposite to the gate portion can be made small, thereby ensuring reduction of the capacitance (Qgd).
However, when the width of the groove where the gate portion is to be formed, the resistance of the gate portion becomes large, thereby causing the switching characteristic to be degraded instead.
Especially, in high frequency operations, an efficiency fi is greatly influenced depending on the resistance of the gate portion as will be hereinafter described in detail. This efficiency means a value of output power/input power.
Accordingly, a measure for reducing the resistance of the gate portion becomes important.
An object of the invention is to provide a semiconductor device of the type wherein the resistance of a gate portion of power MISFET is reduced.
Another object of the invention is to provide a semiconductor device of the type wherein a semiconductor device having power MISFET can be improved in characteristics.
The above and other objects and novel features of the invention will become apparent from the following description with reference to the accompanying drawings.
Typical embodiments of the invention among those embodiments set forth in this application are briefly described below.
A semiconductor device according to the invention comprises:
(a) a MISFET formed in a chip region of a semiconductor substrate and having a gate portion, a source portion and a drain portion, each made of a first conductor;
(b) a gate electrode which is electrically connected with the gate portion and is made of a second conductor having a resistivity lower than the first conductor and which includes (b1) a first portion formed along a periphery of the chip region and (b2) a second portion connected with the first portion and formed on the inside of said first portion in said chip region;
(c) a source electrode which is electrically connected with the source portion and is made of the second conductor and which is formed plurally within the chip region;
(d) a bump electrode formed on the upper portions of the gate electrode and the plurality of source electrodes, respectively;
(e) the gate electrode and the plurality of source electrodes being arranged at the same layer level; and
(f) the second portion of the gate electrode being arranged between adjacent source electrodes of the plurality of source electrodes.
The embodiments of the invention are described with reference to the accompanying drawings, in which like members or parts having a similar function are indicated by like reference numerals throughout the drawings illustrating the embodiments and are not repeatedly explained.
A semiconductor device according to this embodiment is described by way of a fabrication method thereof.
Initially, as shown in
Next, as shown in
Subsequently, as shown in
Next, as shown in
Next, the silicon oxide film 3 in the element forming region is removed and a thin silicon oxide film 13 is formed over the gate portion G and also over each portion between the grooves 7 as is particularly shown in
Next, an n-type impurity (e.g. arsenic) is injected into the substrate 1 at a portion between the grooves 7 through a mask of a resist film (not shown) and diffused to form an n+-type semiconductive region (source region) 17. It will be noted that this n′-type semiconductive region (source region) 17 extends between the gate portions G, shown in
This contact grove 21s is so arranged as to permit the n+-type semiconductive region 17 to be exposed from the side walls thereof and the p−-type semiconductive region 15 to be exposed from the bottom thereof. In other words, the depth of the contact groove 21s exceeds the n+-type semiconductive region 17 and arrives at the p−-type semiconductive region 15.
At this stage, the silicon oxide film 19 on the polysilicon film patterns P1 and P2 is removed to form contact grooves (gate contacts 21a, 21b) (see
The contact groove 21b is contacted at one end thereof (i.e. at a left end as viewed in
Next, as shown in
In this way, the contact groove 21s is formed and the p+-type semiconductive region 23 is formed at the bottom thereof, so that an allowance for mask alignment can be reduced and spaces between the gate portions can be made finer over the case where a device having such a structure as shown in
Next, according to a sputtering method, a TiW (titanium tungsten) film 25 is thinly deposited, for example, as a barrier film over the silicon oxide film 19 including the insides of the contact holes (21s, 21a, 21b), followed by thermal treatment. Subsequently, an aluminium (Al) film 27 is deposited, for example, as a conductive film according to a puttering method. This barrier film serves to prevent an undesirable reaction layer from being formed owing to the contact between Al and the substrate (Si). It will be noted that the Al film means a film mainly made of Al, and other types of metals may be contained therein.
Next, the TiW film 25 and the Al film 27 are, respectively, etched through a mask of a resist film not shown to form a gate electrode (gate leading electrode) GE and a source electrode (source leading electrode) SE. These electrodes (GE, DE) serve as a first-layer wiring.
As shown in
As shown in
It should be noted that any gate finger portion G2 is not formed on the space between the contact grooves 21a and 21b (space S1).
On the other hand, the source electrode SE is constituted, as shown in
It will be noted that the gate electrode GE and the source electrode SE are at the same layer level, and a guard ring (not shown) may be formed at the outside of the gate electrode GE for protection of the element.
Next, as shown in
Thereafter, the substrate 1 is protected such as with a tape on the surface thereof, after which the substrate 1 is polished at the back side thereof so that the protecting face is turned downside as shown in
Next, the tape is peeled off and a bump electrode made, for example, of gold or the like is formed at the openings 31g, 31s, respectively, followed by dicing the wafer-shaped substrate 1 along the chip region, packaging the resulting individual chips on a lead frame (packaging plate) and sealing (packaging) with a resin or the like. Eventually, a semiconductor device is completed. With respect to bump-forming and packaging procedures, these are described in detail in Embodiment 4 or the like and are not illustrated herein.
Thus, according to this embodiment, the gate finger portion G2 is disposed in the gate electrode GE, so that the gate resistance Rg can be reduced. As a result, switching characteristics can be improved.
Especially, because the gate-drain capacitance (Qgd) is reduced, the gate resistance can be reduced if the width of a groove where the gate portion is formed is made small (particularly, in the case where the groove is formed as a stripe). Thus, it becomes possible to reduce the gate-drain capacitance (Qgd), ensure high-speed switching operation due to the reduction of the gate resistance and reduce a switching loss.
Especially, where the groove pattern is formed as a stripe, it is possible to reduce the gate resistance according to this embodiment with the tendency that the gate resistance Rg increases in proportion to the pattern length of the groove over the case using a pattern of
Upon driving LSI, there is a tendency toward low voltage and great electric current. For instance, with CPU of a notebook computer, studies have been made to design a drive voltage at about 1.6V and an applied current at about 20 A. In addition, miniaturization of a notebook computer and the like has been greatly required, for which a working frequency (f) is in a high frequency range of from 300 kHz to 500 kHz. Studies on the breakdown of a loss of a synchronous rectifying circuit used as a power supply for notebook computers and constituted of power MISFET reveal that the sum of “on” loss and switching loss is at 50% or over. Accordingly, it will be seen that the reduction of these losses contributes greatly to high efficiency.
Accordingly, in power MISFET corresponding to a high frequency potential, it is convenient to use such a structure as stated in this embodiment.
It will be noted that extensive studies on the structure have been made wherein a gate finger portion G2 and the like are disposed, revealing that the gate resistance can be suppressed to 1Ω or below.
Upon comparison with an existing structure checked by the inventors (i.e. a structure having such a pattern of a groove 7 as shown in
In this manner, the gate resistance Rg can be reduced and thus, the efficiency can be improved.
It will be noted that the shape in pattern of the contact groove may be any one which allows the connection between the gate electrode GE and the gate portion G, and also between the source electrode SE and the n′-type semiconductive region 17 and should not be construed as limiting to the shape which has been illustrated with reference to
Although the polysilicon film is used as a gate portion in this embodiment, other types of films including a silicide film and a composite film of polysilicon and silicide may be likewise used.
Although the space S1 is provided between the contact groove 21a and 21b (see
It will be noted that because those other than the patterns of the contact grooves and the gate electrode GE and the source electrode SE are similar to in Embodiment 1, the structures of the respective members and procedures for forming same are not described herein.
The case where only one gate finger portion G2 is formed along the direction of X (see
It will be noted that contact grooves (21a, 21b) may be formed in the same pattern as the gate electrode GE.
In this way, an increase in number of the gate finger portions allows the gate resistance Rg to be efficiently reduced. Especially, it is preferred that where the gate portion G is elongated along the direction of Y correspondingly to the size of the chip region, the number of gate fingers is increased to reduce the gate resistance.
In
In this embodiment, the procedure of forming bump electrodes on the openings 31g, 31s illustrated in Embodiment 1 and mounting a chip is described.
Initially, a substrate 1 of the type, which has been described in Embodiment 1 with reference to
Reference numeral 37g indicates a bump electrode for connection with a gate electrode DE, and reference numeral 37s indicates a bump electrode for connection with a source electrode SE. These bump electrodes 37s, 37q can be formed, for example, by placing balls of molten gold over the openings 31g, 31s, respectively.
Next, the wafer-shaped substrate 1 is diced, for example in a rectangular form along the chip region.
Thereafter, as shown in
On the other hand, the chip CH has a lead frame R2 mounted on the surface side thereof, followed by thermocompression to permit the bump electrodes 37s, 37g and the lead frame R2 to be bonded together. The lead frame R2 has four external terminals R2a to R2d, of which the external terminals R2b to R2d are electrically connected to the bump 37s, respectively, and the external terminal R2a is electrically connected to the bump electrode 37g. More particularly, the external terminal Ra serves as a gate terminal GT and the external terminals R2b to R2d serve as a source terminal ST.
Subsequently, as shown in
According to this embodiment, because the connection with the external terminals R2a to R2d is established by use of the bump electrodes, the connection resistance between the source electrode SE or gate electrode GE and each of the external terminals R2a to R2d can be reduced.
For instance, although these connections are possible by use of a wire such as of a gold wire, the resistance of the gold wire and the inductance of a source or a gate undesirably increase.
If this inductance is great, (1) a transient induced voltage occurs. This voltage acts as a negative feedback relative to gate drive voltage and increases an ON resistance in the course of the period of transition. Moreover, 2) an impedance between source and drain increases, adversely influencing the transient characteristics under working conditions at a large electric current and at a high value of di/dt. Such problems as mentioned above are more frequently experienced as the frequency becomes higher.
In contrast, according to this embodiment, the inductance can be reduced, with an improved efficiency and improved device characteristics. It will be noted that as a result of the inventors' study, the device of this embodiment has an efficiency higher by about 1 to 2% than a package using a gold wire.
Especially, as described in detail in Embodiment 1, if the resistance Rg of the gate portion is reduced by trying various measures for the arrangement of the gate electrode and the source electrode, the reduction effect of the gate resistance Rg cannot be satisfactorily shown under high frequency working conditions in case where the resistance or inductance becomes large in association with external terminals.
Accordingly, the package form (or package structure) set forth in this embodiment may be one which is suitable for use in power MISFET set out in Embodiment 1 and the like. Of course, this package structure may be applicable to structures different from the power MISFET described in Embodiment 1.
In Embodiment 4, although the bump electrodes have been formed on the gate electrode GE and the like, a bump electrode may be formed after formation of a conductive film made, for example, of Al on the gate electrode GE as described below.
First, a substrate 1 of the type, which has been illustrated with reference to
Next, the Al film (33) is so patterned as to be larger in size than the openings 31g, 31s. Reference numeral 33g indicates an Al film over the opening 31g and reference numeral 33s indicates an Al film over the opening 31s.
Thereafter, bump electrodes 37g, 37s are, respectively, formed on the Al films 33g, 33s in the same manner as in Embodiment 4.
The wafer-shaped substrate 1 is diced and individual chips are packaged. These steps may be performed in the same manner as in Embodiment 4 and are not described again.
As will be apparent from the above, the Al films 33g, 33s are, respectively, formed below the bump electrodes 37g, 37s in addition to the Al film 27 constituting the gate electrode and the source electrode in accordance with this embodiment, so that stress exerted upon the formation of the bump electrodes 37g, 37s or upon the connection of the lead frames R1, R2 can be mitigated, thereby reducing a bonding damage.
With packaging using a so-called wire bonding technique, stress is exerted on chips only when wire bonding is performed. Accordingly, the need for applying the embodiment of the invention to the technique is not great. Nevertheless, the technique set out in this embodiment is important for the package using bump electrodes because stress is applied to not only at the time of formation of bump electrodes, but also at the time of connection (thermocompression) between the lead frame and the bump electrode, under which bonding damage is liable to occur.
This stress may be mitigated by forming a thick Al film (27) constituting the gate electrode and the source electrode. However, if the Al film is formed as being thick, a subsequent processing step (i.e. for the formation of gate and source electrodes) becomes difficult.
Especially, as illustrated in Embodiment 1 or the like, where the gate finger portion G2 is provided at the gate electrode GE, the pattern becomes complicated in shape, so that the procedure of this embodiment wherein the Al films are built up is appropriate.
The Al films 33g, 33s are formed only over the openings 33g, 33s, under which film stress exerted on the substrate can be mitigated. More particularly, when the forming areas of the Al films 33g, 33s are increased, film stress becomes great, causing the substrate to be strained or cracked.
In the power MISFET illustrated in Embodiment 1 or the like, a bump electrode is formed over the gate portion G and the gate portion G has a trench structure. In this case, stress is liable to be exerted on the upper end portion of the groove 7 shown in
Many tests (inspections) are usually conducted in the course of fabrication of semiconductor devices or after completion of the devices.
For instance, whether or not power MISFET works properly is inspected by applying a given potential to the gate electrode GE or source electrode SE that has been illustrated with reference to
This probe inspection may be carried out, for example, by bringing a probe into contact with the gate electrode GE and the source electrode SE exposed from the openings 31g, 31s shown in
If bump electrodes (37g, 37s) are formed on the probe traces, connection failure or the lowering of connection strength may be caused.
To avoid this, according to this embodiment, an opening 31p for probe inspection (or for measurement) is provided aside from the openings for bump electrodes (
In the MISFET of this embodiment, a pad for probe inspection is formed on a so-called active region in order to make effective use of the chip area. The term “on active region” means, for example, a region that is marked out with the silicon oxide film 3 formed beneath the gate electrode GE shown in
In contrast, a pad for probe inspection may be provided, for example, at a region other than the active region (e.g. a stripe region extending to around the active region or between the chip regions) However, such a region is very narrow, making it difficult to provide the pad for probe inspection. If a pad for probe inspection is provided in a peripheral region, the chip size becomes great, so that the number of chips obtained form one wafer is reduced. This eventually leads to higher manufacture costs.
The pattern of the opening 31p is in a rectangular (or oblong) form. The rectangle-shaped pattern permits easy contact of a probe and a reduced opening area. It should be noted that any bump electrode 31p is not formed over the opening 31p, which is covered, for example, with a resin 91.
As shown in
Accordingly, as illustrated in the above embodiment, where the gate finger portion G2 is provided or where connection with an external terminal through a bump electrode is intended, it is preferred to form an opening 31p for probe inspection.
As having illustrated in Embodiment 2, where the gate finger portion G2 and the gate electrode portion G1 formed along the periphery of the chip region CA are connected with each other over the space S1, it is favorable to form an opening 31p for probe inspection on individual halves obtained by division of the source electrode SE.
In this way, when the opening 31p for probe inspection is formed on each of the divided source electrode SE, element characteristics of the respective region can be accurately obtained.
On the contrary, where the patterns of the source electrode SE are integrally connected with each other, it is convenient to form an opening 31p for probe inspection in any of the regions and the probe inspection time (number of inspections) can be reduced.
In this embodiment, although the case where the electrode is divided into halves (
According to this embodiment, unlike the case shown in
It will be noted that this embodiment is applicable to a structure other than that of power MISFET set forth in Embodiment 1.
Although the invention made by us has been particularly described based on the embodiments, the invention should not be construed as limiting top these embodiments and many changes are possible without departing from the spirit of the invention.
Especially, in the foregoing embodiments, the case where the groove 7 is in a striped pattern has been set out. Besides, the groove may be formed in such patterns as shown in
The effects of typical embodiments disclosed in the present invention are briefly described below.
A gate finger (second portion) is provided at a gate electrode of power MISFET, so that the gate resistance can be reduced, thus leading to improved characteristics of semiconductor device.
The gate electrode and source electrode of power MISFET are connected to external terminals by use of bump electrodes, so that the characteristics of semiconductor device can be improved.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-211019 | Jul 2002 | JP | national |
This application is a continuation of application Ser. No. 10/458,668 filed Jun. 11, 2003.
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| Entry |
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| Office Action dated Nov. 13, 2012 issued in Japanese Patent Application No. 2010-164696. |
| Office Action dated May 7, 2013 issued in Japanese Patent Application No. 2010-164696. |
| Office Action dated Feb. 18, 2014 issue in Japanese Patent Application No. 2013-002229. |
| Office Action issued Dec. 16, 2014 in Japanese Patent Application No. 2014-085994 with English language translation. |
| Number | Date | Country | |
|---|---|---|---|
| 20150028400 A1 | Jan 2015 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10915416 | Aug 2004 | US |
| Child | 11180612 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13350438 | Jan 2012 | US |
| Child | 14514254 | US | |
| Parent | 12964651 | Dec 2010 | US |
| Child | 13350438 | US | |
| Parent | 12709260 | Feb 2010 | US |
| Child | 12964651 | US | |
| Parent | 11944343 | Nov 2007 | US |
| Child | 12709260 | US | |
| Parent | 11180612 | Jul 2005 | US |
| Child | 11944343 | US | |
| Parent | 10458668 | Jun 2003 | US |
| Child | 10915416 | US |
