Patent Application
20100053407
The subject matter shown and described in the present application relates to microelectronic image sensors and methods of fabricating, e.g., microelectronic image sensors.
Solid state image sensors, e.g. charge-coupled devices, (“CCD”) arrays, have a myriad of applications. For instance, they may be used to capture images in digital cameras, camcorders, cameras of cell phones and the like. One or more light-sensing elements on a chip, along with the necessary electronics are used to capture a “pixel” or a picture element, a basic unit of an image.
Improvements can be made to the structure of solid state image sensors and the processes used to fabricate them.
In accordance with one embodiment, a solid state image sensor can include a microelectronic element having a front face and a rear face remote from the front face. The rear face can have a surface a first distance from the front surface in a direction normal to the front surface. A plurality of light sensing elements may be disposed adjacent to the front face and be aligned with the surface of the rear face so as to receive light through that surface.
In accordance with one embodiment, a solid state image sensor can include a microelectronic element having a front face, a plurality of chip contacts at the front face, and a rear face remote from the front face. A plurality of light sensing elements can be disposed adjacent to the front face, and may be conductively connected with the chip contacts. The light sensing elements may be arranged to receive light through the rear face. An insulating packaging layer can overlie and be attached to the front face and can include a compliant layer. Electrically conductive package contacts can directly overlie the front face and the light sensing elements. Conductors can extend within openings in the packaging layer from the chip contacts to the package contacts. The package contents, in turn, can be bonded to terminals of a circuit panel, such that the package contacts are subject to external loads applied by the terminals of the circuit panel. With the package contacts disposed on the compliant layer, the package contacts may be movable with respect to the chip contacts under external loads applied to the package contacts, For example, differential thermal expansion between a circuit panel and the chip can cause the terminals of the circuit panel to apply loads to the package contacts, which in turn, can cause the package contacts to move relative to the chip or the chip contacts.
The light sensing elements can include active semiconductor devices disposed adjacent to the front face. The conductors can include vertical interconnects in conductive communication with the active semiconductor devices and the package contacts.
In one embodiment, chip contacts can be exposed within the openings. The image sensor may include leads extending along interior surfaces of the openings which conductively connect the chip contacts with the package contacts. Each lead may cover an entire exposed interior surface of each opening or less than an entire exposed interior surface of each opening.
In one embodiment, each lead may extend along only a portion of an interior wall of each opening. For example, a second portion of the wall of the vertical interconnect remote from the first portion can remain uncovered by the lead.
In one embodiment, the light sensing elements can be disposed in a first region of the microelectronic element and the chip contacts can be disposed in a second region laterally adjacent to the first region, wherein the leads extend from the chip contacts to locations overlying the first region. The second region can be disposed between the first region and an edge of the microelectronic element.
The package contacts may be spaced farther apart than the chip contacts. The chip contacts may be disposed in at least a first direction along the front surface. The chip contacts may have a first pitch in the first direction and the package contacts may have a second pitch in the first direction. In one embodiment, the second pitch can be substantially greater than the first pitch.
In a particular embodiment, the package contacts can include one or the other of conductive masses and lands, or both. In such embodiment, the lands may be wettable by a fusible metal.
The image sensor may include a cover slip adjacent to the rear face. The image sensor may include an integrated stack lens disposed adjacent to the rear face.
In yet another embodiment of the present invention, a method of packaging a microelectronic image sensor includes (a) recessing portions of a rear surface of a device wafer, the portions being aligned with a plurality of light sensing elements adjacent to a front surface of the device wafer, (b) forming package contacts conductively interconnected with chip contacts exposed at the front surface, (c) assembling the device wafer with a light transmissive structure overlying the rear surface, and (d) severing the device wafer into individual packaged chips, each containing light sensing elements arranged to receive light through at least one of the recessed portions.
In an embodiment of the present invention, a wafer level package assembly is disclosed having a backside illuminated image sensor. U.S. Pat. No. 6,646,289, which is hereby incorporated by reference, discloses integrated circuit devices employing a thin silicon substrate. Optronic components are formed on a surface facing away from a corresponding transparent protective layer.
As discussed in the '289 patent, the thinness of the silicon allows for the optronic components to be exposed to light impinging via the transparent protective layer. Color filters may be formed on an inner surface of the protective layer. Further, an array of microlenses may also be disposed on an inner surface of the protective layer.
A method of fabricating a rear-face illuminated image sensor will now be described with reference to sectional views illustrating respective stages of fabrication in
As used in this disclosure, terms such as “top”, “bottom”, “upward” or “upwardly” and “downward” or “downwardly” refer to the frame of reference of the microelectronic element, e.g., semiconductor wafer or chip, or an assembly or unit which incorporates such wafer or chip. These terms do not refer to the normal gravitational frame of reference. For ease of reference, directions are stated in this disclosure with reference to a “top” or “front”, i.e., contact-bearing surface 13 of a semiconductor wafer or chip 10A. Generally, directions referred to as “upward” or “rising from” shall refer to the direction orthogonal and away from the chip top surface 13. Directions referred to as “downward” shall refer to the directions orthogonal to the chip top surface 13 and opposite the upward direction. A “vertical” direction shall refer to a direction orthogonal to the chip top surface. The term “above” a reference point shall refer to a point upward of the reference point, and the term “below” a reference point shall refer to a point downward of the reference point. The “top” of any individual element shall refer to the point or points of that element which extend furthest in the upward direction, and the term “bottom” of any element shall refer to the point or points of that element which extend furthest in the downward direction.
As used in this disclosure, a statement that an electrically conductive structure is “exposed at” a surface of a dielectric structure indicates that the electrically conductive structure is available for contact with a theoretical point moving in a direction perpendicular to the surface of the dielectric structure toward the surface of the dielectric structure from outside the dielectric structure. Thus, a terminal or other conductive structure which is exposed at a surface of a dielectric structure may project from such surface; may be flush with such surface; or may be recessed relative to such surface and exposed through a hole or depression in the dielectric.
As seen in
Photolithography may be used to form mask patterns 16 overlying a rear surface 15 of the wafer, after which the wafer 10 may be etched from a rear surface 15 thereof using wet or dry etching as desired, as shown in
In addition, the transmissivity of the semiconductor material to light, especially silicon, can be limited. The distance d2 can be the same as the maximum thickness of the wafer in the normal direction 21. In an exemplary embodiment, the distance d2 and the maximum thickness of the device wafer 10 can range from about 50 microns to several hundred microns.
An anti-reflective coating (not specifically shown in
Sets of microlenses 20 may then be formed which overlie an exposed surface of the array of color filters 28. The microlenses 20 include tiny bumps of refractive material arranged in an array which help to focus light on one or more picture elements (“pixels”) of the imaging sensor. Each pixel typically is defined by an array of light-sensing elements, such that the light which arrives at the exposed surface 20A of each microlens is directed primarily onto one or more corresponding pixels.
As further illustrated in
After mounting the lid wafer 22 to the device wafer 10, the wafer may then be severed along the dicing lanes 25 into individual regions or dies 10A (
In an alternative embodiment, the device wafer 10 is not assembled with an intact lid wafer 22 in a wafer level assembly process. Rather, individual lids 22A can be mounted to the outer surfaces 15A of individual regions 11 of the intact device wafer 10, such as via pick-and-place techniques. Then, the device wafer 10 with the individual lids mounted thereon is severed into individual chips, each having an attached lid. In another alternative embodiment, an individual lid 22A can be mounted to an individual die 10A after the device wafer 10 has been singulated into individual dies.
As also illustrated in
Solder bumps 30 or other raised conductive features can be formed which extend from the bond pad extensions 27 in a direction downwardly away from the front surface 13. For example, the conductive features can include solder balls 30 attached to the extensions 27 in form of a ball grid array (“BGA”) or other arrangement. A solder mask or other dielectric layer 28 overlying the front surface 13 can avoid solder or other fusible metal used to mount the packaged die 11A from flowing in directions along the front surface of the packaged die 11A. The dielectric layer 28 may form a layer which encapsulates the original contacts 12 and the image sensor 14 at the front surface 13. The dielectric layer 28 or solder mask can be a photoimageable layer which can be deposited in liquid form by a spin-on or spray-on technique, followed by photolithographic patterning to form openings exposing at least portions of the pads 27 to which the.
It is to be noted that, in one embodiment, the above-described packaging processes (
The rear face illuminated configuration of the packaged die 11A achieves a standoff height 24 between the image sensor 14 and the inner surface 42 of the lid 22A. As seen in
Another advantage is that the foregoing-described processes for forming packaged dies can be performed without requiring a handler wafer to be mounted to the device wafer during such processing. Still another advantage is that, with the recesses being made in the rear surface in alignment with the image sensors, processes such as grinding or polishing may not need to be performed to reduce the total thickness of the device wafer 10. Still another advantage is the ability to use wafer-level chip-scale packaging technology to form the packaged dies by the above-described processes.
In a variation (
A compliant layer can reduce stresses placed on the pads 127 and solder bumps by allowing the pads 127 and bumps 30 thereon to move relative to the surface 19 of the chip under the influence of external loads applied to the bumps 30, such as through their connections with terminals 131 of a circuit panel. The chip 14 and the circuit panel 133 can have different linear coefficients of thermal expansion (“CTE”). For example, a chip consisting essentially of silicon has a CTE of about 3 ppm/° K, whereas an epoxy-glass printed circuit board of type FR-4 can have a CTE of about 10-15 ppm/° K. The compliant layer can reduce stresses that result from differential thermal expansion between the chip 14 and the circuit panel 133. For example, the compliant layer can reduce stresses that result from the chip 14 heating up to an operating temperature, given the difference in CTE between the chip and the circuit panel, by allowing the package contacts 127 to move relative to the chip contacts 12 under the influence of the loads applied from the circuit panel terminals 131.
The compliant layer 129 can be made of various materials such as, but not limited to, silicone, polyimide, flexibilized epoxy, liquid crystal polymer material, etc. The compliant layer can be a photoimageable or a non-photoimageable layer. In a particular embodiment, the compliant layer can be relatively thin. For example, the compliant layer can have a thickness ranging from 10 micrometers (microns or μm) and up.
In a particular embodiment, the temperature at which the compliant layer is curable should be higher than the temperature at which subsequent processes are performed. For example, the temperature required for curing the microlens array 20 may be between 100° C. and 250° C., or more typically between 150° C. and 200° C. In practice, the actual curing temperature or temperature range may depend upon a number of variables, such as the particular material used, the desired lens shape, etc. In one example, when formed prior to the microlens array, the compliant layer 129 can have a glass transition temperature Tg which is higher than the temperature at which the microlens array is fabricated.
Referring to
A temporary carrier, e.g., a handler wafer 94 is laminated onto the device wafer 90, as shown in
Thereafter, the device wafer 90 is thinned from a rear face 136 of the wafer until a desired thickness 138 is reached between the front face 36 and the rear face 38, as shown in
Color masks (not shown), e.g., sets of color filters as described above, microlenses 96, or both can be applied on the device wafer 90 at a rear surface 38 as shown in
Next, a lid wafer or “coverslip” wafer 98 is prepared which has standoffs 99 thereon. The standoffs 99 may take the form of a patterned adhesive layer projecting from an inwardly directed inner surface 88 of the coverslip wafer, as shown in
Thereafter, as shown in
Alternatively, the dielectric layer 104 can be formed on the device wafer front surface and subsequently patterned by photolithography, or other technique such as, without limitation, laser or mechanical drilling. In one example, the dielectric layer can be deposited by a spin-on or spray-on technique.
In another example, the dielectric layer can be formed of a material such as an epoxy or an epoxy-glass substrate e.g., an FR-4 board, which is subsequently patterned. If it is desired for the dielectric layer 104 to be compliant, a compliant epoxy dielectric material can be used. If the material of the dielectric layer, e.g., FR-4 board is not sufficiently compliant, another layer, e.g., of polyimide, silicone or other material can be provided thereon to provide compliancy for traces and terminals which will be subsequently formed thereon.
In yet another embodiment, the dielectric layer can include a liquid crystal polymer (“LCP”) layer to provide compliancy. In one example, such layer can be attached to the device wafer 90 in an unpatterned condition and subsequently patterned to form through holes 107.
Thereafter, as seen in
As best seen in
Alternatively, without requiring 3-D lithography, portions of the seed metal layer which overlie the top surface 116 of the dielectric layer can be patterned and the seed layer along entire walls 130 of the through holes 107 can remain intact. In this way, the inner walls 130 of the through holes are plated to form a layer 110A which covers interior walls 130 of the holes 107, as seen in
Optionally, a conductive barrier layer may be provided adjacent to the surfaces of the dielectric layer. In one example, leads 110 can be formed which have layers starting with a layer of aluminum, then nickel, then copper (Al/Ni/Cu) and then a finish layer such as gold (Au). In another example, the leads 110 can be formed which have layers starting with a layer of titanium, then copper, then nickel, and then a finish layer such as gold (Ti/Cu/Ni/Au). In yet another example, the leads 110 can be formed which have layers starting with a layer of nickel, then palladium, then a finish layer such as gold (Ni/Pd/Au). In another example, the leads 110 can be formed which have layers starting with a layer of aluminum, then nickel, and then a finish layer such as gold (Al/Ni/Au).
In a particular embodiment of the invention, the dielectric layer 104 is not a pre-formed layer which is then laminated onto the wafer-level assembly. In such case, the dielectric 104 can be deposited using electrophoretic deposition, spin-on, spray on, roller-coating or other deposition method.
Interconnections 110, which extend upward from the front surface of the chip and laterally along a surface of layer 104 connect the peripheral bonding pads or chip contacts 106 of each chip to an area array of package contacts 108. The package contacts, 108, which may include under bump metal (UBM) pads and solder bumps or balls, can be distributed over the front surface of the chip. In one embodiment, a seed layer for forming the interconnections 110 can be formed on an exposed major surface 116 and exposed wall surfaces 130 of the holes, such as by sputtering or electrolessly depositing a metal layer thereon. Thereafter, the seed layer can be patterned by photolithography, after which the interconnections 110 can be formed, such as by electroplating one or more layers of metal thereon such as described above.
Alternatively, package contacts can be in the form of conductive masses, lands or the like. The lands may be wettable by a fusible metal such as solder, tin or a eutectic composition including a fusible metal.
The dotted line in
The above-discussed method of forming redistributed package contacts can improve the reliability by allowing the use of larger solder balls for robust interconnection and better thermal management of the device's input output (“I/O”) system.
Further, this type of structure is advantageous because chip contacts 106 are commonly placed very closely together. For instance, the pitch of the chip contacts is usually very small, whereas the pitch of the package contacts is normally substantially greater than the pitch of the chip contacts. Substantially greater can be defined such that the ratio of the pitch of the package contacts and the pitch of the chip contacts is greater than 1.2. The ratio may be much greater than 1.2 and 2.0. Redistribution also allows for package contacts 108 to be spaced further apart than chip contacts 106 and allows the package contacts to be larger in size.
Some or all of the methods and processes described in the foregoing may be performed via chip level packaging techniques with respect to individual chips as well as wafer level packaging techniques as described above. Further, the methods recited herein are applicable to solid state image sensors as well as other types of sensors.
Reference is now made to
Turning to
The thermal expansion characteristics of the packaging layer 610 can be closely matched to those of the semiconductor wafer 600. For example, if the semiconductor wafer 100 is made of silicon, which has a coefficient of thermal expansion of 2.6 μm·m−1·K−1 at 25° C., the packaging layer 610 can be selected so as to have a similar coefficient of thermal expansion. Furthermore, the adhesive 612 can have a coefficient of thermal expansion which is matched to the coefficients of thermal expansion of the semiconductor wafer 600 and of the packaging layer 610 or is compatible therewith. Also, in one example, when the semiconductor wafer 600 consists essentially of silicon, the packaging layer 610 may also consist essentially of silicon having sufficient conductivity to permit electrophoretic coating thereof.
After the wafer 600 is joined with the packaging layer 610, the above-described processing (
Turning to
In one example, the compliant layer 622 can be formed by electrophoretic deposition. Electrophoretic deposition can be utilized to form a compliant dielectric layer as a conformal coating that is deposited only onto exposed conductive and/or semiconductive surfaces of the assembly. Electrophoretically deposited coating is self-limiting in that after it reaches a certain thickness governed by parameters, e.g., voltage, concentration, etc. of its deposition, the deposition stops. Electrophoretic deposition forms a continuous and uniformly thick conformal coating on conductive and/or semiconductive exterior surfaces of the assembly. In addition, the electrophoretically deposited coating typically does not form on surfaces of existing insulating (dielectric) layers of the assembly, due to their dielectric (i.e., nonconductive) property. The electrophoretically deposited compliant layer can be formed from a cathodic epoxy deposition precursor. Alternatively, in another example, a polyurethane or acrylic deposition precursor could be used. Examples of electrophoretic coating materials that form compliant layers include Powercron 645 and Powercron 648, both commercially available from PPG of Pittsburgh, Pa., USA; Cathoguard 325, commercially available from BASF of Southfield, Mass., USA; Electrolac, commercially available from Macdermid of Waterbury, Conn., USA and Lectraseal DV494 and Lectrobase 101, both commercially available from LVH Coatings of Birmingham, UK.
Once cured, the compliant layer 622 encapsulates all exposed surfaces of the packaging layer 610. Compliant layer 622 may also provide protection to the device from alpha particles emitted by BGA solder balls.
As shown in
Then, similar to that described relative to
Reference is now made to
The notch 650 exposes a row of bond pads 654, corresponding to bond pads 608 (
Patterned metal connections 662, corresponding to metal connections 632 (
In a variation of the above-described embodiment, the packaging layer can be a material other than a semiconductor, e.g., silicon. For example, the packaging layer can be made of glass. In such case, the packaging layer is a dielectric material. In that case, the compliant layer can be formed by a technique other than electrophoretic coating. For example, the compliant layer can be deposited by a spin-on or spray-on technique. After forming the compliant layer by such technique, some or all of the compliant material within the notches in the packaging layer can be removed by subsequent patterning, e.g., laser or mechanical drilling.
In another example, the packaging layer can be formed of a material such as an epoxy or an epoxy-glass substrate e.g., an FR-4 board, which is subsequently patterned. On such epoxy layer, if it is not sufficiently compliant, another layer, e.g., polyimide, silicone or other material can be provided thereon to provide compliancy for traces and terminals which are formed thereon.
In yet another embodiment, the packaging layer can include a liquid crystal polymer (“LCP”) layer to provide compliancy. In one example, such layer can be attached to the device wafer 600 in unpatterned condition and subsequently patterned to form notches, after which traces and terminals can be formed thereon. In this case, processing steps similar to that described above with respect to
In one variation of the above-described embodiments, conductive elements, e.g., traces, pads, etc., between the bond pads on the wafer and the terminals at a face of the package can be formed by a different technique similar to that used in the fabrication of printed circuit boards. For example, a dielectric material, e.g., an epoxy-glass composite such as an FR-4 layer can be used as the packaging layer which can then be roughened by a pre-treatment process, after which a continuous metal layer can be formed thereon such as by electroplating. Thereafter, the continuous metal layer can be subtractively patterned by photolithography to form the conductive elements.
The above-described embodiments have shown packaged image sensors which have solder bump terminals 30 (
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
This application is a continuation-in-part of U.S. patent application Ser. No. 12/393,233 filed Feb. 26, 2009′. Said application claims the benefit of the filing date of U.S. Provisional Patent Application No. 61/067,209 filed Feb. 26, 2008, the disclosure of which is hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61067209 | Feb 2008 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12393233 | Feb 2009 | US |
| Child | 12583830 | US |
