Patent Grant
10535763
This invention relates to semiconductor electronic devices, specifically devices with electrodes connected to field plates.
Most power semiconductor devices such as high-voltage P-I-N diodes and power transistors such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBT) have been typically fabricated with silicon (Si) semiconductor materials. More recently, silicon carbide (SiC) power devices have been used due to their superior properties. III-Nitride (III-N) semiconductor devices are emerging as an attractive candidate to carry large currents and support high voltages, and provide very low on resistance, high voltage operation, and fast switching times. As used herein, the terms III-N or III-Nitride materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula BwAlxInyGazN, where w+x+y+z is about 1.
Examples of III-N high electron mobility transistors (HEMTs) of the prior art are shown in
Field plates are commonly used in III-N devices to shape the electric field in the high-field region of the device in such a way that reduces the peak electric field and increases the device breakdown voltage, thereby allowing for higher voltage operation. An example of a field plated III-N HEMT of the prior art is shown in
Slant field plates have been shown to be particularly effective in reducing the peak electric field and increasing the breakdown voltage in III-N devices. A prior art III-N device similar to that of
Slant field plates, such as field plate 24 in
The III-N HEMTs shown in
Reliable fabrication and manufacturing of high-voltage III-N E-mode devices has thus far proven to be very difficult. One prior art alternative to a single high-voltage III-N E-mode device is to combine a high-voltage III-N D-mode device with a low-voltage silicon-based E-mode device in the configuration of
In a first aspect, a III-N device is described. The III-N device comprises a III-N enhancement-mode transistor including a source contact and a first gate, the first gate being on a gate insulator, and a III-N depletion-mode transistor including a drain contact. The III-N device also includes a III-N structure including a conductive channel, where a first portion of the conductive channel serves as a device channel of the III-N enhancement-mode transistor, and a second portion of the conductive channel serves as a device channel of the III-N depletion-mode transistor. The III-N device further includes an insulator layer over the III-N structure, where a first recess is formed through the insulator layer in a gate region of the III-N enhancement-mode transistor, and the gate insulator and the first gate are at least partially in the recess. The III-N device also includes an electrode-defining layer having a thickness, the electrode-defining layer being over the insulator layer, with a second recess being formed in the electrode-defining layer in a gate region of the III-N depletion-mode transistor, the second recess including a sidewall proximal to the drain contact. The III-N device further includes an electrode in the second recess, the electrode including a second gate of the III-N depletion-mode transistor and an extending portion, the second gate being in a gate region of the III-N depletion-mode transistor, and the extending portion being at least partially over the sidewall. Additionally, the electrode is electrically connected to the source contact.
In a second aspect, a III-N enhancement-mode transistor is described. The transistor comprises a III-N structure including a conductive channel therein, a source contact and a drain contact, the source and drain contacts electrically contacting the conductive channel, and a gate electrode positioned between the source and drain contacts. The transistor also includes an insulator layer over the III-N structure, where a recess is formed through the insulator layer in a gate region of the III-N enhancement-mode transistor, and the gate electrode is at least partially in the recess. The transistor further includes a field plate having a portion that is between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact, and a separation between the conductive channel and the extending portion of the gate electrode is greater than a separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.
In a third aspect, another enhancement-mode transistor is described. The transistor comprises a semiconductor material structure including a conductive channel therein, and a source contact and a drain contact, with the source and drain contacts electrically contacting the conductive channel. The transistor also includes a gate electrode positioned between the source and drain contacts, a field plate that is electrically connected to the source contact, and a diode, with a first side of the diode electrically connected to the field plate.
In a fourth aspect, a half bridge is described. The half bridge comprises a III-N structure including a conductive channel therein, and a first gate electrode and a second gate electrode, the first and second gate electrodes being on the III-N structure. The half bridge also includes a first source contact and a drain contact, the first source contact and the drain contact electrically contacting the conductive channel, and the first and second gate electrodes are both between the first source contact and the drain contact. The half bridge further includes a second source contact, the second source contact including a first portion electrically contacting the conductive channel, wherein the first portion of the second source contact is between the first gate electrode and the second gate electrode. Additionally, the first source contact is part of a first electrode and the second source contact is part of a second electrode, the first electrode including a portion which is between the first gate electrode and the second source contact, and the second electrode including a portion that is between the second gate electrode and the drain contact.
In a fifth aspect, a bidirectional switch is described. The bidirectional switch comprises a III-N structure including a conductive channel therein, and a first gate electrode and a second gate electrode, the first and second gate electrodes being on the III-N structure. The bidirectional switch also includes a first source contact and a second source contact, the first source and second source contacts electrically contacting the conductive channel, where the first and second gate electrodes are each between the first and second source contacts. Furthermore, the first source contact is part of a first electrode and the second source contact is part of a second electrode, the first electrode including a first portion which is between the first and second gate electrodes, and the second electrode including a second portion that is between the first and second gate electrodes.
Each of the devices, transistors, half bridges, and bidirectional switches described herein can include one or more of the following features. A portion of the second recess distal from the III-N structure can have a first width and a portion of the second recess proximal to the III-N structure can have a second width, the first width being larger than the second width. A breakdown voltage of the III-N depletion-mode transistor can be at least 3 times a breakdown voltage of the III-N enhancement-mode transistor. The device can be configured to function as an enhancement-mode transistor having a breakdown voltage which is at least 3 times the breakdown voltage of the III-N enhancement-mode transistor. The electrode-defining layer can be over both the device channel of the III-N enhancement-mode transistor and the device channel of the III-N depletion-mode transistor. The first gate can include an extending portion that is outside the first recess and extends towards the drain contact. A separation between the conductive channel and the extending portion of the first gate can be greater than a separation between the conductive channel and the second gate. The first recess can extend into the III-N structure. The first recess can extend through the conductive channel.
The III-N structure can comprise a first III-N layer and a second III-N layer, wherein the conductive channel is a 2DEG channel induced in the first III-N layer adjacent to the second III-N layer as a result of a compositional difference between the first III-N layer and the second III-N layer. The second recess can extend completely through the thickness of the electrode-defining layer. The electrode-defining layer can comprise SiNx. The device can further include an additional dielectric layer between the insulator layer and the electrode-defining layer. The additional dielectric layer can comprise AlN, and the insulator layer can comprise SiN. The sidewall can include a plurality of steps. The device can further comprise an additional contact between the first gate and the second gate, the additional contact contacting the conductive channel. The device can further comprise a current-carrying component, wherein a first side of the current-carrying component is electrically connected to the source contact and a second side of the current-carrying component is electrically connected to the additional contact. The current-carrying component can comprise a diode, with the first side of the current-carrying component being an anode, and the second side of the current-carrying component being a cathode. The current-carrying component can comprise a resistor. The III-N enhancement-mode transistor can lack a drain contact, the III-N depletion-mode transistor can lack a source contact, and the III-N enhancement-mode transistor and III-N depletion-mode transistor can share a common drift region between the first gate and the second gate.
The device can further comprise an additional contact between the gate electrode and the drain electrode. The additional contact can electrically contact the conductive channel. The device can further comprise a diode, wherein a first side of the diode is electrically connected to the field plate and a second side of the diode is electrically connected to the additional contact. The first side of the diode can be an anode and the second side of the diode can be a cathode. The semiconductor material structure can comprise one or more III-Nitride layers, with the conductive channel in the one or more III-Nitride layers. The device can further comprise an additional contact between the gate electrode and the drain electrode. The additional contact can electrically contact the conductive channel. A second side of the diode can be electrically connected to the additional contact. The gate electrode can include a main gate portion and an extending portion, the extending portion extending from the main gate portion towards the drain contact, the field plate can include a portion which is between the extending portion and the drain contact, and a separation between the conductive channel and the extending portion of the gate electrode can be greater than a separation between the conductive channel and the portion of the field plate which is between the extending portion and the drain contact.
The device or half bridge can further comprise an additional contact between the first gate electrode and the drain contact, as well as a diode having an anode and a cathode, wherein the anode is electrically connected to the first electrode or to the second electrode, and the cathode is electrically connected to the additional contact. The additional contact can electrically contact the conductive channel. The first gate can be part of a first III-N switch and the second gate can be part of a second III-N switch. The half bridge or device can further comprise an additional contact between the first gate electrode and the second source contact, as well as a diode having an anode and a cathode, wherein the anode is electrically connected to the first electrode and the cathode is electrically connected to the additional contact. A reverse bias breakdown voltage of the diode can be smaller than a breakdown voltage of the first III-N switch. The reverse bias breakdown voltage of the diode can be less than 0.5 times the breakdown voltage of the first III-N switch. The second electrode can be configured to operate as a drain of the first III-N switch.
The first gate electrode can include a main gate portion and an extending portion, the extending portion can extend from the main gate portion towards the drain contact, and a separation between the conductive channel and the extending portion of the first gate electrode can be greater than a separation between the conductive channel and the portion of the first electrode which is between the first gate electrode and the second source contact. The half bridge can further comprise an insulating material over the III-N structure, the insulating material including a first recess and a second recess, wherein the portion of the first electrode which is between the first gate electrode and the second source contact is in the first recess, and the portion of the second electrode which is between the second gate electrode and the drain contact is in the second recess.
The bidirectional switch or device can further comprise a first additional contact between the first gate electrode and the second gate electrode, as well as a first diode having an first anode and a first cathode, wherein the first anode is electrically connected to the first electrode and the first cathode is electrically connected to the first additional contact. The additional contact can electrically contact the conductive channel. The bidirectional switch or device can further comprise a second additional contact between the first gate and second gate electrodes and a second diode having a second anode and a second cathode, wherein the second anode is electrically connected to the second electrode and the second cathode is electrically connected to the second additional contact. A reverse bias breakdown voltage of the diode can be smaller than a breakdown voltage of the device or bidirectional switch. The reverse bias breakdown voltage of the diode can be less than 0.3 times the breakdown voltage of the device or bidirectional switch.
The first gate electrode can include a main gate portion and an extending portion, the extending portion extending from the main gate portion towards the second gate electrode, wherein a separation between the conductive channel and the extending portion of the first gate electrode is greater than a separation between the conductive channel and the first portion of the first electrode. The bidirectional switch or device can further comprise an insulating material over the III-N structure, the insulating material including a first recess and a second recess, wherein the first portion of the first electrode is in the first recess, and the second portion of the second electrode is in the second recess.
III-N devices which can be fabricated reproducibly, can support high voltages with low leakage, and at the same time can exhibit low on-resistance and high breakdown voltage, are described. Methods of forming the devices are also described. The III-N devices described herein can be transistors, half bridges, and/or bidirectional switches, and can be high-voltage devices suitable for high voltage applications. The details of one or more implementations of the invention are set forth in the accompanying drawings and description below. Other features and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.
Devices based on III-N heterostructures are described. The III-N devices are designed to operate as enhancement-mode transistor devices. The III-N devices described herein can be high-voltage devices suitable for high voltage applications. In such a high-voltage device, when the device is biased off (i.e., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which the device is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, or higher. When the high voltage device is biased on (i.e., the voltage on the gate relative to the source is greater than the device threshold voltage), it is able to conduct substantial current with a low on-voltage. The maximum allowable on-voltage is the maximum voltage that can be sustained in the application in which the device is used.
Implementations of the device described herein are illustrated in
Enhancement-mode transistor 41 additionally includes source and drain contacts 34 and 35, respectively, which form ohmic contacts to the 2DEG 19, and a gate contact 38 formed on a gate insulator 37. The gate of the enhancement-mode transistor 41 is formed as follows. After depositing insulator layer 22 over III-N layer 12, a recess is etched through insulator layer 22 and into the III-N materials in the gate region 61 of the enhancement-mode transistor 41. As shown in
A gate insulator 37 is then conformally deposited in the gate region 61 and over the entire upper surface of insulator layer 22. Gate insulator 37 can, for example, be formed of or include aluminum oxide, silicon dioxide, or another wide bandgap insulator. Next, the gate contact 38 is deposited conformally over gate insulator 37 in the recess in gate region 61. The gate contact 38 includes extending portions 31 and 32 that extend towards the source 34 and drain 35 contacts, respectively. The extending portions 31 and 32 are in the source and drain access regions 62 and 63, respectively, of the enhancement-mode transistor 41, and are over the upper surface of both gate insulator 37 and insulator layer 22. Extending portion 32 functions as a field plate for the enhancement-mode transistor 41. In implementations where the sidewalls of the recess in which layers 37 and 38 are deposited are slanted, extending portion 32 functions as a slant field plate, which may improve device performance. Finally, the gate contact 38 is used as an etch mask to etch gate insulator 37, such that gate insulator 37 remains directly beneath gate contact 38 but is etched away everywhere else.
Referring now to the high-voltage depletion-mode transistor 42 of hybrid device 40, depletion-mode transistor 42 includes source and drain contacts 44 and 45, respectively, which form ohmic contacts to the 2DEG 19. Depletion-mode transistor 42 also includes an electrode 49 which is deposited in a recess 17 in an electrode-defining layer 33 which is formed over the III-N material layers 11 and 12. The recess 17 can extend through the entire thickness of the electrode-defining layer 33, as shown in
The electrode-defining layer 33 is typically between about 0.1 microns and 5 microns thick, such as about 0.85 microns thick. The electrode-defining layer 33 can have a composition that is substantially uniform throughout. The electrode-defining layer 33 is formed of an insulator, such as silicon nitride (SiNx).
As described above, electrode 49 is formed in the recess 17. In the implementation shown in
Source and drain contacts 44 and 45, respectively, are on opposite sides of the gate 48. The depletion-mode transistor 42 also includes a gate region 51, in which the gate 48 is deposited, and source and drain access regions 52 and 53, respectively, on opposite sides of the gate region. The regions 56 of the device structure in which the source and drain contacts 44 and 45, respectively, are deposited are referred to as the device ohmic regions. The source access region 52 is between the source contact 44 and gate 48, and the drain access region 53 is between the drain contact 45 and gate 48.
The depletion-mode transistor 42 optionally includes an additional dielectric layer 21 between the electrode-defining layer 33 and the insulator layer 22. The additional dielectric layer 21, which can be formed of an insulator such as AlN, can serve as an etch stop layer during the formation of the recess 17, as further described below. As seen in
In order for hybrid device 40 to operate as a high-voltage enhancement-mode device, transistors 41 and 42 are connected in the circuit configuration shown in
In some implementations, in order to provide stability to the device and/or to improve reliability, a current-carrying component 39 (shown in
Alternatively, current-carrying component 39 could be included to allow off-state leakage currents in the enhancement-mode transistor 41 to be better matched to off-state leakage currents in the depletion-mode transistor 42. In this case, current-carrying component 39 can be a resistor, or a diode with an anode connected to drain contact 35 and a cathode connected to source contact 34. Or, current-carrying component 39 can be a combination of transistors and diodes, connected in parallel, series, or a combination of parallel and series connections.
Still referring to
As used herein, two or more contacts or other items such as conductive layers or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, i.e., is about the same, at all times under any bias conditions. As used herein, a “hybrid enhancement-mode electronic device or component” is an electronic device or component formed of a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor configured such that the component can operate similarly to a single high-voltage enhancement-mode transistor. That is, a hybrid enhancement-mode device or component includes at least 3 nodes having the following properties. When the first node (source node) and second node (gate node) are held at the same voltage, the hybrid enhancement-mode device or component can block a positive high voltage applied to the third node (drain node) relative to the source node. When the gate node is held at a sufficiently positive voltage relative to the source node, current passes from the source node to the drain node or from the drain node to the source node when a sufficiently positive voltage is applied to the source node relative to the drain node or to the drain node relative to the source node, respectively. As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications.
As used herein, a “high-voltage device”, such as a high-voltage switching transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, i.e., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least Vmax, where Vmax is the maximum voltage that can be supplied by the circuit or power supply, and Vmax can for example be 300V, 600V, 1200V, or other suitable blocking voltage required by the application. In some implementations, a high-voltage device can block any voltage between 0V and at least 2*Vmax. As used herein, a “low-voltage device”, such as a low-voltage transistor, is an electronic device which is capable of blocking low voltages, such as between 0V and Vlow (where Vlow is less than Vmax), but is not capable of blocking voltages higher than Vlow. In some implementations, Vlow is equal to about |Vth|, about 2*|Vth|, about 3*|Vth|, or between about |Vth| and 3*|Vth|, where |Vth| is the absolute value of the threshold voltage of a high-voltage transistor contained within the circuit in which the low-voltage device is used. In other implementations, Vlow is about 10V, about 20V, about 30V, about 40V, or between about 5V and 50V, such as between about 10V and 30V. In yet other implementations, Vlow is less than about 0.5*Vmax, less than about 0.3*Vmax, less than about 0.1*Vmax, less than about 0.05*Vmax, or less than about 0.02*Vmax. In implementations described herein, high-voltage transistors which are connected or coupled to a low-voltage transistor can have breakdown voltages which are at least 3 times, at least 5 times, or at least 10 times the breakdown voltage of the low-voltage transistor.
Dispersion refers to a difference in observed current-voltage (I-V) characteristics when the device is operated under RF or switching conditions, as compared to when the device is operated under DC conditions. In III-N devices, effects such as dispersion are often caused by voltage fluctuations at the uppermost surface(s) of the III-N material layers, the result of charging of surface states during device operation. Accordingly, an insulating layer such as layer 22 in
Referring again to
Referring now to
For the devices of
As in previous implementations, a recess is formed through the insulator layer 22 and optionally into the III-N material structure in the gate region 81 where gate 88 is formed, and gate insulator 87 and gate 88 are deposited in the recess. As seen in
Similar to the case described for device 40 in
The same may also be true for devices 80, 90, 90′, and 90″, which are illustrated in
In the device 70 of
Such a configuration is shown in device 80 of
For each of devices 70 and 80 in
In the configuration shown in
As stated earlier, III-N layers 11 and 12 have different compositions from one another. The compositions are selected such that the second III-N layer 12 has a larger bandgap than the first III-N layer 11, which helps enable the formation of 2DEG 19. As an example, III-N layer 11 can be GaN and III-N layer 12 can be AlGaN or AlInGaN, whereas layer 12 can be n-doped or can contain no significant concentration of doping impurities. In the case that layer 12 is undoped, the induced 2DEG results from the difference in polarization fields between layers 11 and 12.
Substrate 10 can be any suitable substrate upon which III-N layers 11 and 12 can be formed, for example silicon carbide (SiC), silicon, sapphire, GaN, AlN, or any other suitable substrate upon which III-N devices can be formed. In some implementations, a III-N buffer layer (not shown) such as AlGaN or AlN is included between substrate 10 and semiconductor layer 11 to minimize material defects in layers 11 and 12.
A method of forming the device of
Referring to
Next, as illustrated in
Next, as seen in
Referring to
Next, as illustrated in
Another implementation of a III-Nitride device 100 is shown in
Referring to
As in previous implementations, switches 111 and 112 each include source-connected field plates 92 and 102, respectively. Field plate 92 is electrically connected to the first source contact 94, such that field plate 92 and the first source contact 94 are part of electrode 96. Field plate 102 is electrically connected to the second source contact 104, such that field plate 102 and the second source contact 104 are part of electrode 106. Similar to the field plate 79 of the transistor 70 in
Also as in previous implementations, gate recesses for the gates of both switches 111 and 112 are formed through the insulator layer 22 and optionally into the III-N material structure in the gate regions where gates 98 and 108 are formed, gate insulator 97 and gate electrode 98 are deposited in the first recess, and gate insulator 107 and gate electrode 108 are deposited in the second recess. As seen in
Also similar to previously described implementations, in device 100 of
Although not shown in
Another implementation of a III-Nitride device 120 is shown in
As in previous implementations, device 120 also includes source-connected field plates 122 and 132. Field plate 122 is electrically connected to the first source contact 124, such that field plate 122 and the first source contact 124 are part of electrode 126. Field plate 132 is electrically connected to the second source contact 134, such that field plate 132 and the second source contact 134 are part of electrode 136. Similar to the field plate 79 of the transistor 70 in
Also as in previous implementations, gate recesses for both gates 128 and 138 are formed through the insulator layer 22 and optionally into the III-N material structure in the gate regions where gates 128 and 138 are formed, gate insulator 127 and gate electrode 128 are deposited in the first recess, and gate insulator 137 and gate electrode 138 are deposited in the second recess. As seen in
Also similar to previously described implementations, in device 120 of
Device 130 in
As in previously described implementations, device 130 can further include additional contacts 125 and 135 contacting the 2DEG 19 between the two gate electrodes 128 and 138. Opposite ends of a first diode 148 are connected to the first electrode 126 and to the first additional contact 125, and opposite ends of a second diode 149 are connected to the second electrode 136 and to the second additional contact 135. As illustrated in
When the device 130 is biased in the off state, for example with a large voltage applied to the second source contact 134 relative to the first source contact 124 and with the first gate 128 biased below its threshold voltage relative to the first source contact 124, the majority of the total voltage dropped across the device is supported/blocked in the III-N material in the region between portions 123 and 133. Only a small voltage is applied across either of the diodes 148 and 149. As such, the reverse bias breakdown voltage of the diodes can be much smaller than the breakdown voltage of the bidirectional switch, which can result in lower switching losses and lower electromagnetic interference (EMI) during switching, as compared to the case where a higher voltage diode is used. In one implementation, the reverse bias breakdown voltage of the diodes is less than 0.3 times the breakdown voltage of the bidirectional switch 130. Note that when the device 130 is biased off in state described above, with a large voltage applied to the second source contact 134 relative to the first source contact 124, the device is in the off state whether the second gate electrode 138 is biased above or below its threshold voltage.
Another implementation of a III-Nitride device 140 is shown in
As seen in
Also as in previous implementations, gate recesses for both gates 168 and 178 are formed through the insulator layer 22 and optionally into the III-N material structure in the gate regions where gates 168 and 178 are formed, gate insulator 167 and gate electrode 168 are deposited in the first recess, and gate insulator 177 and gate electrode 178 are deposited in the second recess. As seen in
Also similar to previously described implementations, in device 140 of
As further illustrated in
As in previously described implementations, device 140 can further include additional contacts 165 and 175 contacting the 2DEG 19. Opposite ends of the first diode 158 are connected to the electrode 146 and to the first additional contact 165, and opposite ends of the second diode 159 are connected to the electrode 146 and to the second additional contact 175. As illustrated in
When the device 140 is biased in the off state, for example with a large voltage applied to the first drain contact 155 relative to the second drain contact 165 and with the first gate 168 biased below its threshold voltage relative to the source contact 144, the majority of the total voltage dropped across the device 140 is supported/blocked in the III-N material in the region between the first drain contact 155 and portion 143 of field plate 142. Only a small voltage is applied across either of the diodes 158 and 159. As such, the reverse bias breakdown voltage of the diodes can be much smaller than the breakdown voltage of the bidirectional switch, which can result in lower switching losses and lower electromagnetic interference (EMI) during switching, as compared to the case where a higher voltage diode is used. In one implementation, the reverse bias breakdown voltage of the diodes is less than 0.3 times the breakdown voltage of the bidirectional switch 130. Note that when the device 140 is biased off in state described above, with a large voltage applied to the first drain contact 155 relative to the second contact 165 and gate 168 biased below its threshold voltage relative to the source contact 144, the device is in the off state whether the second gate electrode 178 is biased above or below its threshold voltage.
While bidirectional switches 120 and 130 of
A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Features shown in each of the implementations may be used independently or in combination with one another. Accordingly, other implementations are within the scope of the following claims.
This is a continuation application of U.S. application Ser. No. 15/440,404, filed on Feb. 23, 2017, which is a continuation of U.S. application Ser. No. 14/714,964, filed on May 18, 2015 (now U.S. Pat. No. 9,590,060), which is a divisional application of U.S. application Ser. No. 13/799,989, filed on Mar. 13, 2013 (now U.S. Pat. No. 9,087,718). The disclosures of the prior applications are considered part of and are incorporated by reference in the disclosure of this application.
This invention was made with Government support awarded by ARPA-E [Award #DE-AR0000212]. The Government has certain rights in this invention, including the right to revoke or modify the license to manufacture if the recipient is unable to expeditiously realize practical applications.
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| Number | Date | Country | |
|---|---|---|---|
| 20180315843 A1 | Nov 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13799989 | Mar 2013 | US |
| Child | 14714964 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15440404 | Feb 2017 | US |
| Child | 16029505 | US | |
| Parent | 14714964 | May 2015 | US |
| Child | 15440404 | US |
