BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view of a wiring board showing the entire appearance of the wiring board;
FIG. 2 is a plan view of the wiring board;
FIG. 3 is a sectional view of the wiring board;
FIG. 4 is an enlarged sectional view of an essential portion of the wiring board shown in FIG. 3;
FIG. 5 is a plan view showing the process of manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 6 is a sectional view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 7 is an enlarged sectional view of an essential portion of the semiconductor device shown in FIG. 6;
FIG. 8 is a plan view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 9 is a sectional view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 10 is a sectional view showing a wire bonding step;
FIG. 11 is a plan view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 12 is a sectional view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 13 is a plan view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 14 is a sectional view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 15 is a plan view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 16 is a sectional view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 17 is a sectional view showing the process of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 18 is an enlarged sectional view of an essential portion of the semiconductor device shown in FIG. 17; and
FIG. 19 is a plan view showing a wiring board in which the proportion of portions where Cu wiring exists in the surface area for bonding of the chip is 90% or more.