This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0096486, filed on Sep. 23, 2011, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
Embodiments of the inventive concepts relate to semiconductor chips, semiconductor packages including the same, and methods of fabricating the same.
Packaging technology is continuously being developed to meet requirements for small-sized and highly reliable semiconductor products. Such technologies include stacking techniques, in which two or more chips or two or more packages are stacked along a vertical direction, which have been intensively developed to meet the requirement for small-sized and high performance electronic products.
Due to the use of the stacking techniques, it may be possible to realize, for example, a memory device with an increased capacity, which may be two or more times higher than a chip-level capacity realized by a process of integrating each semiconductor chip. In addition to the increase in capacity, various technical advantages, such as high efficiency in packaging density and/or packaging area, may be achieved from semiconductor packages fabricated by the stacking technique.
In the meantime, there is an increasing demand for a flip-chip bonding technique, because it can improve a signal transmitting speed of the stack-type semiconductor package. In a stack structure fabricated by the flip-chip bonding technique, a through-silicon via may be used to transmit signals between chips or packages thereof.
Some embodiments provide a semiconductor device including a substrate and a through via penetrating the substrate. The through via has a protruding portion at a first end thereof extending out from a first surface of the substrate and a second end of the via contacting an interconnection line proximate a second, opposite, end of the substrate. A wetting layer is positioned between the via and the substrate and extends over the protruding portion of the via. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer.
In other embodiments, the wetting layer includes at least one of gold (Au), palladium (Pd) and platinum (Pt) and the device further includes a first and second barrier layer. The first barrier layer is interposed between the wetting layer and the substrate. The first barrier layer does not extend over at least a portion of the protruding portion. The second barrier layer is interposed between the wetting layer and the via. The first and second material layers comprise a material selected to limit diffusion of gold (Au), palladium (Pd) and platinum (Pt) from the wetting layer.
In further embodiments, the first barrier layer extends over only a lower portion of sidewalls of the protruding portion and does not extend over an upper portion of the sidewalls or an upper surface of the protruding portion so that the solder ball contacting the wetting layer on the upper surface and the upper portion of the sidewalls of the protruding portion.
In other embodiments, the semiconductor device includes a seed layer positioned between the via and the second barrier layer. At least one of the seed layer and the via include copper. The second barrier layer comprises a material selected to limit diffusion of copper from the at least one of the seed layer and the via. The first barrier layer and the second barrier layer may include at least one of titanium, titanium nitride, tantalum, and tantalum nitride. The device may further include a contact barrier layer positioned between the at least one of the seed layer and the via and the interconnection line. The contact barrier layer may be a material selected to limit diffusion of copper from the at least one of the seed layer and the via to the interconnection line.
In further embodiments, a semiconductor package includes the semiconductor device as described above as a first semiconductor device. The semiconductor package further includes a second semiconductor device stacked on the first semiconductor device and having a conductive component positioned proximate the protruding portion of the via. The solder ball is positioned between the wetting layer and the conductive component of the second semiconductor device and forms an electrical connection between the via and the conductive component including an intermetallic component (IMC) layer formed by interfusion between the wetting layer and the solder ball. The IMC layer may extend to cover at least a portion of a sidewall of the protruding portion of the via having the wetting layer thereon.
In other embodiments, the second semiconductor device includes a through via penetrating a substrate thereof and having a protruding portion. The protruding portion of the through via of the second semiconductor device is positioned proximate the protruding portion of the via of the first semiconductor device with the solder ball and IMC therebetween.
In further embodiments, the second semiconductor device includes a through via penetrating a substrate thereof and having a protruding portion at a first end thereof and an interconnection line proximate a second, opposite end thereof. The solder ball is positioned between the protruding portion of the first semiconductor device and the interconnection line of the second semiconductor device.
In yet further embodiments, a method of forming a semiconductor device includes forming a hole in a substrate of the semiconductor device and sequentially conformally forming a first barrier layer, a wetting layer and a second barrier layer in the hole using a deposition process. A through via is formed on the second barrier layer to fill the hole. A surface of the substrate is etched back to define a protruding portion of the via extending out from the surface of the substrate. Etching back the surface includes removing the first barrier layer from an upper surface and a portion of sidewalls of the protruding portion without removing the wetting layer. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer.
In other embodiments, forming a hole is preceded by forming an interlayer dielectric layer including an integrated circuit therein on an opposite, second surface of the substrate. Forming the hole includes forming the hole through the interlayer dielectric layer. Sequentially conformally forming includes forming the first barrier layer, the wetting layer and the second barrier layer on an upper surface of the interlayer dielectric layer. Forming the through via includes forming the through via filling the hole an extending over the upper surface of the interlayer dielectric layer. Forming the through via is followed by planarizing the upper surface of the interlayer dielectric layer to expose the upper surface of the interlayer dielectric layer. Interconnection lines are formed on the upper surface of the interlayer dielectric layer that electrically couple the via in the hole to the integrated circuit in the interlayer dielectric layer. A conductive bump including a solder ball is formed on the upper surface of the interlayer dielectric layer aligned with the via and electrically connected to the interconnection lines and the via.
Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.
Advantages and features of the present inventive concept and methods of accomplishing the same may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. The present inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present inventive concept will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on”, “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper”, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, these embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concept.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
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A seed pattern (layer) 17a may be provided between the wetting pattern 13a and the through via 19a. The seed pattern 17a may be formed of a material including copper. A first barrier pattern (layer) 11a may be provided between the wetting pattern 13a and the insulating liner 9a, and a second barrier pattern (layer) 15a may be provided between the wetting pattern 13a and the seed pattern 17a. The first and second barrier patterns 11a and 15a may be formed of a material including at least one selected from the group consisting of titanium, titanium nitride, tantalum, and tantalum nitride. The second barrier pattern 15a may be configured to limit or even prevent copper elements, which may be included in the seed pattern 17a and the through via 19a, from being diffused. In addition, the first and second barrier patterns 11a and 15a may be configured to limit or even prevent gold elements, which may be included in the wetting pattern 13a, from being diffused. The first barrier pattern 11a may be interposed between the wetting pattern 13a and the insulating liner 9a to serve as an adhesive layer. The wetting pattern 13a, the second barrier pattern 15a and the seed pattern 17a may extend to cover a protruding surface of the through via 19a. In some embodiments, the first barrier pattern 11a and the insulating liner 9a may be formed to expose a sidewall of the wetting pattern 13a, while they protrude outward from the second surface 1b of the substrate 1.
In the semiconductor chip 100 described with reference to
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The first and second barrier layers 11 and 15 may be formed of a material including at least one selected from the group consisting of titanium, titanium nitride, tantalum, and tantalum nitride. For example, the seed layer 17 may be formed of copper. The deposition process may be performed using, for example, a chemical vapor deposition, a physical vapor deposition or an atomic layer deposition method. In some embodiments, a single fabricating line or apparatus may be used to perform the deposition processes of the insulating liner layer 9, the first barrier layer 11, the wetting layer 13, the second barrier layer 15 and the seed layer 17. This may reduce a cost and improve a manufacturing turn-around time. A conductive layer 19 may be formed on the seed layer 17 to fill the through hole 7 provided with the insulating liner layer 9, the first barrier layer 11, the wetting layer 13, the second barrier layer 15 and the seed layer 17. In some embodiments, the conductive layer 19 may be formed using an electroplating or electroless-plating process.
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Thereafter, the supporting structure 31 may be removed, as shown in
Hereinafter, a process of packaging the semiconductor chip 100 will be described with reference to
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In other embodiments, the second semiconductor chip 100b may be different from the semiconductor chip 100 of
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According to example embodiments of the inventive concepts, the protruding through via of the semiconductor chip is covered with the wetting layer, and thus, there is no necessity to additionally form a conductive pad and a wetting layer. This may reduce a thickness of the semiconductor chip and simplify a structure of the semiconductor chip. As a result, it may be possible to realize a semiconductor device or package having an increased density or capacity.
In some embodiments, the solder ball is formed to be in contact with the wetting layer encapsulating the protruding through via. This may improve an adhesive strength between the solder ball and the wetting layer. In addition, the solder ball and the wetting layer may be attached to each other without a natural oxide layer interposed therebetween, and this may improve reliability of the semiconductor package.
In some embodiments, a method of fabricating a semiconductor chip may include forming the insulating liner using a chemical vapor deposition method and forming the first barrier layer, the wetting layer, the second barrier layer, and the seed layer using physical vapor deposition method. This may reduce a cost and improve a manufacturing turn-around time.
As described above, embodiments of the inventive concepts may provide a highly reliable and high density semiconductor chip and a semiconductor package including the same.
Other embodiments of the inventive concepts may provide a fabricating method of a semiconductor chip capable of reducing a cost and improve a manufacturing turn-around time.
According to example embodiments of the inventive concepts, a semiconductor chip may include a substrate, a through via penetrating the substrate, a wetting layer interposed between the through via and the substrate, and a seed layer interposed between the wetting layer and the through via.
In some embodiments, the through via may include a portion protruding outward from a surface of the substrate. Here, a width of the through via may be equivalent to or greater than a height of the protruding portion of the through via.
In some embodiments, the chip may further include a first barrier layer interposed between the wetting layer and the substrate and a second barrier layer interposed between the wetting layer and the seed layer.
In some embodiments, the wetting layer, the second barrier layer and the seed layer may extend to cover a top surface of the through via, and the first barrier layer may be formed to partially expose a sidewall of the wetting layer.
In some embodiments, the seed layer and the through via may be formed of copper containing materials, and the wetting layer may be formed of a material including at least one selected from the group consisting of gold (Au), palladium (Pd) and platinum (Pt).
According to example embodiments of the inventive concepts, a semiconductor package may include a package substrate, a plurality of semiconductor chips stacked on the package substrate, and solder balls interposed between the semiconductor chips to electrically connect the semiconductor chips with each other. At least one of the semiconductor chips may include a first substrate, a first through via penetrating through and protruding from the first substrate, a first wetting layer interposed between the first substrate and the first through via, and a first seed layer interposed between the first wetting layer and the first through via. In addition, the solder ball and the first wetting layer may be connected to each other with an intermetallic compound layer interposed therebetween.
In some embodiments, at least one of the remaining ones of the semiconductor chips may include a conductive pad, and the solder ball may be in contact with both of the intermetallic compound layer and the conductive pad.
In some embodiments, the intermetallic compound, layer may extend to cover at least a portion of a sidewall of the first seed layer.
In some embodiments, at least one of the remaining ones of the semiconductor chips may include a second substrate, a second through via penetrating the second substrate, a second wetting layer interposed between the second substrate and the second through via, and a second seed layer interposed between the second wetting layer and the through via. The solder ball may be in contact with both of the first wetting layer and the second wetting layer.
In some embodiments, a method of fabricating a semiconductor chip may include forming a hole in a substrate, conformally forming a wetting layer in the hole, conformally forming a seed layer on the wetting layer, forming a through via on the seed layer to fill the hole, and then, removing a lower portion of the substrate to expose the wetting layer.
In some embodiments, the wetting layer and the seed layer may be formed using deposition processes, and the through via may be formed using a plating process.
The foregoing is illustrative of the present inventive concept and is not to be construed as limiting thereof. Although a few embodiments of the present inventive concept have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present inventive concept and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present inventive concept is defined by the following claims, with equivalents of the claims to be included therein.
Number | Date | Country | Kind |
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10-2011-0096486 | Sep 2011 | KR | national |