1. Field of the Invention
The present invention relates, in general, to a semiconductor package and method for fabricating the same and, more particularly, to a semiconductor package and method for fabricating the same that allows a plurality of semiconductor chips to be fixedly stacked in a single, thin package.
2. Description of the Prior Art
Currently, there is a tendency in which a plurality of semiconductor chips are packaged and mounted on the motherboard of an electronic device such as a PCS phone, a cellular phone or a notebook to perform various functions within a minimum time, and semiconductor packages in which semiconductor chips are packaged and the electronic devices on which the semiconductor packages are mounted are miniaturized. In the meantime, in order to allow a semiconductor package to be thinned, there has been fabricated a semiconductor package in which an opening is formed in a circuit board and a semiconductor is disposed in the opening.
With reference to
As depicted in the drawing, reference numeral 20′ designates a circuit board 20′ that has an opening 27′. A semiconductor 2′ on the upper surface of which a plurality of input/output pads 4′ are formed is disposed in the opening 27′ of the circuit board 20′. The circuit board 20′ comprises a base resin layer 21′. A circuit pattern including a plurality of bond fingers 22′ and ball lands 23′ are formed on the upper surface of the base resin layer 21′. The surface of the circuit pattern is coated with a cover coat 24′ with the bond fingers 22′ and the ball lands 23′ being exposed upward out of the cover coat 24′. The input/output pad 4′ of the semiconductor chip 2′ is electrically connected to the bond fingers 22′ of the circuit board 20′ by means of connection means 30′. Additionally, an encapsulation 40′ is formed around the semiconductor chip 2′ and the connection means 30′ so as to protect them from the external environment. A plurality of conductive balls 50′ are respectively fusion-welded on the ball lands 23′ to allow the package to be easily mounted on a motherboard.
However, in the conventional semiconductor package 100′, since only a single semiconductor chip 2′ is disposed in the opening 27′, there is an inherent shortcoming in the high density, function and capacity of semiconductor package 100′.
Furthermore, in a case where the semiconductor chip 2′ disposed in the opening of the circuit board 20′ is a memory chip, such as a flash memory chip, SRAM chip or the like, since a plurality of semiconductor packages 100′ must be mounted on a motherboard (not shown), there occurs a problem in which the mounting density is limited.
Recently, there is an increased desire for a semiconductor in which an ASIC (application specific integrated circuit) semiconductor chip and a memory semiconductor chip are packaged together. However, the desire is not satisfied by the conventional semiconductor package.
In order to overcome the problem, there has been developed a stack type semiconductor package in which a plurality of semiconductors respectively having various functions are packaged into a single semiconductor package by stacking the semiconductor chips together. The construction of the stack type semiconductor package is depicted in
In the conventional stack type semiconductor package, a circuit board 10 on which bond fingers 12 are formed includes a resin layer 11, circuit patterns 19 are formed on the upper and lower surfaces of the resin layer 11, and a first semiconductor chip 1 is bonded on the center portion of the circuit board 10 with a bonding layer 7 interposed between the circuit board 10 and the first semiconductor chip 1. Reference numeral 14 designates conductive via holes for connecting the upper circuit pattern 18 to the lower circuit pattern 18, and reference numeral 15 designates cover coats for protecting the circuit patterns 19 from the external environment.
In addition, a second semiconductor chip 2 is bonded on the upper surface of the first semiconductor chip 1 with a bonding layer 7 interposed between the first and second semiconductor chip 1 and 2. The input/output pads 4A of the first semiconductor chip 1 and the input/output pads 4A of the second semiconductor chip 2 are formed along rectangular directions to prevent them from being overlapped. That is, as illustrated in
However, in the conventional stack type semiconductor package 101′, the first semiconductor chip is bonded on the circuit board and the second semiconductor chip is bonded on the first semiconductor chip. Accordingly, the package is very thick which is contrary to recent trends.
Additionally, since the height difference between the input/output pads and the circuit board is excessively enlarged, the loop height of the connection means, such as conductive wires that connect the second semiconductor chip to the circuit pattern, tends to be enlarged. Accordingly, since the loop angle becomes an acute angle, the sweeping phenomenon of the conductive wires occurs easily by the filling pressure during a molding process, thereby causing the inferiority of the package.
As another example of the conventional semiconductor package, a composite stack type semiconductor package 102′ is illustrated in FIG. 9.
As depicted in the drawing, the conventional composite stack type semiconductor package is fabricated by stacking a plurality of conventional Ball Grid Array (BGA) semiconductor packages.
In each of the BGA semiconductor packages, a semiconductor chip 1 is positioned in the opening of a circuit board 10 on the upper and lower surfaces of which ball lands 13 are formed, the input/output pads (not shown) of the semiconductor chip 1 are respectively connected to the bond fingers 12 of conductive material formed on the upper surface of the circuit board 10 by conductive wires 20, the ball lands 13 are electrically connected to the bond fingers 12 through conductive via holes 14, conductive balls 40 are fusion-welded on the ball lands 13, and an encapsulation 30 is formed on the upper surface of the circuit board 10 to protect the semiconductor chip 1 and the conductive wires 20 from the external environment. In this case, the bond fingers 12 formed on the upper surface of the circuit board 10 are exposed to the outside, and projected pads 8 are respectively formed on the bond fingers 12.
In this conventional BGA package, since the semiconductor chip is disposed in the opening in the central portion of the circuit board, the semiconductor package can be fabricated to be relatively thin. Additionally, a plurality of BGA packages are stacked in such a way that one BGA package is bonded on another BGA package with the solder balls on the lower surface of the upper BGA being fusion-welded on the projected pads on the upper surface of the lower BGA, thereby increasing the mounting density of the package.
However, in the conventional composite stack type semiconductor package 102′, since projected pads are formed on the periphery of the circuit board of the BGA package 103′ and solder balls are fusion-welded on the projected pads, the semiconductor package causes inconvenience in having an extra step to form the projected pads, and has a limitation on the reduction of the thickness of electronic devices owing to the thickness of the projected pads. Additionally, in each of BGA packages, since a single chip is mounted in each package, there occur limitations on the maximization of the memory capacity of each package and the increase of the mounting density of each package.
Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and a first object of the present invention is to provide a semiconductor package in which at least two semiconductor chips are mounted at the position of the opening of a circuit board, thereby allowing the semiconductor package to be thinned and achieving high mounting density, high function and high capacity.
A second object of the present invention is to provide a semiconductor package in which solder ball lands are formed on the upper and lower surfaces of its circuit board and a plurality of sub-semiconductor packages are stacked using the solder ball lands, thereby allowing the semiconductor package to be thinned still more and maximizing mounting density and memory capacity.
A third object of the present invention is to provide a method for fabricating a semiconductor package in accordance with the first object, which is capable of eliminating a wire sweeping phenomenon.
In one embodiment of the invention, there is provided a semiconductor package, comprising: a circuit board having, a resin layer provided with an opening at its center portion, and a circuit pattern formed on at least one of the upper and lower surfaces of the resin layer, the circuit pattern including one or more bond fingers and ball lands exposed to the outside; at least two semiconductor chips on one surface of each of which a plurality of input/output pads are formed, the semiconductor chips being stacked at a position of the opening of the circuit board; electric connection means respectively connecting the input/output pads of the semiconductor chips to the bond fingers of the circuit board; an encapsulation with which the semiconductor chips are encapsulated so as to protect them from the external environment; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board; wherein at least one of the semiconductor chips exists within the opening of the circuit board.
In accordance with another embodiment of the invention, there is provided a semiconductor package, comprising: a first semiconductor chip on one surface of which a plurality of input/output pads are formed; a second semiconductor chip bonded by means of a bonding agent on one surface of the first semiconductor on which the input/output pads are formed; a circuit board having, a resin layer provided with an opening at its center portion, the opening being of a size for accommodating the first and second semiconductor chips, two circuit patterns formed on at least one of the upper and lower surfaces of the resin layer, and at least one cover coat with which the circuit pattern is coated; electric connection means respectively connecting the input/output pads of the first and second semiconductor chips to the bond fingers of the circuit board; an encapsulation with which the first and second semiconductor chips are encapsulated so as to protect them from the external environment; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board.
In various embodiments, one or both of the first and second semiconductor chips are rectangular in plan view, and the input/output pads of the first semiconductor chip and the input/output pads of the second semiconductor chip are respectively arranged along different directions in their sectional view or plan view.
In one embodiment, the first semiconductor chip is exposed out of the encapsulation at a surface opposite to a surface on which the second semiconductor chip is bonded.
In one embodiment, the input/output pads of the first and second semiconductor chips are arranged in directions opposite to those in which the conductive balls are arranged. Alternatively, the input/output pads of the first and second semiconductor chips are arranged in same directions as those in which the conductive balls are arranged.
The circuit board in one embodiment is fabricated in such a way that circuit patterns are formed on the upper and lower surfaces of the resin layer and the circuit patterns are electrically connected to each other through conductive via holes.
In accordance with another embodiment of the present invention, there is provided a semiconductor package, comprising: a circuit board having, a resin layer provided with an opening at its center portion, and two circuit patterns formed on the upper and lower surfaces of the resin layer, the circuit patterns including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; a first semiconductor chip on a lower surface of which a plurality of input/output pads are formed, the first semiconductor chip being disposed in the opening of the circuit board; a second semiconductor chip on the upper surface of which a plurality of input/output pads are formed, the second semiconductor chip being bonded on the upper surface of the first semiconductor chip; connection means connecting the input/output pads of the first and second semiconductor chips to the bond fingers formed on the upper and lower surfaces of the circuit board; a first encapsulation with which a predetermined area of the lower surface of the circuit board covering the first semiconductor chip and the opening is encapsulated; a second encapsulation with which a predetermined area of the upper surface of the circuit board covering the second semiconductor chip and the opening is encapsulated; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board.
The package may further include a third semiconductor, the third semiconductor being connected to the bond fingers of the circuit board with connection means.
The package may further include a fourth semiconductor chip bonded on the lower surface of the first semiconductor chip, and connection means connecting the fourth semiconductor chip to the bond fingers of the circuit board.
The first encapsulation may be formed of a liquid phase encapsulation material and the second encapsulation may be formed of an epoxy molding compound.
The package may further include a dam formed along the upper surface of the circuit board in the vicinity of the opening so as to prevent a bonding agent for bonding the second semiconductor chip on the first semiconductor chip from overflowing.
In accordance with an embodiment of the present invention for accomplishing the second object, there is provided a semiconductor package, comprising: a semiconductor chip within an opening of a circuit board on the upper and lower surfaces of which two circuit patterns are respectively formed, the lower surface of the semiconductor chip and the lower surface of the circuit board being on a same plane; electric connection means respectively connecting the input/output pads of the semiconductor chips to the circuit pattern formed on the upper surface of the circuit board; a plurality of conductive via holes electrically connecting the circuit patterns formed on the upper and lower surfaces of the circuit board to each other; a plurality of ball lands on which a plurality of conductive balls are fusion-bonded, the ball lands being formed on the circuit patterns formed on the upper and lower surfaces of the circuit board; and an encapsulation for protecting the semiconductor chip and the connection means from the external environment.
The semiconductor chip may consist of at least two stacked sub-semiconductor chips, input/output pads of the sub-semiconductor chips being electrically connected to the circuit pattern formed on the upper surface of the circuit board by the connection means.
The semiconductor package may further include one or more additional semiconductor packages wherein a plurality of solder balls are fusion-bonded on the ball lands formed on the lower surface of the circuit board of each semiconductor package, all the semiconductor packages being fixedly stacked together with the solder balls of the lower surface of the circuit board of one semiconductor package being fusion-bonded on the ball lands of the upper surface of the circuit board of another semiconductor package.
In accordance with an embodiment of the present invention, there is provided a method for fabricating a semiconductor package, comprising: providing a circuit board, the circuit board having a resin layer and two circuit patterns, the resin layer being provided with an opening at its center portion, the circuit patterns being formed on the upper and lower surfaces of the resin layer and including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; disposing a first semiconductor chip, on the lower surface of which a plurality of input/output pads are formed, in the opening of the circuit board, and connecting the input/output pads of the first semiconductor chip to the bond fingers of the circuit board with connection means; primarily encapsulating a predetermined area of the lower surface of the circuit board covering the first semiconductor chip and the opening with an encapsulating material; bonding a second semiconductor chip, on the upper surface of which a plurality of input/output pads are formed, on the upper surface of the first semiconductor chip, and connecting the input/output pads of the second semiconductor chip to the bond fingers of the circuit board with connection means; secondly encapsulating a predetermined area of the upper surface of the circuit board covering the second semiconductor chip and the opening with an encapsulating material; and fusion-bonding a plurality of conductive balls on the ball lands of the circuit board.
The first semiconductor chip may consist of at least two sub-semiconductors, i.e., two chips stacked upon each other.
The second semiconductor chip also may consist of at least two sub-semiconductors.
The method may further include the step of bonding another semiconductor chip on the lower surface of the first semiconductor chip after the step of disposing the first semiconductor within the opening of the circuit board.
The method may further include the step of bonding another semiconductor chip on the upper surface of the second semiconductor chip after the step of bonding the second semiconductor.
In accordance with another embodiment of the present invention, there is provided a method for fabricating a semiconductor package, comprising: providing a circuit board, the circuit board having a resin layer and two circuit patterns, the resin layer being provided with an opening at its center portion, the circuit patterns being formed on the upper and lower surfaces of the resin layer and including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; bonding at least one semiconductor chip over the opening of the circuit board, and connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board with connection means; primarily encapsulating the upper surface of the opening of the circuit board and the semiconductor chip with an encapsulating material; disposing at least one semiconductor chip, on the lower surface of which a plurality of input/output pads are formed, within the opening of the circuit board, and connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board with connection means; secondly encapsulating a predetermined area of the lower surface of the circuit board covering the semiconductor chip and the opening with an encapsulating material; and fusion-bonding a plurality of conductive balls on the ball lands of the circuit board.
The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
This application claims priority to Korean patent applications 99-35108, 99-65926 and 99-65934, which were filed in the KIPO on Aug. 24, 1999, Dec. 30, 1999 and Dec. 30, 1999, respectively, and are incorporated herein by reference in their entireties. Certified copies have been filed herewith.
At least one of the first and second semiconductor chips 1 and 2 is shaped in the form of an oblong rectangle in this example (though both may be oblong), so that the input/output pads of the first semiconductor chip 1 and the input/output pads 2a of the second semiconductor chip 2 are prevented from disturbing each other, thereby allowing a connecting process to be easily performed by means of connection means 20, such as conductive wires, leads, or extensions of the bond fingers. Of course, both of the first and second semiconductor chips may be shaped in the form of oblong rectangles. Additionally, the input/output pads of the first semiconductor chip 1 and the input/output pads 2a of the second semiconductor chip are formed on different positions in their sectional view or plan view (although not visible in FIGS. 1A and 1B), so that the connecting process is easily performed by means of connection means 20. That is, if the input/output pads of the first semiconductor chip 1 are formed along the front and rear edges of the first semiconductor chip 1, the input/output pads 2a of the second semiconductor chip 2 are formed along the side edges of the second semiconductor chip 2.
A circuit board 10 is disposed around the first semiconductor chip 1. A predetermined-sized opening 16 is formed in the center portion of the circuit board 10, and the first semiconductor chip 1 is accommodated in the opening 16. In the circuit board 10, a conductive pattern 19 is minutely formed on the lower surface of a resin layer 11, and the circuit pattern 19 is coated with a cover coat 15 for protecting the circuit pattern 19 from the external environment.
The input/output pads of the first and second semiconductor chips 1 and 2 are respectively connected to the circuit pattern 19 formed on the lower surface of the resin layer 11 by means of electric connection means 20, such as conductive wires. As a result, electric signals can be transmitted via the connection means from the first and second semiconductor chips 1 and 2 to the circuit pattern 19 or from the circuit pattern 19 to the first and second semiconductor chips 1 and 2.
The first and second semiconductor chips 1 and 2 and the connection means 20 are encapsulated with an encapsulation material for protecting them from dust, moisture, mechanical impact and the like. The area that is encapsulated with the encapsulation material is referred to as an encapsulation 30. A plurality of conductive balls 40 are fusion-bonded on the circuit pattern 19 formed on the lower surface of the resin layer 11 to allow the package to be mounted on a motherboard. The conductive balls 40 are preferably solder balls.
In this case, since the direction along which the input/output pads of the first semiconductor chip 1 and the input/output pads 2a of the second semiconductor chip 2 are arranged is the same as that of the circuit pattern 19 or the conductive balls 40, an additional circuit pattern and an additional cover coat may be formed on the upper surface of the circuit board 10.
The upper surface of the first semiconductor chip 1, that is, the surface that is not in contact with the second semiconductor chip 2, is exposed out of the encapsulation 30 to dissipate heat out of the package. As illustrated in
Although the input/output pads of the first and second semiconductor chips 1 and 2 are depicted to be formed on the lower surfaces of the first and second semiconductor chips 1 and 2 in
The semiconductor packages 103, 104 and 105 of the second embodiment are similar to the semiconductor packages 101 and 102 of the first embodiment. The difference between them is described as follows.
In the drawings, reference numeral 1 designates a first semiconductor chip 1 on the upper surface of which input/output pads 1a are formed. A second semiconductor 2 is bonded on the surface of first semiconductor chip 1, on which input/output pads are not formed, by means of a bonding layer 7. Input/output pads 2a (not shown) are formed on the upper surface of the second semiconductor 2, also. The lower surface of the second semiconductor chip 2 is exposed out of an encapsulation 30 to improve the performance of heat dissipation.
A circuit board 10 is disposed around the first semiconductor chip 1. A predetermined-sized opening 16 is formed in the center portion of the circuit board 10, and the first semiconductor chip 1 is accommodated in the opening 16. In the circuit board 10, conductive patterns 19 are minutely formed on the upper and lower surfaces of a resin layer 11, and the circuit patterns 19 are coated with cover coats 15 for protecting the circuit patterns 19 from the external environment. The conductive patterns 19 formed on the upper and lower surfaces of a resin layer 11 are connected to each other through conductive via holes 14.
The input/output pads 1a of the first semiconductor chip 1 are connected to the circuit patterns 19 formed on the upper surface of the resin layer 11 by means of electric connection means 20, and the input/output pads 2a (not shown) of the second semiconductor chip 2 are connected to the circuit pattern 19 formed on the lower surface of the resin layer 11 by means of electric connection means 20, e.g., bond wires. As a result, electric signals are transmitted from the first and second semiconductor chips 1 and 2 to a mother board or from the mother board to the first and second semiconductor chips 1 and 2, through the connection means, the circuit patterns 19, the conductive via holes 14 and the circuit pattern 19.
In accordance with the second embodiment, a thin semiconductor package can be obtained because the first semiconductor chip 1 is disposed in the opening of the circuit board 10, and the sweeping phenomenon of the connection means 20 is prevented because the loop height of the connection means connecting the second semiconductor chip 2 to the circuit board 10 is relatively small. Low loop wire bonds may be used.
As illustrated in
As depicted in
In the semiconductor packages in accordance with the first and second embodiments 101 to 105, since an opening is formed on the circuit board and reduces the thickness of the package, the semiconductor package can be thin notwithstanding that a plurality of semiconductor chips are stacked.
Additionally, since a plurality of semiconductor chips are stacked, various semiconductor chips having various functions can be provided in a single semiconductor package, for example, a memory chip and a logic chip or a processor chip can be stacked.
Furthermore, since the height difference between the input/output pads of the second semiconductor chip and the circuit board is equal to the height difference between the input/output pads of the first semiconductor chip and the circuit board, the hoop height of the connection means is relatively small. Accordingly, the possibility of the occurrence of the sweeping phenomenon of the connection means can be reduced notwithstanding that the semiconductor chips are stacked.
As shown in
A first semiconductor chip 1 is disposed in the opening 16 of the circuit board 10. A plurality of input/output pads 1a are formed on the lower active surface of chip 1.
A second semiconductor chip 2 is bonded on the upper surface of the first semiconductor chip 1 by means of a bonding agent 34. A plurality of input/output pads 2a are formed on the upper surface of the second semiconductor chip 2.
A dam 17 of a predetermined height is formed on the upper surface of the circuit board 10 to prevent the bonding agent 34, which is used to bond the second semiconductor chip 2 on the first semiconductor chip 1, from contaminating the bond fingers 12. The dam 17 is preferably made of the same material as that of a general cover coat. Alternatively, the bonding agent 34 may be a preformed adhesive film.
Even though a third semiconductor chip 3 that is smaller than the second semiconductor chip 2 may be bonded on the upper surface of the second semiconductor chip 2, the present invention is not limited to this. Of course, a plurality of input/output pads 3a are formed on the upper surface of the third semiconductor chip 3.
The input/output pads 1a, 2a and 3a of the first, second and third semiconductor chips 1, 2 and 3 are respectively connected to the bond fingers 12 formed on the upper and lower surfaces of the circuit board 10 by means of connection means 20, such as an aluminum or gold wire. That is, the input/output pads 1a of the first semiconductor chip 1 are connected to the bond fingers 12 formed on the lower surface of the circuit board 10, while the input/output pads 2a and 3a of the second and third semiconductor chips 2 and 3, respectively, are connected to the bond fingers 12 formed on the upper surface of the circuit board 10.
The predetermined areas of the upper and lower surfaces of the circuit board 10 covering the first, second and third semiconductor chips 1, 2 and 3 and the opening 16 are encapsulated with an insulative encapsulant material. In more detail, the predetermined area of the lower surface of the circuit board 10 covering the first semiconductor chip 1 and the opening 16 is encapsulated with a first encapsulation 31, preferably, a liquid phase encapsulation. However, the first encapsulation 31 is not limited to the liquid phase encapsulation. Additionally, the predetermined area of the upper surface of the circuit board 10 covering the second and third semiconductor chips 2 and 3 and the opening 16 is encapsulated with a second encapsulation 32, preferably, an epoxy molding compound encapsulation. However, the second encapsulation 32 is not limited to the epoxy molding compound encapsulation.
In
As illustrated in
A plurality of conductive balls 40, such as solder balls, are respectively fusion-welded on the ball lands 13 of the circuit board 10, that is, the ball lands 13 formed on the lower surface of the circuit board 10, so that the package can be mounted on a motherboard with the conductive balls 40 fusion-bonded on the predetermined pattern of a motherboard.
As illustrated in
First of all, there is provided a circuit board 10. The circuit board 10 includes a resin layer 11 having an opening 16 at its center portion. Two circuit patterns respectively including bond fingers 12 and the ball lands 13 are respectively formed on the upper and lower surfaces of the resin layer 11. The circuit patterns are connected to each other through conductive via holes 14, which are filled or plated with metal, conductive ink, or some other conductive material.
At this time, a film 18 is bonded on the upper surface of the opening 16 to close the opening 16, so that semiconductor chips 1, 2 and 3 are disposed and bonded easily. Film 18 in may be an adhesive, heat resisting material. For example, film 18 may be a one or two sided adhesive tape or film. Depending on the type of bonding agent subsequently used to affix semiconductor chip 2 to semiconductor chip 1, a ring dam 17 of a predetermined height may be provided on the upper surface of the circuit board in the vicinity of the opening 16 to prevent the bond fingers from being contaminated by a viscous bonding agent.
Thereafter, as shown in
In this case, first semiconductor chip 1 is a single chip. Alternatively, a previously-formed stack of chips may be disposed in opening 16 in order to make the embodiment of FIG. 3C. Of course, the embodiment of
Subsequently, as depicted in
Thereafter, as shown in
In this case, a third semiconductor chip 3 is bonded on the upper surface of the second semiconductor chip 2 with an non-conductive adhesive layer 34. After chip 2 has been attached to chip 1. Alternatively, chips 2 and 3 may be stacked and then the backside of chip 2 maybe attached to chip 1.
Next, as shown in
Thereafter, the second and third semiconductor chips 2 and 3 positioned over the opening 16 are encapsulated with a second encapsulation 32. In this case, the second encapsulation 32 may be formed by molding an epoxy molding compound, but this embodiment is not limited to this.
Finally, as shown in
In one embodiment, circuit board 10 is part of strip of identical interconnected units of circuit boards 10 that are arranged in an array (e.g., in a line or in a matrix having rows and columns of circuit boards 10). A package is assembled at each of the units in parallel process steps, and then after completion, the strip is severed with a saw or the like along the perimeter of each unit so as to singular individual packages each having a circuit board 10. The saw forms orthogonal peripheral sides on circuit board 10. In the embodiment of
As shown in
Subsequently, as depicted in
Thereafter, as shown in
Subsequently, as illustrated in
Thereafter, as shown in
Finally, a plurality of conductive balls 40 are respectively fusion-welded on the ball lands 13 of the circuit board 10, so that the package is capable of being mounted on a motherboard.
In the semiconductor packages 106, 107 and 108 and method for fabricating the same in accordance with the present invention, a plurality of semiconductor chips are mounted in the opening of the circuit board while being stacked, so that the high density, high function and high capacity of the semiconductor packages are achieved.
Furthermore, in the case of a memory semiconductor chip, the capacity of the semiconductor package can be maximized with the minimum size of the semiconductor package.
Additionally, since an ASIC (application specific integrated circuit) semiconductor chip and a memory semiconductor chip may be packaged together in such a single semiconductor package, many electronic functions can be satisfied by the single semiconductor package.
The embodiments of
The semiconductor package 109 of
As shown in
In the composite stack type semiconductor package in accordance with the fourth embodiment, since a plurality of semiconductor packages are integrated into a single body in such a simple way that the conductive balls 40 of one semiconductor package 103 are fusion-bonded on the ball lands 13 of another semiconductor package 103, the semiconductor packages are easily integrated together without a change in construction. Additionally, since the conductive balls 40 of one semiconductor package 103 are fusion-bonded on the ball lands 13 of another semiconductor package 103, the thickness of the composite stack type semiconductor package 109 is saved by the elimination of the thickness of the projected pads 8 when compared with a conventional stack type semiconductor 102′ (refer to FIG. 9).
In accordance with the fourth embodiment, at least one semiconductor chip is disposed within the opening of the circuit board. The embodiment of
As described above, in the semiconductor package 108 in accordance with the fourth embodiment, a composite stack type semiconductor can be fabricated easily by forming solder ball lands on the upper and lower surfaces of the circuit board, so that the semiconductor package can be thinned and the mounting density and memory capacity of the semiconductor package can be maximized. Additionally, two or more semiconductor chips are disposed in a single semiconductor package, so that the mounting density of semiconductor chips and the memory capacity of a semiconductor package.
Although various embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Number | Date | Country | Kind |
---|---|---|---|
99-35108 | Aug 1999 | KR | national |
99-65926 | Dec 1999 | KR | national |
99-65934 | Dec 1999 | KR | national |
This application is a Division of U.S. application Ser. No. 09/648,284, filed Aug. 24, 2000 now U.S. Pat. No. 6,798,049 entitled “Semiconductor Package And Method For Fabricating The Same”.
Number | Name | Date | Kind |
---|---|---|---|
3851221 | Beaulieu et al. | Nov 1974 | A |
4567643 | Droguet et al. | Feb 1986 | A |
4729061 | Brown | Mar 1988 | A |
4730232 | Lindberg | Mar 1988 | A |
4763188 | Johnson | Aug 1988 | A |
4982265 | Watanabe et al. | Jan 1991 | A |
4996587 | Hinrichsmeyer et al. | Feb 1991 | A |
5012323 | Farnworth | Apr 1991 | A |
5025306 | Johnson et al. | Jun 1991 | A |
5040052 | McDavid | Aug 1991 | A |
5138438 | Masayuki et al. | Aug 1992 | A |
5140404 | Fogal et al. | Aug 1992 | A |
5165067 | Wakefield et al. | Nov 1992 | A |
5198888 | Sugano et al. | Mar 1993 | A |
5200362 | Lin et al. | Apr 1993 | A |
5229647 | Gnadinger | Jul 1993 | A |
5273938 | Lin et al. | Dec 1993 | A |
5291061 | Ball | Mar 1994 | A |
5323060 | Fogal et al. | Jun 1994 | A |
5334875 | Sugano et al. | Aug 1994 | A |
5347429 | Kohno et al. | Sep 1994 | A |
5422435 | Takiar et al. | Jun 1995 | A |
5426563 | Moresco et al. | Jun 1995 | A |
5432729 | Carson et al. | Jul 1995 | A |
5436203 | Lin | Jul 1995 | A |
5463253 | Waki et al. | Oct 1995 | A |
5473196 | De Givry | Dec 1995 | A |
5474957 | Urushima | Dec 1995 | A |
5474958 | Djennas et al. | Dec 1995 | A |
5491612 | Nicewarner, Jr. | Feb 1996 | A |
5495394 | Kornfeld et al. | Feb 1996 | A |
5495398 | Takiar et al. | Feb 1996 | A |
5502289 | Takiar et al. | Mar 1996 | A |
5514907 | Moshayedi | May 1996 | A |
5545922 | Golwalkar et al. | Aug 1996 | A |
5569625 | Yoneda et al. | Oct 1996 | A |
5581498 | Ludwig et al. | Dec 1996 | A |
5587341 | Masayuki et al. | Dec 1996 | A |
5604376 | Hamburgen et al. | Feb 1997 | A |
5614766 | Takasu et al. | Mar 1997 | A |
5620928 | Lee et al. | Apr 1997 | A |
5637536 | Val | Jun 1997 | A |
5637912 | Cockerill et al. | Jun 1997 | A |
5646828 | Degani et al. | Jul 1997 | A |
5668405 | Yamashita | Sep 1997 | A |
5682062 | Gaul | Oct 1997 | A |
5689135 | Ball | Nov 1997 | A |
5696031 | Wark | Dec 1997 | A |
5696666 | Miles et al. | Dec 1997 | A |
5715147 | Nagano | Feb 1998 | A |
5721452 | Fogal et al. | Feb 1998 | A |
5737191 | Horiuchi et al. | Apr 1998 | A |
5739581 | Chillara et al. | Apr 1998 | A |
5763939 | Yamashita | Jun 1998 | A |
5777387 | Yamashita et al. | Jul 1998 | A |
5783870 | Mostafazadeh et al. | Jul 1998 | A |
5793108 | Nakahishi et al. | Aug 1998 | A |
5796586 | Lee et al. | Aug 1998 | A |
5798014 | Weber | Aug 1998 | A |
5815372 | Gallas | Sep 1998 | A |
5819398 | Wakefield | Oct 1998 | A |
5835355 | Dordi | Nov 1998 | A |
5861666 | Bellaar | Jan 1999 | A |
5866949 | Schueller | Feb 1999 | A |
5872025 | Cronin et al. | Feb 1999 | A |
5885849 | DiStefano et al. | Mar 1999 | A |
5886412 | Fogal et al. | Mar 1999 | A |
5894108 | Mostafazadeh et al. | Apr 1999 | A |
5903052 | Chen et al. | May 1999 | A |
5917242 | Ball | Jun 1999 | A |
5952611 | Eng et al. | Sep 1999 | A |
5973403 | Wark | Oct 1999 | A |
5977640 | Bertin et al. | Nov 1999 | A |
5986317 | Wiese | Nov 1999 | A |
6001671 | Fjelstad | Dec 1999 | A |
6005778 | Spielberger et al. | Dec 1999 | A |
6013948 | Akram et al. | Jan 2000 | A |
RE36613 | Ball | Mar 2000 | E |
6034427 | Lan et al. | Mar 2000 | A |
6051886 | Fogal et al. | Apr 2000 | A |
6057598 | Payne et al. | May 2000 | A |
6060778 | Jeong et al. | May 2000 | A |
6072243 | Nakanishi | Jun 2000 | A |
6080264 | Ball | Jun 2000 | A |
6100804 | Brady et al. | Aug 2000 | A |
6107689 | Kozono | Aug 2000 | A |
6118184 | Ishio et al. | Sep 2000 | A |
6126428 | Mitchell et al. | Oct 2000 | A |
6127833 | Wu et al. | Oct 2000 | A |
6133637 | Hikita et al. | Oct 2000 | A |
6160705 | Stearns et al. | Dec 2000 | A |
6172419 | Kinsman | Jan 2001 | B1 |
6180881 | Isaak | Jan 2001 | B1 |
6184463 | Panchou et al. | Feb 2001 | B1 |
6198171 | Huang et al. | Mar 2001 | B1 |
6214641 | Akram | Apr 2001 | B1 |
6235554 | Akram et al. | May 2001 | B1 |
6329709 | Moden et al. | Dec 2001 | B1 |
6395578 | Shin et al. | May 2002 | B1 |
6399418 | Glenn et al. | Jun 2002 | B1 |
6452278 | DiCaprio et al. | Sep 2002 | B1 |
6501184 | Shin et al. | Dec 2002 | B1 |
6515356 | Shin et al. | Feb 2003 | B1 |
6541854 | Huang et al. | Apr 2003 | B2 |
6576998 | Hoffman | Jun 2003 | B1 |
Number | Date | Country |
---|---|---|
503 201 | Dec 1991 | EP |
54128274 | Apr 1979 | JP |
56062351 | May 1981 | JP |
60182731 | Sep 1985 | JP |
61059862 | Mar 1986 | JP |
61117858 | Jun 1986 | JP |
62119952 | Jun 1987 | JP |
62126661 | Jun 1987 | JP |
62-126661 | Jun 1987 | JP |
62142341 | Jun 1987 | JP |
63128736 | Jun 1988 | JP |
63211663 | Sep 1988 | JP |
63-244654 | Oct 1988 | JP |
63244654 | Oct 1988 | JP |
1028856 | Jan 1989 | JP |
64001269 | Jan 1989 | JP |
1071162 | Mar 1989 | JP |
1099248 | Apr 1989 | JP |
3169062 | Jul 1991 | JP |
4028260 | Jan 1992 | JP |
4-56262 | Feb 1992 | JP |
4056262 | Feb 1992 | JP |
4096358 | Mar 1992 | JP |
4116859 | Apr 1992 | JP |
4368154 | Dec 1992 | JP |
4398167 | Dec 1992 | JP |
5013665 | Jan 1993 | JP |
5-75015 | Mar 1993 | JP |
5109975 | Apr 1993 | JP |
5136323 | Jun 1993 | JP |
5283601 | Oct 1993 | JP |
10-256470 | Sep 1998 | JP |
11-204565 | Jul 1999 | JP |
1019990016319 | May 1999 | KR |
1999-0065599 | Aug 1999 | KR |
1019990020939 | Sep 1999 | KR |
1019990037925 | Sep 1999 | KR |
1019990037928 | Sep 1999 | KR |
1999-0080278 | Nov 1999 | KR |
Number | Date | Country | |
---|---|---|---|
20040007771 A1 | Jan 2004 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 09648284 | Aug 2000 | US |
Child | 10600931 | US |