Claims
- 1. A method of making a semiconductor package, the method comprising:
providing an insulative substrate having a first surface, an opposite second surface, a through hole therebetween, and electrically conductive circuit patterns at the first surface of the substrate, each circuit pattern including a ball land; bonding a hole closing member to the second surface of the insulative substrate, the hole closing member covering the through hole; disposing a semiconductor chip within the through hole, the semiconductor chip having a first surface with bond pads formed thereon and an opposite second surface, the second surface of the semiconductor chip being bonded to the hole closing member, the first surface of the semiconductor chip ad the first surface of the insulative substrate facing in a same direction; electrically connecting the bond pads of the semiconductor chip to at least one of the electrically conductive circuit patterns; covering the first surface of the semiconductor chip and a portion of the first surface of the insulative substrate with an encapsulant.
- 2. The method of claim 1, further comprising electrically connecting conductive balls to the electrically conductive circuit patterns.
- 3. The method of claim 1, further comprising removing the hole closing member from the second surface of the semiconductor chip and from the second surface of the insulative substrate.
- 4. The method of claim 1, wherein the bonding comprises adhering.
- 5. The method of claim 1, wherein the hole closing member comprises a film.
- 6. The method of claim 1, wherein the hole closing member comprises tape.
- 7. The method of claim 1, wherein the electrically conductive circuit patterns include bond fingers that project into the through hole, the electrically connecting further comprising electrically connecting the bond pads of the semiconductor chip to the bond fingers.
- 8. The method of claim 1 further comprising applying an insulative cover coat over at least a portion of the electrically conductive circuit patterns.
- 9. A method of making a semiconductor package, the method comprising:
providing a circuit board having opposing first and second surfaces a plurality of holes; applying a film to the first surface of the circuit board a film; forming circuit patterns on the film, the circuit patterns including a plurality of bond fingers and ball lands; respectively positioning a plurality of semiconductor chips in the holes of the circuit board, each of the semiconductor chips having a first surface and a second surface, a plurality of input and output pads being formed on the first surfaces of the semiconductor chips; electrically connecting the input and output pads of each semiconductor chip with the bond fingers; covering the semiconductor chips and a portion of the circuit board with an encapsulation material; and forming input and output pads by respectively connecting conductive balls on the ball lands of the circuit board.
- 10. The method of claim 9, further comprising applying a cover coat over at least a portion of the circuit patterns, wherein the ball lands and the bond fingers are exposed through the cover coat.
- 11. The method of claim 9, further comprising:
bonding a hole cover member to the second surface of the circuit board, the ho le cover member covering the plurality of holes; bonding the second surface of each semiconductor chip to the hole cover member; removing the hole cover member after the covering.
- 12. The method of claim 11, wherein the hole cover member comprises tape.
- 13. A method of making a semiconductor package, the method comprising:
providing an insulative substrate having a first surface, an opposite second surface, and a through hole therebetween; bonding a leadframe to the first surface of the insulative substrate, the leadframe having leads extending laterally into the through hole; positioning a semiconductor chip within the through hole, the semiconductor chip having opposing first and second surfaces with bond pads at the first surface; electrically connecting the bond pads with the leads; covering the first surface of the semiconductor chip and the leads with an encapsulation material.
- 14. The method of claim 13, further comprising fusing conductive balls to the leadframe.
- 15. The method of claim 13, wherein the positioning further comprises positioning the semiconductor chip within the through hole such that the first surface of the semiconductor chip faces in a same direction as the first surface of the insulative substrate.
- 16. The method of claim 13, wherein the positioning further comprises positioning the semiconductor chip within the through hole such that the second surface of the semiconductor chip and the second surface of the insulative substrate are in a same plane.
Priority Claims (3)
Number |
Date |
Country |
Kind |
1999-18245 |
May 1999 |
KR |
|
1999-37925 |
Sep 1999 |
KR |
|
1999-37928 |
Sep 1999 |
KR |
|
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of and claims priority of U.S. patent application Ser. No. 09/574,006, now U.S. Patent No. ______, which claims priority of the following Korean patent applications: 1999-18245 filed May 20, 1999, 1999-37925 filed Sep. 7, 1999, and 1999-37928 filed Sep. 7, 1999, the disclosures of which are hereby incorporated by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09574006 |
May 2000 |
US |
Child |
10162953 |
Jun 2002 |
US |