This disclosure relates generally to integrated circuits, and more particularly to methods of stacking dies, and even more particularly to package assemblies including stacked dies and methods of packaging the same.
The semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limit comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the above-discussed limitations. In a typical formation process of 3D ICs, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Deep vias are then formed to interconnect devices in the two wafers.
An alternative scheme for forming 3D ICs is bonding dies. Conventionally, to bond two dies together, each of the dies is bonded onto a package substrate, and then the package substrates are further bonded together to form a package. The known methods include package-in-package (PIP) bonding and package-on-package (POP) bonding. These bonding methods, however, suffer from drawbacks. With the usage of package substrates, which are typically larger than the dies, the size of the final package is increased over any of the dies, which may not be desirable. Further, in conventional packaging schemes, a molding compound is used. However, in some high-performance applications, a significant amount of heat is generated in dies, and the molding compounds, which are often not good thermal conductors, reduce the efficiency in heat dissipation.
In accordance with one aspect of the embodiment, an integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound.
Other embodiments are also disclosed.
For a more complete understanding of the disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the package structure.
A novel package structure and the method of forming the same are presented. The intermediate stages of manufacturing an embodiment are illustrated. The variations of the embodiment are then discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Referring to
In
Referring to
Referring to
It is observed that in package-molded unit 26, top die 10 and bottom die 14 do not need to be bonded onto package substrates first before they are bonded together. As a result, fewer process steps and fewer package substrates are needed. The size of the final package is also small.
Next, as shown in
Referring to
The embodiments have several advantageous features. By bonding top dies directly to bottom wafers without through package substrates, the package size may be reduced, and the process time and the cost are also reduced. The embodiments provide a multi-die stacking solution, in which a temporary flat surface is formed for the processes such as carrier de-bonding, testing, singulation, and the like. Further, with the use of reusable materials, the manufacturing cost is further reduced. The removal of the molding compound also improves the heat-dissipating ability of package assemblies.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the invention.
This application claims the benefit of U.S. Provisional Application No. 61/237,153 filed on Aug. 26, 2009, entitled “Wafer-Level Molded Structure for Package Assembly,” which application is hereby incorporated herein by reference.
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