Stackable via package and method

Information

  • Patent Grant
  • 11700692
  • Patent Number
    11,700,692
  • Date Filed
    Friday, August 6, 2021
    3 years ago
  • Date Issued
    Tuesday, July 11, 2023
    a year ago
Abstract
A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A
Description
BACKGROUND OF THE INVENTION
Field Of The Invention

The present application relates to the field of electronics, and more particularly, to methods of forming electronic component packages and related structures.


Description of the Related Art

To form an electronic component package, an electronic component is mounted to a substrate. The substrate includes traces on the same surface of the substrate to which the electronic component is mounted. Bond wires are formed to electrically connect bond pads of the electronic component to the traces.


To protect the electronic component as well as the bond wires, the electronic component and bond wires are covered in an encapsulant. The traces extend from under the encapsulant to an exposed area of the surface of the substrate outside of the periphery of the encapsulant, i.e., not covered by the encapsulant. The traces include terminals on the exposed area of the substrate outside of and around the encapsulant.


Solder balls are formed on the terminals. These solder balls extend from the substrate to a height greater than the height of the encapsulant to allow the solder balls to be electrically connected to a larger substrate such as a printed circuit motherboard.


However, the solder balls are substantially spherical in shape. Thus, forming the solder balls with a height greater than the height of the encapsulant places fundamental restrictions on minimizing the pitch of the solder balls.


SUMMARY OF THE INVENTION

In accordance with one embodiment, a stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D.


A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<1/2×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.


These and other features of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a cross-sectional view of a stackable via package during fabrication in accordance with one embodiment;



FIG. 2 is an enlarged cross-sectional view of the region II of the stackable via package of FIG. 1 after formation of a via aperture solder ball structure in accordance with one embodiment;



FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 are enlarged cross-sectional views of via aperture solder ball structures in accordance with various embodiments;



FIG. 17 is a cross-sectional view of an electronic component assembly including the stackable via package of FIGS. 1, 2 during fabrication in accordance with one embodiment;



FIG. 18 is a cross-sectional view of the electronic component assembly of FIG. 17 at a later stage during fabrication in accordance with one embodiment;



FIG. 19 is a cross-sectional view of an electronic component assembly including a stackable via package having the via aperture solder ball structure of FIG. 4 during fabrication in accordance with one embodiment;



FIG. 20 is a cross-sectional view of the electronic component assembly of FIG. 19 at a later stage during fabrication in accordance with one embodiment;



FIG. 21 is a cross-sectional view of the electronic component assembly of FIG. 17 having misalignment between an interconnection ball and a solder ball in accordance with one embodiment;



FIG. 22 is a cross-sectional view of the electronic component assembly of FIG. 21 at a later stage during fabrication in accordance with one embodiment;



FIG. 23 is a cross-sectional view of the electronic component assembly of FIG. 19 having misalignment between an interconnection ball and a solder ball in accordance with one embodiment;



FIG. 24 is a cross-sectional view of the electronic component assembly of FIG. 23 at a later stage during fabrication in accordance with one embodiment;



FIG. 25 is a cross-sectional view of an electronic component assembly including the stackable via package of FIGS. 1, 2 during fabrication in accordance with one embodiment;



FIG. 26 is a cross-sectional view of the electronic component assembly of FIG. 25 at a later stage during fabrication in accordance with one embodiment;



FIG. 27 is a cross-sectional view of an electronic component assembly including a stackable via package having the via aperture solder ball structure of FIG. 4 during fabrication in accordance with one embodiment; and



FIG. 28 is a cross-sectional view of the electronic component assembly of FIG. 27 at a later stage during fabrication in accordance with one embodiment.





In the following description, the same or similar elements are labeled with the same or similar reference numbers.


DETAILED DESCRIPTION

As an overview and in accordance with one embodiment, referring to FIGS. 1 and 2 together, a stackable via package 100 includes a substrate 102 having an upper surface 102U and a trace 114 on upper surface 102U, trace 114 including a terminal 228. A solder ball 122 is on terminal 228. Solder ball 122 has a solder ball diameter A and a solder ball height D.


A via aperture 230 is formed in a package body 124 enclosing solder ball 122 to expose solder ball 122. Via aperture 230 includes a via bottom 234, sometimes called a via aperture shelf, having a via bottom diameter B and a via bottom height C from upper surface 102U of substrate 102, where A<B and 0=<C<1/2×D. The shape of via aperture 230 prevents solder deformation of the solder column formed from solder ball 122 as well as prevents solder bridging between adjacent solder columns.


Now in more detail, FIG. 1 is a cross-sectional view of a stackable via package 100 during fabrication in accordance with one embodiment. Stackable via package 100, sometimes called an electronic component package, includes a substrate 102 including an upper, e.g., first, surface 102U and an opposite lower, e.g., second, surface 102L. Substrate 102 further includes sides 102S extending perpendicularly between upper surface 102U and lower surface 102L. Substrate 102 is a dielectric material such as laminate, ceramic, printed circuit board material, or other dielectric material.


Stackable via package 100 further includes an electronic component 104. In one embodiment, electronic component 104 is an integrated circuit chip, e.g., an active component. However, in other embodiments, electronic component 104 is a passive component such as a capacitor, resistor, or inductor.


In accordance with this embodiment, electronic component 104 includes an active surface 106 and an opposite inactive surface 108. Electronic component 104 further includes bond pads 110 formed on active surface 106. Inactive surface 108 is mounted to upper surface 102U of substrate 102 with an adhesive 112, sometimes called a die attach adhesive.


Although electronic component 104 is illustrated and described as being mounted in a wirebond configuration, in other embodiments, electronic component 104 is mounted in a different configuration such as a flip chip configuration. In another embodiment, a plurality of electronic components are mounted, e.g., in a stacked configuration.


Formed on upper surface 102U of substrate 102 are electrically conductive upper, e.g., first, traces 114, e.g., formed of copper. Bond pads 110 are electrically connected to upper traces 114, e.g., bond fingers thereof, by electrically conductive bond wires 116.


Formed on lower surface 102L of substrate 102 are lower, e.g., second, traces 118. Lower traces 118 are electrically connected to upper traces 114 by electrically conductive vias 120 extending through substrate 102 between upper surface 102U and lower surface 102L. Although not illustrated in FIG. 1, in one embodiment as discussed in greater detail below with reference to FIG. 2, stackable via package 100 further includes solder masks on upper and lower surface 102U, 102L that protect first portions of upper and lower traces 114, 118 while exposing second portions, e.g., terminals and/or bond fingers, of upper and lower traces 114, 118.


Although a particular electrically conductive pathway between bond pads 110 and lower traces 118 is described above, other electrically conductive pathways can be formed. For example, contact metallizations can be formed between the various electrical conductors.


Further, instead of straight though vias 120, in one embodiment, substrate 102 is a multilayer substrate and a plurality of vias and/or internal traces form the electrical interconnection between upper traces 114 and lower traces 118.


In accordance with one embodiment, one or more of upper traces 114 is not electrically connected to lower traces 118, i.e., is electrically isolated from lower traces 118, and electrically connected to bond pads 110. To illustrate, a first upper trace 114A of the plurality of upper traces 114 is electrically isolated from lower traces 118 and electrically connected to a respective bond pad 110. In accordance with this embodiment, the respective bond pad 110 electrically connected to upper trace 114A is also electrically isolated from lower traces 118.


In accordance with one embodiment, one or more of upper traces 114 is electrically connected to both bond pads 110 and to lower traces 118. To illustrate, instead of being electrically isolated from lower traces 118, upper trace 114A is electrically connected to lower traces 118 by a via 120A of the plurality of vias 120. In accordance with this embodiment, the respective bond pad 110 is electrically connected to upper trace 114A and is also electrically connected to lower traces 118.


Via 120A is indicated by dashed lines to signify that formation of via 120A is optional. If via 120A is not formed, upper trace 114A is electrically isolated from lower traces 118. Conversely, if via 120A is formed, upper trace 114 is electrically connected to lower traces 118.


In accordance with one embodiment, one or more of upper traces 114 is not electrically connected to a bond pad 110, i.e., is electrically isolated from bond pads 110, and is electrically connected to lower traces 118. To illustrate, the upper trace 114 to the left of electronic component 104 in the view of FIG. 1 is electrically isolated from bond pads 110 and electrically connected to lower traces 118. In accordance with this embodiment, the respective lower traces 118 electrically connected to the upper trace 114 electrically isolated from bond pads 110 are also electrically isolated from bond pads 110.


Although various examples of connections between bond pads 110, upper traces 114, and lower traces 118 are set forth above, in light of this disclosure, those of skill in the art will understand that any one of a number of electrical configurations are possible depending upon the particular application.


Formed on upper traces 114 are electrically conductive solder balls 122. Illustratively, solder balls 122 are formed of solder. In other embodiments, solder balls 122 are formed of other electrically conductive material such as plated copper or electrically conductive adhesive.


As set forth above, in accordance with various embodiments, upper traces 114 are electrically connected to lower traces 118, to bond pads 110, and/or to lower traces 118 and bond pads 110. Thus, in accordance with various embodiments, solder balls 122 are electrically connected to lower traces 118 only, to bond pads 110 only, and/or to both lower traces 118 and bond pads 110.


Electronic component 104, bond wires 116, solder balls 122 and the exposed portions of upper surface 102U including upper traces 114 are enclosed, sometimes called encased, encapsulated, and/or covered, with a package body 124. Illustratively, package body 124 is a cured liquid encapsulant, molding compound, or other dielectric material. Package body 124 protects electronic component 104, bond wires 116, solder balls 122, and the exposed portions of upper surface 102U including upper traces 114 from the ambient environment, e.g., from contact, moisture and/or shorting to other structures.


Package body 124 includes a principal surface 124P parallel to upper surface 102U of substrate 102. In accordance with this embodiment, package body 124 includes sides 124S extending perpendicularly between substrate 102 and principal surface 124P. Sides 124S are parallel to and lie in the same plane as sides 102S of substrate 102. Thus, package body 124 entirely covers upper traces 114.


Illustratively, stackable via package 100 is formed simultaneously with a plurality of packages in an array or strip. The array or strip is singulated resulting in sides 124S of package body 124 parallel to and lying in the same plane as sides 102S of substrate 102


Although the terms parallel, perpendicular, and similar terms are used herein, it is to be understood that the described features may not be exactly parallel and perpendicular, but only substantially parallel and perpendicular to within excepted manufacturing tolerances.


To form stackable via package 100 as illustrated in FIG. 1, inactive surface 108 of electronic component 104 is mounted to upper surface 102U of substrate 102 by adhesive 112. Bond pads 110 are electrically connected to upper traces 114 by bond wires 116. Solder balls 122 are formed on upper traces 114. Electronic component 104, bond wires 116, solder balls 122 and the exposed portions of upper surface 102U including upper traces 114 are enclosed within package body 124. Via apertures are formed in package body 124 to expose solder balls 122 as discussed further below.



FIG. 2 is an enlarged cross-sectional view of the region II of stackable via package 100 of FIG. 1 after formation of a via aperture solder ball structure 200 in accordance with one embodiment. Referring now to FIG. 2, substrate 102 includes a solder mask 226, i.e., a dielectric material, on upper surface 102U. A terminal 228 of upper traces 114 is exposed from solder mask 226. Formation of solder mask 226 is optional, and in one embodiment, solder mask 226 is not formed.


Stackable via package 100 includes a via aperture 230 penetrating into package body 124 from principal surface 124P to expose solder ball 122. Although only a single via aperture 230, a single terminal 228 and a single solder ball 122 are illustrated in FIG. 2 and discussed herein, in light of this disclosure, those of skill in the art will understand that a plurality of via apertures 230 are formed. Each via aperture 230 exposes a respective solder ball 122 on a respective terminal 228.


In one embodiment, via aperture 230 is formed using a laser-ablation process. More particularly, a laser is repeatedly directed at principal surface 124P perpendicularly to principal surface 124P. This laser ablates, i.e., removes, portions of package body 124 leaving via apertures 230, sometimes called a through hole.


Although a laser-ablation process for formation of via aperture 230 is set forth above, in other embodiments, other via aperture formation techniques are used. For example, via aperture 230 is formed using selective molding, milling, mechanical drilling, chemical etching and/or other via aperture formation techniques.


As illustrated in FIG. 2, via aperture 230 extends between principal surface 124P of package body 124 and solder ball 122. Accordingly, solder ball 122 is exposed through via aperture 230.


Via aperture 230 tapers from principal surface 124P to solder ball 122. More particularly, the diameter of via aperture 230 in a plane parallel to principal surface 124P is greatest at the top of via aperture 230, and smallest at the bottom of via aperture 230 and gradually diminishes between the top and bottom of via aperture 230. The top of via aperture 230 is located at principal surface 124P and the bottom of via aperture 230 is located between principal surface 124P of package body 124 and upper surface 102U of substrate 102 in this embodiment.


In another embodiment, via aperture 230 has a uniform diameter, i.e., has a cylindrical shape. In yet another embodiment, via aperture 230 tapers from the bottom to the top of via aperture 230. More particularly, the diameter of via aperture 230 in a plane parallel to principal surface 124P is smallest at the top of via aperture 230 and greatest at the bottom of via aperture 230 and gradually increases between the top and bottom of via aperture 230.


Via aperture 230 is defined by a via aperture sidewall 232 and a via aperture shelf 234 of package body 124. Via aperture shelf 234 is the via bottom of via aperture 230. Via aperture sidewall 232 extends between principal surface 124P of package body 124 and via aperture shelf 234. In accordance with this embodiment, via aperture sidewall 232 is in the shape of the lateral surface of an inverted truncated cone, sometimes called a frustum. Via aperture sidewall 232 is thus sometimes called a sloped sidewall.


Via aperture shelf 234 is parallel to upper surface 102U of substrate 102. Via aperture shelf 234 extends from via aperture sidewall 232 to solder ball 122.


As illustrated in FIG. 2, package body 124 encloses a lower, e.g., first, portion 236 of solder ball 122 while an upper, e.g., second, portion 238 of solder ball 122 is exposed through via aperture 230.


Solder ball 122 has a solder ball diameter A, which is the diameter of solder ball 122. Via aperture shelf 234 has a via aperture shelf diameter B, which is the diameter of via aperture shelf 234. Via aperture shelf diameter B is also the diameter of the bottom of via apertures 230 as so is sometimes also called the via bottom diameter B. In accordance with this embodiment, via aperture shelf diameter B is greater than solder ball diameter A. More particularly, solder ball diameter A and via aperture shelf diameter B are governed by the following relation (1):

A<B.


Via aperture shelf 234 has a via aperture shelf height C from upper surface 102U of substrate 102. More particularly, via aperture shelf height C is the distance between upper surface 102U of substrate 102 and via aperture shelf 234. Via aperture shelf height C is also the distance between upper surface 102U of substrate 102 and the bottom of via aperture 230 so is also sometimes called the via bottom height C. Solder ball 122 has a solder ball height D from upper surface 102U of substrate 102. More particularly, solder ball height D is the distance that solder ball 122 extends from upper surface 102U of substrate 102.


Via aperture shelf height C is greater than or equal to zero and less than one-half of solder ball height D (Solder ball height D is the middle of solder ball 122 in one embodiment). More particularly, via aperture shelf height C and solder ball height D are governed by the following relation (2):

0=<C<1/2×D.


According to relation (2), via aperture shelf 234 is located below the horizontal great circle of solder ball 122, i.e., below the maximum horizontal width of solder ball 122. Solder ball 122 is approximately spherical. The horizontal great circle is an imaginary circle on solder ball 122 that is parallel with upper surface 102U of substrate 102 and has the same center and radius as solder ball 122, and consequently divides solder ball 122 into two approximately equal parts. Accordingly, the cross-sectional area in a plane parallel to upper surface 102U of substrate 102 of lower portion 236 of solder ball 122 increases between terminal 228 and via aperture shelf 234.


Package body 124 includes a solder ball contact surface 240 in direct physical contact with lower portion 236 of solder ball 122. Solder ball contact surface 240 extends between upper surface 102U of substrate 102 and via aperture shelf 234. The circumference in a plane parallel to upper surface 102U of substrate 102 of solder ball contact surface 240 increases between upper surface 102U of substrate 102 and via aperture shelf 234.


Accordingly, the pocket defined by solder ball contact surface 240 which corresponds to lower portion 236 of solder ball 122 has a maximum diameter opening at via aperture shelf 234. In this manner, it has been surprisingly discovered that gases released during reflow of solder ball 122 are readily vented thus avoiding solder deformation of the solder column formed from solder ball 122 as discussed in greater detail below with reference to FIGS. 17 and 18.


As a further surprising result, solder bridging (shorts) between the solder column formed from solder ball 122 and adjacent solder columns is also avoided by via aperture 230. More particularly, by forming via aperture 230 with via aperture shelf 234, in the event that there is excess solder during the solder reflow of solder ball 122, via aperture 230 provides space for capture of the excess solder. This avoids the excess solder from overflowing on top of principal surface 124P of package body 124 and shorting to other electrically conductive structures such as adjacent solder columns. This is also discussed in greater detail below with reference to FIGS. 17 and 18.



FIG. 3 is an enlarged cross-sectional view of a via aperture solder ball structure 300 in accordance with another embodiment. Via aperture solder ball structure 300 of FIG. 3 is similar to via aperture solder ball structure 200 of FIG. 2 and only the significant differences are discussed below. A solder ball 122A of via aperture solder ball structure 300 of FIG. 3 extends to a height from upper surface 102U of substrate 102 which is less than the height that solder ball 122 of via aperture solder ball structure 200 of FIG. 2 extends from surface 102U of substrate 102.


Referring now to FIG. 3, solder ball 122A is hemispherical in shape. More particularly, solder ball 122A approximates the northern hemisphere and is connected to terminal 228 approximate at the equator.


In accordance with this embodiment, via aperture solder ball structure 300 is governed by: relation (1): A<B; and relation (2): 0=<C<1/2×D, where solder ball diameter A is the diameter of solder ball 122A, via aperture shelf diameter B is the diameter of via aperture shelf 234, via aperture shelf height C is the distance between upper surface 102U of substrate 102 and via aperture shelf 234, and solder ball height D is the distance that solder ball 122A extends from upper surface 102U of substrate 102.



FIG. 4 is an enlarged cross-sectional view of a via aperture solder ball structure 400 in accordance with another embodiment. Via aperture solder ball structure 400 of FIG. 4 is similar to via aperture solder ball structure 200 of FIG. 2 and only the significant differences are discussed below.


Referring now to FIG. 4, via aperture solder ball structure 400 is governed by: relation (1): A<B; and relation (2): 0=<C<1/2×D, where C=0, and where solder ball diameter A is the diameter of solder ball 122, via aperture shelf diameter B is the diameter of via aperture 230B at upper surface 102U, and solder ball height D is the distance that solder ball 122 extends from upper surface 102U of substrate 102.


As there is no via aperture shelf in accordance with this embodiment, via aperture shelf diameter B is sometimes called the via bottom diameter B. Further, as there is no via aperture shelf in accordance with this embodiment, a via aperture sidewall 232B of a via aperture 230B extends from principal surface 124P of package body 124 to upper surface 102U of substrate 102. The via bottom of via aperture 230 is at upper surface 102U of substrate 102. Further, an exposed portion 402 of upper surface 102U around terminal 228 and solder ball 122 is exposed through via aperture 230B.


In accordance with via aperture solder ball structure 400, solder ball 122 is mounted to terminal 228 prior to the formation of package body 124. More particularly, package body 124 is formed to enclose solder ball 122 in a manner similar to that discussed above in reference to FIG. 1. After formation of package body 124, via aperture 230B is formed to expose solder ball 122.


In accordance with another embodiment, solder ball 122 is mounted to terminal 228 after formation of package body 124 and via aperture 230B. In accordance with this embodiment, referring to FIGS. 1 and 4 together, electronic component 104, bond wires 116, and the exposed portions of upper surface 102U including upper traces 114 are enclosed within package body 124. Referring now to FIG. 4, via aperture 230B is formed to expose terminal 228. Solder ball 122 is then mounted to terminal 228 resulting in via aperture solder ball structure 400 as illustrated in FIG. 4.



FIG. 5 is enlarged cross-sectional view of a via aperture solder ball structure 500 in accordance with another embodiment. Via aperture solder ball structure 500 of FIG. 5 is similar to via aperture solder ball structure 200 of FIG. 2 and only the significant differences are discussed below.


In accordance with this embodiment, via aperture solder ball structure 500 is governed by: relation (1): A<B; and relation (2): 0=<C<1/2×D, where solder ball diameter A is the diameter of solder ball 122, via aperture shelf diameter B is the diameter of via aperture shelf 234, via aperture shelf height C is the distance between upper surface 102U of substrate 102 and via aperture shelf 234, and solder ball height D is the distance that solder ball 122 extends from upper surface 102U of substrate 102.


As illustrated in FIG. 5, via aperture solder ball structure 500 allows a substantial amount of misalignment between via aperture 230 and solder ball 122. More particularly, solder ball 122 is not required to be centered within via aperture shelf 234. In one embodiment, solder ball 122 is located within the area defined by via aperture shelf 234. In this particular embodiment, solder ball 122 is formed at the outer periphery of via aperture shelf 234 and, more particularly, is formed at the intersection of via aperture sidewall 232 and via aperture shelf 234.


Referring now generally to FIGS. 1-5, principal surface 124P of package body 124 has a package body height H above upper surface 102U of substrate 102. Package body height H is the distance between upper surface 102U of substrate 102 and principal surface 124P. In accordance with the embodiments illustrated in FIGS. 1-5, package body height H is greater than solder ball height D, i.e., H >D. Recall that solder ball height D is the distance that solder ball 122 (solder ball 122A in FIG. 3) extends from upper surface 102U of substrate 102.


In accordance with another embodiment, referring now to FIG. 1, package body 124 has a principal surface 124P-1. Principal surface 124P-1 is located below the tops of solder balls 122 such that solder balls 122 protrude from package body 124 and extend above principal surface 124P-1. In accordance with this embodiment, principal surface 124P-1 is indicated by the dashed line. A package body height H1 is the distance between upper surface 102U of substrate 102 and principal surface 124P-1. Package body height H1 is less than solder ball height D in accordance with this embodiment, i.e., H1<D.



FIGS. 6, 7, 8, 9 are enlarged cross-sectional views of via aperture solder ball structures 600, 700, 800, 900 in accordance with various embodiments. Via aperture solder ball structures 600, 700, 800, 900 of FIGS. 6, 7, 8, 9 are similar to via aperture solder ball structures 200, 300, 400, 500 of FIGS. 2, 3, 4, 5, respectively. One significant difference is that the height H1 of principal surface 124P-1 of package body 124 is less than solder ball height D of solder balls 122 (solder ball 122A in FIG. 7) in accordance with the embodiments of via aperture solder ball structures 600, 700, 800, 900 of FIGS. 6, 7, 8, 9, respectively.


In accordance with yet another embodiment, referring again to FIG. 1, package body 124 has a principal surface 124P-2. Principal surface 124P-2 is parallel to the tops of solder balls 122 such that the tops of solder balls 122 are even with principal surface 124P-2. In accordance with this embodiment, principal surface 124P-2 is indicated by the dashed dot line. A package body height H2 is the distance between upper surface 102U of substrate 102 and principal surface 124P-2. Package body height H2 is equal to solder ball height D in accordance with this embodiment, i.e., H2 =D.



FIGS. 10, 11, 12, 13 are enlarged cross-sectional views of via aperture solder ball structures 1000, 1100, 1200, 1300 in accordance with various embodiments. Via aperture solder ball structures 1000, 1100, 1200, 1300 of FIGS. 10, 11, 12, 13 are similar to via aperture solder ball structures 200, 300, 400, 500 of FIGS. 2, 3, 4, 5, respectively. One significant difference is that the height H2 of principal surface 124P-2 of package body 124 is equal to solder ball height D of solder balls 122 (solder ball 122A in FIG. 11) in accordance with the embodiments of via aperture solder ball structures 1000, 1100, 1200, 1300 of FIGS. 10, 11, 12, 13, respectively.



FIGS. 14, 15, 16 are enlarged cross-sectional views of via aperture solder ball structures 1400, 1500, 1600 in accordance with various embodiments. Via aperture solder ball structures 1400, 1500, 1600 of FIGS. 14, 15, 16 are similar to via aperture solder ball structures 200, 300, 500 of FIGS. 2, 3, 5, respectively. Only the significant differences between via aperture solder ball structures 1400, 1500, 1600 of FIGS. 14, 15, 16 and via aperture solder ball structures 200, 300, 500 of FIGS. 2, 3, 5 are discussed below.


Referring now to FIG. 14, solder ball 122 includes an exposed solder ball diameter E. Exposed solder ball diameter E is the diameter of the portion of solder ball 122 exposed from via aperture shelf 234 when viewed perpendicular to principal surface 124P from the topside, i.e., along the line 1442. State another way, exposed solder ball diameter E is the diameter of the circle defined at the intersection of via aperture shelf 234 and solder ball 122, i.e., at the inner periphery of via aperture shelf 234.


Recall that solder ball 122 has solder ball diameter A. Via aperture shelf 234 has via aperture shelf diameter B. In accordance with this embodiment, solder ball diameter A is greater than via aperture shelf diameter B, which is greater than exposed solder ball diameter E. More particularly, solder ball diameter A, via aperture shelf diameter B, and exposed solder ball diameter E are governed by the following relation (3):

A>B>E.


Referring now to FIG. 15, via aperture solder ball structure 1500 is also governed by relation (3): A>B>E, where solder ball diameter A is the diameter of solder ball 122A, via aperture shelf diameter B is the diameter of via aperture shelf 234, and exposed solder ball diameter E is the diameter of solder ball 122A exposed from via aperture shelf 234.


Referring now to FIG. 16, via aperture solder ball structure 1600 is also governed by relation (3): A>B>E, where solder ball diameter A is the diameter of solder ball 122, via aperture shelf diameter B is the diameter of via aperture shelf 234, and exposed solder ball diameter E is the diameter of solder ball 122 exposed from via aperture shelf 234.


In FIGS. 14, 15, 16, via aperture solder ball structures 1500, 1600, 1700 include principal surface 124P having package body height H greater than solder ball height D of solder balls 122 (solder ball 122A in FIG. 15). Referring now to FIGS. 1, 14, 15, and 16 together, in other embodiments, via aperture solder ball structures 1500, 1600, 1700 are formed to include principal surfaces 124P-1 or 124P-2 having package body height Hl or H2 less than or equal to solder ball height D of solder balls 122 (solder ball 122A in FIG. 15), respectively.



FIG. 17 is a cross-sectional view of an electronic component assembly 1700 including stackable via package 100 of FIGS. 1, 2 during fabrication in accordance with one embodiment. Referring now to FIG. 17, a larger substrate 1750 such as a printed circuit motherboard includes a terminal 1752 formed on a first surface 1750L of larger substrate 1750. An electrically conductive interconnection ball 1754 is formed on terminal 1752. Illustratively, interconnection ball 1754 is formed of solder or solder paste. First surface 1750L further includes a solder mask 1756. Solder mask 1756 is patterned to expose terminal 1752.



FIG. 18 is a cross-sectional view of electronic component assembly 1700 of FIG. 17 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 17 and 18 together, interconnection ball 1754 is placed in contact with solder ball 122 as illustrated in FIG. 17. Assembly 1700 is heated to reflow interconnection ball 1754 and solder ball 122 forming solder column 1858 as illustrated in FIG. 18.


More particularly, interconnection ball 1754 and solder ball 122, e.g., solder, are heated to melt interconnection ball 1754 and solder ball 122. Upon melting, interconnection ball 1754 and solder ball 122 combine into a single molten structure, e.g., molten solder. This molten structure cools and forms solder column 1858. In accordance with this embodiment, solder column 1858 is integral, i.e., is a single unitary structure and not a plurality of different layers connected together.


Gases released during reflow of solder ball 122 are readily vented thus avoiding solder deformation of solder column 1858. Further, solder bridging (shorts) between adjacent solder columns 1858 is also avoided by the structure of via aperture 230. More particularly, by forming via aperture 230 with via aperture shelf 234, in the event that there is excess solder during the solder reflow, via aperture 230 provides space for capture of the excess solder. This avoids the excess solder from overflowing on top of principal surface 124P of package body 124 and shorting to adjacent solder columns 1858.


Solder column 1858 physically and electrically connects terminal 228 of stackable via package 100 with terminal 1752 of larger substrate 1750. Further, package body 124 defines the shape of solder column 1858 at terminal 228. More particularly, solder ball contact surface 240 of package body 124 defines the opening in package body 124 to terminal 228. Solder column 1858 fills this opening, which defines the shape of solder column 1858 at terminal 228.


Further, terminal 1752 and solder mask 1756 of larger substrate 1750 define the shape of solder column 1858 at terminal 1752. More particularly, terminal 1752 is solder wettable, whereas solder mask 1756 is not. Accordingly, solder column 1858 wets (directly contacts and adheres to) terminal 1752 and does not wet (does not contact or adhere to) solder mask 1756. Accordingly, terminal 1752 and solder mask 1756 define the shape of solder column 1858 at terminal 1752.


By defining the shape of solder column 1858 at terminals 228, 1752, reliability in the formation of solder column 1858 is maximized.



FIG. 19 is a cross-sectional view of an electronic component assembly 1900 including a stackable via package having via aperture solder ball structure 400 of FIG. 4 during fabrication in accordance with one embodiment. Referring now to FIG. 19, electronic component assembly 1900 includes larger substrate 1750 having first surface 1750L, terminal 1752, interconnection ball 1754, and solder mask 1756 as discussed above in reference to FIGS. 17, 18, the description of which is not repeated here for purposes of simplicity of discussion.



FIG. 20 is a cross-sectional view of electronic component assembly 1900 of FIG. 19 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 19 and 20 together, interconnection ball 1754 is placed in contact with solder ball 122 as illustrated in FIG. 19. Assembly 1900 is heated to reflow interconnection ball 1754 and solder ball 122 forming solder column 2058.


More particularly, interconnection ball 1754 and solder ball 122, e.g., solder, are heated to melt interconnection ball 1754 and solder ball 122. Upon melting, interconnection ball 1754 and solder ball 122 combine into a single molten structure, e.g., molten solder. This molten structure cools and forms solder column 2058. In accordance with this embodiment, solder column 2058 is integral, i.e., is a single unitary structure and not a plurality of different layers connected together.


Gases released during reflow of solder ball 122 are readily vented through via aperture 2303 thus avoiding solder deformation of solder column 2058. Further, solder bridging (shorts) between solder column 2058 and adjacent solder columns 2058 is also avoided by the structure of via aperture 230B. More particularly, by exposing exposed portion 402 of upper surface 102U around terminal 228 and solder ball 122 through via aperture 230B, in the event that there is excess solder during the solder reflow, via aperture 230B provides space for capture of the excess solder. This avoids the excess solder from overflowing on top of principal surface 124P of package body 124 and shorting to adjacent solder columns 2058.


Solder column 2058 physically and electrically connects terminal 228 with terminal 1752 of larger substrate 1750. Further, terminal 228 and solder mask 226 of substrate 102 define the shape of solder column 2058 at terminal 228. More particularly, terminal 228 is solder wettable, whereas solder mask 226 is not. Accordingly, solder column 2058 wets (adheres to) terminal 228 and does not wet (does not adhere to) solder mask 226. Accordingly, terminal 228 and solder mask 226 define the shape of solder column 2058 at terminal 228.


As discussed above, terminal 1752 and solder mask 1756 of larger substrate 1750 define the shape of solder column 2058 at terminal 1752. By defining the shape of solder column 2058 at terminals 228, 1752, reliability in the formation of solder column 2058 is maximized.


In the embodiments illustrated in FIGS. 17, 18, 19, 20, interconnection ball 1754 is aligned with solder ball 122. More particularly, referring to FIGS. 17, 19, interconnection ball 1754 has a first axis F1 perpendicular to terminal 1752. Solder ball 122 has a second axis F2 perpendicular to terminal 228. First axis F1 is aligned with second axis F2, i.e., axis F1 and axis F2 approximately lie upon a common line. By aligning interconnection ball 1754 with solder ball 122, reliability in the formation of solder columns 1858, 2058 as illustrated in FIGS. 18, 20 is maximized.


However, a via aperture solder ball structure in accordance with one embodiment accommodates a substantial amount of misalignment between interconnection ball 1754 and solder ball 122 as discussed further below in reference to FIGS. 21, 22, 23, 24.



FIG. 21 is a cross-sectional view of electronic component assembly 1700 of FIG. 17 having misalignment between interconnection ball 1754 and solder ball 122 in accordance with one embodiment. Referring to FIG. 21, interconnection ball 1754 is misaligned with solder ball 122. More particularly, first axis F1 of interconnection ball 1754 is offset from second axis F2 of solder ball 122. Interconnection ball 1754 contacts and rests on both solder ball 122 and via aperture sidewall 232.



FIG. 22 is a cross-sectional view of electronic component assembly 1700 of FIG. 21 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 21 and 22 together, assembly 1700 is heated to reflow interconnection ball 1754 and solder ball 122 forming solder column 2258.


Solder column 2258 electrically and physically connects terminal 228 to terminal 1752. Due to the misalignment of interconnection ball 1754 and solder ball 122 and thus the misalignment of terminal 228 and terminal 1752, solder column 2258 is angled, i.e., has an angle of less than 90 degrees, with respect to upper surface 102U of substrate 102. In one embodiment, solder column 2258 rests on and contacts via aperture sidewall 232. In another embodiment, surface tension of solder column 2258 while in the molten state moves larger substrate 1750 with respect to substrate 102 thus aligning terminal 1752 to terminal 228.



FIG. 23 is a cross-sectional view of electronic component assembly 1900 of FIG. 19 having misalignment between interconnection ball 1754 and solder ball 122 in accordance with one embodiment. Referring now to FIG. 23, interconnection ball 1754 is misaligned with solder ball 122. More particularly, first axis F1 of interconnection ball 1754 is offset from second axis F2 of solder ball 122. Interconnection ball 1754 contacts and rests on both solder ball 122 and via aperture sidewall 232B.



FIG. 24 is a cross-sectional view of electronic component assembly 1900 of FIG. 23 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 23 and 24 together, assembly 1900 is heated to reflow interconnection ball 1754 and solder ball 122 forming solder column 2458.


Solder column 2458 electrically and physically connects terminal 228 to terminal 1752. Due to the misalignment of interconnection ball 1754 and solder ball 122 and thus the misalignment of terminal 228 and terminal 1752, solder column 2458 is angled, i.e., has an angle of less than 90 degrees, with respect to upper surface 102U of substrate 102. In one embodiment, solder column 2458 rests on and contacts via aperture sidewall 232B. In another embodiment, surface tension of solder column 2458 while in the molten state moves larger substrate 1750 with respect to substrate 102 thus aligning terminal 1752 to terminal 228.



FIG. 25 is a cross-sectional view of an electronic component assembly 2500 including stackable via package 100 of FIGS. 1, 2 during fabrication in accordance with one embodiment. Referring now to FIG. 25, a larger substrate 2550 such as a printed circuit motherboard includes a terminal 2552 formed on a first surface 2550L of larger substrate 2550. An electrically conductive pin 2554 is formed on terminal 2552. Illustratively, pin 2554 is formed of copper, gold, or other electrically conductive material. In one embodiment, pin 2554 is formed of a material that has a higher melting temperature than solder ball 122 allowing reflow of solder ball 122 without melting of pin 2554. First surface 2550L further includes a solder mask 2556. Solder mask 2556 is patterned to expose terminal 2552 and pin 2554.



FIG. 26 is a cross-sectional view of electronic component assembly 2500 of FIG. 25 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 25 and 26 together, pin 2554 is placed in contact with solder ball 122 as illustrated in FIG. 25. Assembly 2500 is heated to reflow solder ball 122 forming thus encasing pin 2554 in a solder column 2558 as illustrated in FIG. 26. Solder column 2558 extends between terminal 228 and terminal 2552 in this embodiment.


More particularly, solder ball 122 is heated to melt solder ball 122. Upon melting, pin 2554 passes through solder ball 122 to terminal 228. Pin 2554 provides a fixed standoff in accordance with this embodiment, e.g., ensures a fixed space between terminals 228, 2552 equal to the length of pin 2554.



FIG. 27 is a cross-sectional view of an electronic component assembly 2700 including a stackable via package having via aperture solder ball structure 400 of FIG. 4 during fabrication in accordance with one embodiment. Referring now to FIG. 27, electronic component assembly 2700 includes larger substrate 2550 having first surface 2550L, terminal 2552, pin 2554, and solder mask 2556 as discussed above in reference to FIGS. 25-26, the description of which is not repeated here for purposes of simplicity of discussion.



FIG. 28 is a cross-sectional view of electronic component assembly 2700 of FIG. 27 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 27 and 28 together, pin 2554 is placed in contact with solder ball 122 as illustrated in FIG. 27. Assembly 2700 is heated to reflow solder ball 122 thus encasing pin 2554 in solder column 2858 as illustrated in FIG. 28. Solder column 2858 extends between terminal 228 and terminal 2552 in this embodiment.


The drawings and the forgoing description gave examples of the present invention. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.

Claims
  • 1. An electronic package comprising: a substrate comprising a first substrate side facing a first vertical direction;a terminal on the first substrate side;a package interconnect on the terminal; anda package body on the first substrate side and laterally surrounding the package interconnect,wherein: the package body comprises an aperture in which at least a portion of the package interconnect is positioned, the aperture being defined by an interior sidewall of the package body; andin a vertical cross-section, the interior sidewall comprises: a first sidewall portion that contacts the package interconnect and comprises a non-zero concave curvature; anda second sidewall portion that does not contact the package interconnect and is more horizontal than the first sidewall portion.
  • 2. The electronic package of claim 1, wherein the package body comprises a molding material.
  • 3. The electronic package of claim 1, wherein the conductive ball is approximately spherical.
  • 4. The electronic package of claim 1, wherein in the vertical cross-section, the interior sidewall comprises a third sidewall portion that does not contact the package interconnect, and wherein the second sidewall portion is positioned vertically between the first sidewall portion and the third sidewall portion.
  • 5. The electronic package of claim 4, wherein in the vertical cross-section, the third sidewall portion is straighter than the first sidewall portion.
  • 6. The electronic package of claim 1, wherein the package interconnect comprises a solder.
  • 7. The electronic package of claim 1, wherein at a point of maximum lateral width of the package interconnect, the package interconnect is free of contact with the package body.
  • 8. A method of forming an electronic package, the method comprising: providing a first structure comprising: a substrate comprising a first substrate side facing a first vertical direction;a terminal on the first substrate side; anda package interconnect on the terminal; andforming a package body on the first substrate side and laterally surrounding the package interconnect,wherein: the package body comprises an aperture in which at least a portion of the package interconnect is positioned, the aperture being defined by an interior sidewall of the package body; andin a vertical cross-section, the interior sidewall comprises: a first sidewall portion that contacts the package interconnect and comprises a non-zero curvature, the first sidewall portion defining a first portion of the aperture having a first maximum width; anda second sidewall portion that does not contact the package interconnect, the second sidewall portion directly vertically adjacent the first sidewall portion, the second sidewall portion defining a second portion of the aperture having a second maximum width that is greater than the first maximum width.
  • 9. The method of claim 8, wherein said forming the package body comprises molding an encapsulating material around the package interconnect, such that at least a portion of package interconnect is positioned in an aperture of the encapsulating material.
  • 10. The method of claim of 9, wherein said forming the package body comprises, after said molding the encapsulating material, expanding the aperture.
  • 11. The method of claim 8, wherein in the vertical cross-section, the interior sidewall comprises a third sidewall portion defining a third portion of the aperture having a third maximum width that is greater than the second maximum width.
  • 12. The method of claim 11, wherein in the vertical cross-section, the second sidewall portion is positioned vertically between the first sidewall portion and the third sidewall portion.
  • 13. The method of claim 8, wherein the package interconnect comprises a solder.
  • 14. The method of claim 8, wherein at a point of maximum lateral width of the package interconnect, the package interconnect is free of contact with the package body.
  • 15. A method of manufacturing an electronic device, the method comprising: providing a first structure comprising: a substrate comprising a first substrate side facing a first vertical direction;a first interconnection structure coupled to the first substrate side, the first interconnection structure comprising a first solder; andan encapsulating material on the first substrate side and laterally surrounding the first solder, the encapsulating material comprising a first encapsulation side facing the first vertical direction, and a second encapsulation side facing the substrate,where the first solder is entirely confined to an aperture;enlarging the aperture around the first interconnection structure; andafter said enlarging the aperture, coupling a second solder to the first solder.
  • 16. The method of claim 15, wherein said enlarging the aperture comprises laser ablating a portion of the encapsulating material around the first interconnection structure.
  • 17. The method of claim 15, wherein the aperture is defined by an inner sidewall of the encapsulating material, the inner sidewall comprising, in a vertical cross-section: a first sidewall portion that laterally narrows from the first encapsulation side toward the second encapsulation side;a third sidewall portion that contacts the first interconnection structure; anda second sidewall portion between the first sidewall portion and the third sidewall portion, where the second sidewall portion is more horizontal then the first and third sidewall portions.
  • 18. The method of claim 15, wherein at a point of maximum lateral width of the first interconnection structure, the first interconnection structure is free of contact with the encapsulating material.
  • 19. The method of claim 15, wherein the first substrate side comprises a first terminal; the first interconnection structure is coupled to the first terminal; the first structure comprises a solder mask material that contacts and laterally surrounds the first terminal such that no portion of the first interconnection structure contacts a lateral surface of the first terminal.
  • 20. The method of claim 15, wherein before said coupling the second solder to the first solder, no portion of the first solder protrudes from the first encapsulation side.
  • 21. The method of claim 15, wherein after said coupling the second solder to the first solder, the coupled second solder and first solder form an elongated solder structure.
  • 22. The method of claim 15, wherein the aperture comprises an aperture through only the encapsulating material.
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

The present application is a continuation of U.S. patent application Ser. No. 16/774,233, filed Jan. 28, 2020, and titled “STACKABLE VIA PACKAGE AND METHOD,” expected to issue as U.S. Pat. No. 11,089,685; which is a continuation of co-pending U.S. patent application Ser. No. 16/272,135, filed Feb. 11, 2019, and titled “STACKABLE VIA PACKAGE AND METHOD,” now U.S. Pat. No. 10,548,221; which is a continuation of U.S. application Ser. No. 16/042,312, filed Jul. 23, 2018, and titled “STACKABLE VIA PACKAGE AND METHOD,” now U.S. Pat. No. 10,206,285; which is a continuation of U.S. application Ser. No. 15/670,908, filed Aug. 7, 2017, and titled “STACKABLE VIA PACKAGE AND METHOD,” now U.S. Pat. No. 10,034,372; which is a continuation of U.S. application Ser. No. 14/657,032, filed Mar. 13, 2015, and titled “STACKABLE VIA PACKAGE AND METHOD,” now U.S. Pat. No. 9,730,327; which is a continuation of U.S. application Ser. No. 14/246,286, filed Apr. 7, 2014, and titled “STACKABLE VIA PACKAGE AND METHOD, now U.S. Pat. No. 9,012,789; which is a continuation of U.S. application Ser. No. 13/528,206, filed Jun. 20, 2012, and titled “STACKABLE VIA PACKAGE AND METHOD,” now U.S. Pat. No. 8,704,368; which is a continuation of U.S. application Ser. No. 12/483,913, filed Jun. 12, 2009, and titled “STACKABLE VIA PACKAGE AND METHOD,” now U.S. Pat. No. 8,222,538. Each of the above-mentioned applications is hereby incorporated herein by reference in its entirety.

US Referenced Citations (188)
Number Name Date Kind
3868724 Perrino Feb 1975 A
3916434 Garboushian Oct 1975 A
4322778 Barbour et al. Mar 1982 A
4532419 Takeda Jul 1985 A
4642160 Burgess Feb 1987 A
4645552 Vitriol et al. Feb 1987 A
4685033 Inoue Aug 1987 A
4706167 Sullivan Nov 1987 A
4716049 Patraw Dec 1987 A
4786952 Maclver et al. Nov 1988 A
4806188 Rellick Feb 1989 A
4811082 Jacobs et al. Mar 1989 A
4897338 Spicciati et al. Jan 1990 A
4905124 Banjo et al. Feb 1990 A
4964212 Deroux-Dauphin et al. Oct 1990 A
4974120 Kodai et al. Nov 1990 A
4996391 Schmidt Feb 1991 A
5021047 Movern Jun 1991 A
5072075 Lee et al. Dec 1991 A
5072520 Nelson Dec 1991 A
5081520 Yoshii et al. Jan 1992 A
5091769 Eichelberger Feb 1992 A
5108553 Foster et al. Apr 1992 A
5110664 Nakanishi et al. May 1992 A
5191174 Chang et al. Mar 1993 A
5229550 Bindra et al. Jul 1993 A
5239448 Perkins et al. Aug 1993 A
5247429 Iwase et al. Sep 1993 A
5250843 Eichelberger Oct 1993 A
5278726 Bemardoni et al. Jan 1994 A
5283459 Hirano et al. Feb 1994 A
5288944 Bronson Feb 1994 A
5353498 Fillion et al. Oct 1994 A
5371654 Beaman et al. Dec 1994 A
5379191 Carey et al. Jan 1995 A
5404044 Booth et al. Apr 1995 A
5463253 Waki et al. Oct 1995 A
5474957 Urushima Dec 1995 A
5474958 Djennas et al. Dec 1995 A
5497033 Fillion et al. Mar 1996 A
5508938 Wheeler Apr 1996 A
5530288 Stone Jun 1996 A
5531020 Durand et al. Jul 1996 A
5546654 Wojnarowski et al. Aug 1996 A
5574309 Papapietro et al. Nov 1996 A
5581498 Ludwig et al. Dec 1996 A
5582858 Adamopoulos et al. Dec 1996 A
5616422 Ballard et al. Apr 1997 A
5637832 Danner Jun 1997 A
5674785 Akram et al. Oct 1997 A
5719749 Stopperan Feb 1998 A
5726493 Yamashita et al. Mar 1998 A
5739581 Chillara Apr 1998 A
5739585 Akram et al. Apr 1998 A
5739588 Ishida et al. Apr 1998 A
5742479 Asakura Apr 1998 A
5774340 Chang et al. Jun 1998 A
5784259 Asakura Jul 1998 A
5798014 Weber Aug 1998 A
5822190 Iwasaki Oct 1998 A
5826330 Isoda et al. Oct 1998 A
5835355 Dordi Nov 1998 A
5847453 Uematsu et al. Dec 1998 A
5883425 Kobayashi Mar 1999 A
5894108 Mostafazadeh et al. Apr 1999 A
5903052 Chen et al. May 1999 A
5907477 Tuttle et al. May 1999 A
5936843 Ohshima et al. Aug 1999 A
5952611 Eng et al. Sep 1999 A
6004619 Dippon et al. Dec 1999 A
6013948 Akram et al. Jan 2000 A
6021564 Hanson Feb 2000 A
6028364 Ogino et al. Feb 2000 A
6034427 Lan et al. Mar 2000 A
6035527 Tamm Mar 2000 A
6040622 Wallace Mar 2000 A
6060778 Jeong et al. May 2000 A
6069407 Hamzehdoost May 2000 A
6072243 Nakanishi Jun 2000 A
6081036 Hirano et al. Jun 2000 A
6119338 Wang et al. Sep 2000 A
6122171 Akram et al. Sep 2000 A
6127833 Wu et al. Oct 2000 A
6137062 Zimmerman Oct 2000 A
6160705 Stearns et al. Dec 2000 A
6172419 Kinsman Jan 2001 B1
6175087 Keesler et al. Jan 2001 B1
6184463 Panchou et al. Feb 2001 B1
6194250 Melton et al. Feb 2001 B1
6204453 Fallon et al. Mar 2001 B1
6214641 Akram Apr 2001 B1
6235554 Akram et al. May 2001 B1
6239485 Peters et al. May 2001 B1
D445096 Wallace Jul 2001 S
D446525 Okamoto et al. Aug 2001 S
6274821 Echigo et al. Aug 2001 B1
6280641 Gaku et al. Aug 2001 B1
6307161 Grube et al. Oct 2001 B1
6316285 Jiang et al. Nov 2001 B1
6329609 Kaja et al. Dec 2001 B1
6351031 Iijima et al. Feb 2002 B1
6353999 Cheng Mar 2002 B1
6365962 Liang Apr 2002 B1
6365975 DiStefano et al. Apr 2002 B1
6376906 Asai et al. Apr 2002 B1
6392160 Andry et al. May 2002 B1
6395578 Shin et al. May 2002 B1
6405431 Shin et al. Jun 2002 B1
6406942 Honda Jun 2002 B2
6407341 Anstrom et al. Jun 2002 B1
6407930 Hsu Jun 2002 B1
6448510 Neftin et al. Sep 2002 B1
6451509 Keesler et al. Sep 2002 B2
6479762 Kusaka Nov 2002 B2
6497943 Jimarez et al. Dec 2002 B1
6517995 Jacobson et al. Feb 2003 B1
6534391 Huemoeller et al. Mar 2003 B1
6544638 Fischer et al. Apr 2003 B2
6573598 Ohuchi et al. Jun 2003 B2
6586682 Strandberg Jul 2003 B2
6608757 Bhatt et al. Aug 2003 B1
6660559 Huemoeller et al. Dec 2003 B1
6715204 Tsukada et al. Apr 2004 B1
6727645 Tsujimura et al. Apr 2004 B2
6730857 Konrad et al. May 2004 B2
6734542 Nakatani et al. May 2004 B2
6740964 Sasaki May 2004 B2
6753612 Adae-Amoakoh et al. Jun 2004 B2
6774748 Ito et al. Aug 2004 B1
6787443 Boggs et al. Sep 2004 B1
6803528 Koyanagi Oct 2004 B1
6815709 Clothier et al. Nov 2004 B2
6815739 Huff et al. Nov 2004 B2
6838776 Leal et al. Jan 2005 B2
6888240 Towle et al. May 2005 B2
6919514 Konrad et al. Jul 2005 B2
6921968 Chung Jul 2005 B2
6921975 Leal et al. Jul 2005 B2
6931726 Boyko et al. Aug 2005 B2
6953995 Farnworth et al. Oct 2005 B2
7015075 Fay et al. Mar 2006 B2
7030469 Mahadevan et al. Apr 2006 B2
7081661 Takehara et al. Jul 2006 B2
7125744 Takehara et al. Oct 2006 B2
7185426 Hiner et al. Mar 2007 B1
7198980 Jiang et al. Apr 2007 B2
7215026 Park et al. May 2007 B2
7242081 Lee Jul 2007 B1
7282394 Cho et al. Oct 2007 B2
7285855 Foong Oct 2007 B2
7345361 Mallik et al. Mar 2008 B2
7372151 Fan et al. May 2008 B1
7429786 Kamezos et al. Sep 2008 B2
7459202 Magera et al. Dec 2008 B2
7548430 Huemoeller et al. Jun 2009 B1
7550857 Longo et al. Jun 2009 B1
7633765 Scanlan et al. Dec 2009 B1
7642133 Wu et al. Jan 2010 B2
7671457 Hiner et al. Mar 2010 B1
7777351 Berry et al. Aug 2010 B1
7825520 Longo et al. Nov 2010 B1
7960827 Miller, Jr. et al. Jun 2011 B1
8115316 Kohara Feb 2012 B2
8222538 Yoshida et al. Jul 2012 B1
8341835 Huemoeller et al. Jan 2013 B1
8704368 Yoshida et al. Apr 2014 B1
9012789 Yoshida et al. Apr 2015 B1
9730327 Yoshida et al. Aug 2017 B1
20020017712 Bessho et al. Feb 2002 A1
20020061642 Haji et al. May 2002 A1
20020066952 Taniguchi et al. Jun 2002 A1
20020195697 Mess et al. Dec 2002 A1
20030025199 Wu et al. Feb 2003 A1
20030128096 Mazzochette Jul 2003 A1
20030141582 Yang et al. Jul 2003 A1
20030197284 Khiang et al. Oct 2003 A1
20030201309 Grigg et al. Oct 2003 A1
20040063246 Kamezos Apr 2004 A1
20040145044 Sugaya et al. Jul 2004 A1
20040159462 Chung Aug 2004 A1
20040165362 Farnworth Aug 2004 A1
20050139985 Takahashi Jun 2005 A1
20050184371 Yang Aug 2005 A1
20050242425 Leal et al. Nov 2005 A1
20070273049 Khan et al. Nov 2007 A1
20070281471 Hurwitz et al. Dec 2007 A1
20070290376 Zhao et al. Dec 2007 A1
20080230887 Sun et al. Sep 2008 A1
Foreign Referenced Citations (5)
Number Date Country
05-109975 Apr 1993 JP
05-136323 Jun 1993 JP
07-017175 Jan 1995 JP
08-190615 Jul 1996 JP
10-334205 Dec 1998 JP
Non-Patent Literature Citations (5)
Entry
BM Technical Disclosure Bulletin, “Microstructure Solder Mask by Means of a Laser”, vol. 36, Issue 11, p. 589, Nov. 1, 1993. (NN9311589).
Kim et al., “Application of Through Mold Via (TMV) as PoP base package”, 58.sup.th ECTC Proceedings, May 2008, Lake Buena Vista, FL, 6 pages, IEEE.
Scanlan, “Package-on-package (PoP) with Through-mold Vias”, Advanced Packaging, Jan. 2008, 3 pages, vol. 17, Issue 1, PennWell Corporation.
Hiner et al., “Printed Wiring Motherboard Having Bonded Interconnect Redistribution Mesa”, U.S. Appl. No. 10/992,371, filed Nov. 18, 2004.
Huemoeller et al., “Build Up Motherboard Fabrication Method and Structure”, U.S. Appl. No. 11/824,395, filed Jun. 29, 2007.
Related Publications (1)
Number Date Country
20220117087 A1 Apr 2022 US
Continuations (8)
Number Date Country
Parent 16774233 Jan 2020 US
Child 17395893 US
Parent 16272135 Feb 2019 US
Child 16774233 US
Parent 16042312 Jul 2018 US
Child 16272135 US
Parent 15670908 Aug 2017 US
Child 16042312 US
Parent 14657032 Mar 2015 US
Child 15670908 US
Parent 14246286 Apr 2014 US
Child 14657032 US
Parent 13528206 Jun 2012 US
Child 14246286 US
Parent 12483913 Jun 2009 US
Child 13528206 US