Contolini et al., "Embedded Conductors by Electrochemical Planarization", Abstract No. 184, Abstracts from the Spring Electrochemical Society Meeting, Los Angeles, Calif., May 7, 1989. |
Pai et al., "A Planarization Metallization Process Using Selective Electroless Deposition and Spin-On Glass", Abstract No. 481, Fall Meeting, Electrochemical Society, Honolulu, Hi., Oct. 23, 1987, p. 678. |
Mutter, "Choice Stop Material for Chemical/Mechanical Polish Planarization", IBM Technical Disclosure Bulletin, vol. 27, No. 8, Jan. 1985. |
Koburger, "Trench Planarization Technique", IBM Technical Disclosure Bulletin, vol. 27, No. 6, p. 3242, Nov. 1984. |
Rothman et al., "Lift-Off Process to Form Planar Metal/Sputtered SiO2 Structures", Jun. 25-26, 1985, V-MIC Conference, pp. 131-137, Jun. 1985. |
Beyer et al., "Glass Planarization by Stop-Layer Polishing", IBM Technical Disclosure Bulletin, vol. 27, No. 8, pp. 4700-4701, Jan. 1985. |
Bennett et al., "Selective Planarization Process and Structures", IBM Technical Disclosure Bulletin, vol. 27, No. 4B, pp. 2560-2563, Sep. 1984. |
Author unknown, "Chemical Vapor Deposited Device Isolation with Chemical/Mechanical Planarization", IBM Technical Disclosure Bulletin, vol. 29, No. 2, pp. 577-579, Jul. 1986. |
Chakravorty et al., "Photosensitive Polyimide as a Dielectric in High Density Thin Film Copper-Polyimide Interconnect Structures", The Electrochemical Society Extended Abstracts, vol. 88-1, Abstract No. 54, pp. 77-78, May, 1988. |
Ting, "Electroless Deposition for Integrated Circuit Fabrication", Abstract No. 512, Fall Meeting, Electrochemical Society, Honolulu, Hi., Oct. 23, 1987, p. 720. |
Wu, "PRAIRE--A New Planarization Technique and It's Applications in VLSI Multilevel Interconnection", Proceedings of the Symposium on Multilevel Interconnection, and Contact Technologies: Electrochemical Society, vol. 87-4, pp. 239-249, 1987. |
Riley et al., "Planarization of Dielectric Layers for Multilevel Metallization", IEEE Transactions on Semiconductor Manufacturing, vol. 1, No. 4, Nov. 1988. |
Iwasaki et al., "A Pillar-Shaped Via Structure in a Cu-Polyimide Multilayer Substrate", IEEE/CHMT '89 Japan IEMT Symposium, pp. 128-131, 1989. |
Broadbent et al., "High-Density High-Reliability Tungsten Interconnection by Filled Interconnect Groove Metallization", IEEE Transactions on Electron Devices, vol. 35, No. 7, pp. 952-956, Jul. 1988. |
"Lithographic Patterns with a Barrier Liner", IBM Technical Disclosure Bulletin, vol. 32, No. 10B, Mar. 1990, pp. 114-115. |