Patent Application
20140306331
Various embodiments relate generally to a chip, a chip arrangement, and a method for manufacturing the same.
Power semiconductor chips may be integrated into an electronic package, e.g. a through-hole-package (THP) or a surface-mounted-device (SMD).
In some approaches, bond wires, e.g., in the power package 100, are replaced by means of clips or by means of galvanic re-distribution or re-wiring. These measures may improve the maximum current carrying capability due to the increase of the cross-section. However, the thermal chip limitation remains comparable to the bond wire re-distribution, since this is dominated by the leadframe (LF) and the corresponding chip connection.
Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
The word “over” used with regards to a deposited material formed “over” a side or surface, may be used herein to mean that the deposited material may be formed “directly on”, e.g. in direct contact with, the implied side or surface. The word “over” used with regards to a deposited material formed “over” a side or surface, may be used herein to mean that the deposited material may be formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the deposited material.
Various embodiments may provide a chip and a chip arrangement, in which the chip re-wiring or re-distribution is improved electrically and thermally for a power chip package. Various embodiments may provide a three-dimensional (3D) Chip-Redistribution for power packages.
The chip 200 may include a body 202 having two main surfaces 204, 206 (e.g. the top main surface 204 and the bottom main surface 206) and a plurality of side surfaces 208.
The chip 200 may further include a first power electrode 212 extending over at least one main surface 204, 206 and at least one side surface 208 of the body 202; and a second power electrode 214 extending over at least one main surface 204, 206 and at least one side surface 208 of the body. In the embodiments shown in
In various embodiments, at least one of the first power electrode 212 and the second power electrode 214 may extend over at least a portion of a plurality of the side surface 208 of the body 202.
In various embodiments, at least one of the first power electrode 212 and the second power electrode 214 may extend over a portion of both main surfaces 204, 206 of the body 202.
In various embodiments, at least one of the first power electrode 212 and the second power electrode 214 may extend over at least one main surface 204, 206 and at least one side surface 208 of the body through a solderable layer 210.
In various embodiments, the first power electrode 212 and the second power electrode 214 may have a symmetric arrangement. For example, as shown in
At least one of the first power electrode 212 and the second power electrode 214 may be made of a metal such as e.g. a metal selected from a group of metals consisting of: Cu, Ni, Ti, Au, Ag, Pd, Pt, W.
Similar to the chip 200 of
Similar to various embodiments of
Similar to various embodiments of
According to various embodiments, the chip 300 may be configured as a power transistor.
In various embodiments, the chip 300 may further include a control electrode 316 of the power transistor. In various embodiments, the control electrode 316 and both power electrodes 212, 214 may be arranged on the same main surface of the body 202, e.g. on the main surface 204. In various embodiments, the control electrode 316 may also be arranged on the other main surface of the body 202 than the power electrodes 212, 214, e.g. on the other main surface 206.
According to various embodiments, the chip 300 may be configured as a power field effect transistor, e.g., a power MOSFET (metal oxide semiconductor field effect transistor) or a JFET (junction field effect transistor). The first power electrode 212 may be a source electrode (e.g. denoted by S in
According to various embodiments, the chip 300 may be configured as a bipolar transistor. The first power electrode 212 may be an emitter electrode, the second power electrode 214 may be a collector electrode, and the control electrode 316 may be a base electrode.
According to various embodiments, the chip 300 may be configured as an insulated gate bipolar transistor (IGBT). The first power electrode 212 may be an emitter electrode, the second power electrode 214 may be a collector electrode, and the control electrode 316 may be a gate electrode.
In various embodiments, the chip may be configured as various power components, such as High Electron Mobility Transistors (HEMT), e.g., GaN (Gallium Nitride) HEMT, SiC (Silicon Carbide) HEMT, or High-voltage Si (Silicon) HEMT; or low-voltage (e.g., smaller than 200V) MOSFET (p-channel or n-channel), e.g. SFET (silicon field effect transistor).
According to various embodiments, the chip 300 may further include a plurality of through holes or vias 318 extending from at least one of the first power electrode 212 and the second power electrode 214 through the body 202 to the other main surface 206 of the body 202, wherein the vias may be filled with or include electrically conductive material such as e.g. metal such as e.g. Cu.
As shown in
The chip 200 may have the same structure as the chip 200 of
In various embodiments, at least one of the first power electrode 212 and the second power electrode 214 may extend over at least one main surface and at least one side surface of the body 202 through a solderable layer 210.
In various embodiments, the chip 200 may be attached to the chip carrier 420 through a solder layer 430. In various embodiments, the solder layer 430 may be formed over the solderable layer 210 of the chip 200, so as to attach the chip 200 to the chip carrier 420.
According to various embodiments, the chip carrier 420 may be one of an FR4 substrate; a direct copper bond (DCB) substrate; and an isolated metal substrate (IMS), for example.
In various embodiments, the chip carrier 420 may be a leadframe. The leadframe may be made of a metal or a metal alloy, e.g. including a material selected from a group consisting of: copper (Cu), iron nickel (FeNi), steel, and the like. In various embodiments, the chip carrier 420 may be a structured leadframe. The leadframe may be structured to include a plurality of portions or blocks separate from each other, and/or may be structured to provide a desired creepage distance, which may be pre-defined, e.g. depending on the characteristics of the chip 200.
According to various embodiments, the chip 200 may be a bare chip (which may also be referred to as bare die) which is an integrated circuit cut out from the wafer and is ready for packaging.
In various embodiments, the chip arrangement 400 may further include encapsulating material encapsulating the chip carrier 420 and the chip 200, as will be described in more detail below.
In the embodiments of
The chip 300 may have the same structure as the chip 300 of
In the embodiments of
In various embodiments, the control electrode 316 of the chip 300 may be re-wired or re-distributed to the chip carrier 620 via bond wire 632.
Various embodiments of the chip 300 described above are analogously valid for the chip arrangement 600.
In various embodiments, at least one of the first power electrode 212 and the second power electrode 214 may extend over at least one main surface and at least one side surface of the body through a solderable layer 210. A solder layer 630 may be formed over the solderable layer 210 of the chip 300, so as to attach or solder the chip 300 to the chip carrier 620 (e.g. a leadframe).
Similar to various embodiments described above, the chip carrier 620 may be one of an FR4 substrate; a direct copper bond (DCB) substrate; and an isolated metal substrate (IMS). In various embodiments, the chip carrier 620 may be a leadframe. The leadframe may be made of a metal or a metal alloy, e.g. including a material selected from a group consisting of: copper (Cu), iron nickel (FeNi), steel, and the like. In various embodiments, the chip carrier 620 may be a structured leadframe. The leadframe may be structured to include a plurality of portions or blocks separate from each other, and/or may be structured to provide a desired creepage distance.
According to various embodiments, the chip 300 may be a bare chip which is an integrated circuit cut out from the wafer and is ready for packaging.
In various embodiments, the chip arrangement 600 may further include encapsulating material 634 encapsulating the chip carrier 620 and the chip 300, as e.g. shown in
According to various embodiments, a chip arrangement adapted to customer requirements (e.g. requirement on creepage distance) may be provided or manufactured by means of a structured leadframe, e.g., a both-side (double-sided) structured leadframe. By way of example, the embodiments of
Different from the chip arrangement 600, the chip arrangement 700 includes a structured leadframe 720 as the chip carrier. The structured leadframe 720 may be structured such that the distance between both power electrodes, e.g. the distance between the respective leadframe portions 722, 724 electrically coupled to the power electrodes, are further increased, compared with the leadframe 620 of
The chip and the chip arrangement according to various embodiments above provide improved electrical and thermal performance, as shown in
Compared with the chip package 800 wherein both the power electrode 806 and the control electrode 808 are re-distributed by bond wires 810, the chip package 600 of various embodiments redistributes both power electrodes by means of the leadframe and redistributes the control electrode by means of a bond wire, thereby allowing an improvement of electrical and thermal performance over the chip package 800. For example, compared with the chip package 800 wherein the thermal dissipation is only in the downward direction as depicted by arrows 812, the chip package 600 may allow thermal dissipation in both downward and lateral directions as depicted by arrows 852.
According to various embodiments above, the chip redistribution is implemented in a three-dimensional (3D) manner, e.g. by extending the power electrodes over the main surface and the side surface of the chip body and by further re-distribution via the leadframe. By means of 3D chip redistribution, both electrical and thermal performance of the chip and the chip arrangement may be improved, since both power electrodes are arranged symmetrically over the chip surfaces. Based on the symmetric arrangement, the leadframe re-distribution or re-wiring for both power electrodes may be used and thus the total electro-thermal performance may be optimized. The chip and the chip arrangement of various embodiments with the 3D re-distribution may improve the chip re-distribution or re-wiring electrically and thermally for power packages.
According to various embodiments above, 3D chip-redistribution with symmetric power electrodes may be provided. According to various embodiments above, 3D chip-redistribution with both electrodes on both chip surfaces (main surface and side surface) are provided. The 3D chip-redistribution of various embodiments may be used for various power components or power chips, and may be used with structured leadframe.
In various embodiments, 3D coverage over all side surfaces may be possible. For example, though
The re-distribution on a bare chip or a bare die according to various embodiments above, e.g. by extending the power electrodes via the solderable layer, may also provide protection for the chip.
In various embodiments, the chip 200, 300 and the chip arrangement 400, 500, 600, 700 described in various embodiments above may be used for a standard chip package or an embedded chip package.
In various embodiments, the chip 200, 300 and the chip arrangement 400, 500, 600, 700 having symmetric power electrodes as described in various embodiments above may be contacted or connected directly on a substrate or a board by means of wave soldering or reflow soldering, in a comparable manner to existing SMD (surface-mounted-device) packages (e.g. PowerCSP chip-scale package).
In various embodiments, the chip 200, 300 and the chip arrangement 400, 500, 600, 700 described in various embodiments above may be used for multi-chip-modules, which may include, e.g. a half bridge circuit or a cascade circuit formed by multiple chips.
As shown in
Each of the first chip 912 and the second chip 914 may be the chip 200 of
In various embodiments, the source electrode of the GaN HEMT chip 912 may be electrically coupled with the drain electrode of the SFET chip 914, e.g. through electrical coupling of respective leads or respective portions of the leadframe 902 re-wired to the source electrode of the GaN HEMT chip 912 and the drain electrode of the SFET chip 914. In various embodiments, the gate electrode of the GaN HEMT chip 912 may be electrically coupled with the source electrode of the SFET chip 914, e.g. through a bond wire connected between the gate electrode of the GaN HEMT chip 912 and the source electrode of the SFET chip 914. The GaN HEMT chip 912 and the SFET chip 914 with such electrical coupling may form a cascade circuit as described below.
The electrical coupling among the power electrodes and control electrodes of the chips 912, 914, though not shown in detail in
In various embodiments, the chip carrier 902 may include various number of leadframe parts, depending on the required connection between the chips 912, 914 or the number of chips included in the chip arrangement 900.
In the embodiments described with reference to
The cascade circuit 950 may include a low voltage SFET 914 in common-source and a high voltage GaN-HEMT 912 in common-gate configuration. The resulting 3-port circuit may act as a switch. The drain electrode of the GaN-HEMT 912 is defining the 600V behavior of the cascade circuit 950.
The chips 912, 914 may also be connected differently to form other types of circuit instead of the cascade circuit 950 of
At 1002, a body of a chip may be provided, wherein the body includes two main surfaces and a plurality of side surfaces.
At 1004, a first power electrode may be formed extending over at least one main surface and at least one side surface of the body.
At 1006, a second power electrode may be formed extending over at least one main surface and at least one side surface of the body.
In various embodiments, at least one of the first power electrode and the second power electrode may be formed extending over at least a portion of a plurality of the side surface of the body.
In various embodiments, at least one of the first power electrode and the second power electrode may be formed extending over a portion of both main surfaces of the body.
In various embodiments, the first power electrode and the second power electrode may be formed in a symmetric arrangement.
In various embodiments, a control electrode of the chip may be formed. The control electrode and both power electrodes may be formed on the same main surface of the body, or the control electrode may be arranged on the other main surface of the body than the power electrodes.
Various embodiments described in the context of the chip above are analogously valid for the method of manufacturing a chip.
At 1102, a chip carrier may be provided.
At 1104, a chip may be arranged over the chip carrier. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body.
In various embodiments, encapsulating material may be formed encapsulating the chip carrier and the chip.
Various embodiments described in the context of the chip arrangement above are analogously valid for the method of manufacturing a chip arrangement.
Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces. The chip may further include a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body.
In various embodiments, at least one of the first power electrode and the second power electrode may extend over at least a portion of a plurality of the side surface of the body.
In various embodiments, at least one of the first power electrode and the second power electrode may extend over a portion of both main surfaces of the body.
In various embodiments, at least one of the first power electrode and the second power electrode may extend over at least one main surface and at least one side surface of the body through a solderable layer.
In various embodiments, the first power electrode and the second power electrode may have a symmetric arrangement.
At least one of the first power electrode and the second power electrode may be made of a metal selected from a group of metals consisting of: Cu, Ni, Ti, Au, Ag, Pd, Pt, W.
According to various embodiments, the chip may be configured as a power transistor.
In various embodiments, the chip may further include a control electrode of the power transistor. In various embodiments, the control electrode and both power electrodes may be arranged on the same main surface of the body. In various embodiments, the control electrode may also be arranged on the other main surface of the body than the power electrodes
According to various embodiments, the chip may be configured as a power field effect transistor, e.g., a power MOSFET (metal oxide semiconductor field effect transistor) or a JFET (junction field effect transistor). The first power electrode may be a source electrode, the second power electrode may be a drain electrode, and the control electrode may be a gate electrode.
According to various embodiments, the chip may be configured as a bipolar transistor. The first power electrode may be an emitter electrode, the second power electrode may be a collector electrode, and the control electrode may be a base electrode.
According to various embodiments, the chip may be configured as an insulated gate bipolar transistor (IGBT). The first power electrode may be an emitter electrode, the second power electrode may be a collector electrode, and the control electrode may be a gate electrode.
In various embodiments, the chip may be configured as various power components, such as High Electron Mobility Transistors (HEMT), e.g., GaN (Gallium Nitride) HEMT, SiC (Silicon Carbide) HEMT, or High-voltage Si (Silicon) HEMT; or low-voltage (e.g., smaller than 200V) MOSFET (p-channel or n-channel), e.g. SFET (silicon field effect transistor).
According to various embodiments, the chip may further include a plurality of through holes or vias extending from at least one of the first power electrode and the second power electrode 214 through the body to the other main surface of the body.
Various embodiments provide a chip arrangement. The chip arrangement may include a chip carrier and a chip arranged over the chip carrier. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body.
Various embodiments of the chip described above are analogously valid for the chip arrangement.
In various embodiments, at least one of the first power electrode and the second power electrode may extend over at least one main surface and at least one side surface of the body through a solderable layer. In various embodiments, the chip may be attached to the chip carrier through a solder layer. In various embodiments, the solder layer may be formed over the solderable layer of the chip, so as to attach the chip to the chip carrier.
According to various embodiments, the chip carrier may be one of an FR4 substrate; a direct copper bond (DCB) substrate; and an isolated metal substrate (IMS).
In various embodiments, the chip carrier may be a leadframe. The leadframe may be made of a metal or a metal alloy, e.g. including a material selected from a group consisting of: copper (Cu), iron nickel (FeNi), steel, and the like. In various embodiments, the chip carrier may be a structured leadframe. The leadframe may be structured to include a plurality of portions or blocks separate from each other, and/or may be structured to provide a desired creepage distance.
According to various embodiments, the chip may be a bare chip, e.g. an integrated circuit cut out from the wafer and is ready for packaging.
In various embodiments, the chip arrangement may further include encapsulating material encapsulating the chip carrier and the chip.
Various embodiments provide a method of manufacturing a chip. The method may include providing a body of a chip, wherein the body includes two main surfaces and a plurality of side surfaces. The method may further include forming a first power electrode extending over at least one main surface and at least one side surface of the body; and forming a second power electrode extending over at least one main surface and at least one side surface of the body.
In various embodiments, at least one of the first power electrode and the second power electrode may be formed extending over at least a portion of a plurality of the side surface of the body.
In various embodiments, at least one of the first power electrode and the second power electrode may be formed extending over a portion of both main surfaces of the body.
In various embodiments, the first power electrode and the second power electrode may be formed in a symmetric arrangement.
In various embodiments, a control electrode of the chip may be formed. The control electrode and both power electrodes may be formed on the same main surface of the body, or the control electrode may be arranged on the other main surface of the body than the power electrodes.
Various embodiments provide a method of manufacturing a chip arrangement. The method may include providing a chip carrier, and arranging a chip over the chip carrier. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body.
In various embodiments, encapsulating material may be formed encapsulating the chip carrier and the chip.
Various embodiments described in the context of the chip or the chip arrangement above are analogously valid for the method of manufacturing a chip or a chip arrangement.
While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
