Claims
- 1. A package for a semiconductor chip, comprising:
a ground conducting layer; a one metal layer interconnect substrate attached to the ground conducting layer, the one metal layer interconnect substrate having a via hole defining a path to the ground conducting layer; and a conductive material substantially filling the path defined by the via hole, the conductive material being in contact with the ground conducting layer.
- 2. A package for a semiconductor chip as recited in claim 1, wherein the conductive material is one of a solder ball, a solder paste, and conductive paste.
- 3. A package for a semiconductor chip as recited in claim 2, further comprising:
a solder ball defined over the conductive material.
- 4. A package for a semiconductor chip, comprising:
a substrate capable of conducting a ground; a single metal layer interconnect substrate attached to the substrate, the one metal layer interconnect substrate having a via hole; and a conductive material contained in the via hole, the conductive material being in contact with the substrate; wherein the conductive material defines an electrical connection to the ground.
- 5. A package for a semiconductor chip as recited in claim 4, wherein the conductive material is one of a solder ball, a solder paste, and conductive paste.
- 6. A package for a semiconductor chip as recited in claim 5, further comprising:
a solder ball defined over the conductive material.
- 7. A package for a semiconductor chip, comprising:
a substrate capable of conducting a ground; a single metal layer interconnect substrate attached to the substrate, the one metal layer interconnect substrate having a via hole; a conductive material contained in the via hole, the conductive material being in contact with the substrate; and a solder ball defined over the conductive material; wherein the conductive material defines an electrical connection to the ground.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority under 35 U.S.C. § 120 and is a continuation of U.S. patent application having application Ser. No. 09/422,212, filed Oct. 19, 1999, entitled “Methods for Forming Ground Vias in Semiconductor Packages.” application Ser. No. 09/422,212 is a continuation-in-part of U.S. patent application having application Ser. No. 08/892,471, now U.S. Pat. No. 6,020,637, filed Jul. 14, 1997, entitled “Ball Grid Array Semiconductor Package and Method for Making the Same.” The contents of each of these prior applications is hereby incorporated by reference.
Continuations (1)
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Number |
Date |
Country |
Parent |
09422212 |
Oct 1999 |
US |
Child |
10013177 |
Dec 2001 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
08892471 |
Jul 1997 |
US |
Child |
09422212 |
Oct 1999 |
US |