Claims
- 1. A leadless plastic chip carrier comprising:
a plurality of die attach pads; a semiconductor die mounted to said plurality of die attach pads; at least one row of contact pads circumscribing said plurality of die attach pads; a power/ground ring intermediate said at least one row of contact pads and said ground plane; a plurality of wire bonds connecting various ones of said semiconductor die, said contact pads and said power/ground ring; and an overmold covering said semiconductor die, said plurality of die attach pads, said power/ground ring and said contact pads such that each of said die attach pads and said contact pads has one exposed surface.
- 2. The leadless plastic chip carrier according to claim 1 wherein said plurality of die attach pads and said at least one row of contact pads comprise a plurality of metal layers.
- 3. The leadless plastic chip carrier according to claim 2 wherein each of said plurality of die attach pads are separated by a photo-imageable mask.
- 4. The leadless plastic chip carrier according to claim 2 wherein said plurality of metal layers comprises successive layers of Au, Ni, Cu, Ni and Au.
- 5. The leadless plastic chip carrier according to claim 2 wherein said plurality of metal layers comprises successive layers of Au, Ni, Cu and Ag.
- 6. The leadless plastic chip carrier according to claim 2 wherein said plurality of metal layers comprises successive layers of Sn, Cu, Ni and Au.
- 7. The leadless plastic chip carrier according to claim 2 wherein said plurality of metal layers comprises successive layers of Sn, Cu, and Ag.
- 8. The leadless plastic chip carrier according to claim 1 wherein said plurality of die attach pads comprises an array of similarly sized pads.
- 9. The leadless plastic chip carrier according to claim 1 wherein said plurality of die attach pads, said at least one row of contact pads, and said power/ground ring comprises an array of similarly sized pads.
- 10. The leadless plastic chip carrier according to claim 9 wherein said array of similarly sized pads comprises an array of rectangular pads.
- 11. The leadless plastic chip carrier according to claim 10 wherein said array of similarly sized pads comprises an array of round pads.
- 12. The leadless plastic chip carrrier according to claim 2, wherein said at least one row of contact pads is recessed from said photo-imageable mask in a plurality of etch-down cavities.
- 13. The leadless plastic chip carrier according to claim 12, further comprising a plurality of solder balls disposed in said each of said etch-down cavities
- 14. A process for fabricating a leadless plastic chip carrier, having the steps of:
depositing a photo-imageable mask on a first surface of a leadframe strip; imaging and developing said mask to define a plurality of die attach pads, at least one row of contact pads and a power/ground ring intermediate said die attach pads and said contact pads; depositing a plurality of layers on portions of said first surface exposed by said imaging and said developing for creating said at least one row of contact pads, said power/ground ring and said plurality of die attach pads; mounting said semi-conductor die to said die attach pads on a top surface thereof; wire bonding said semiconductor die to said contact pads; encapsulating said mask, said layers, and said die between a moulding compound and said first surface of said leadframe strip; etching back a bottom surface of said leadframe strip for exposing said contact pads and said die attach pads; singulating said leadless plastic chip carrier from said leadframe strip.
- 15. The process for fabricating a leadless plastic chip carrier according to claim 14 wherein said photo-imageable mask is also exposed in said etching step.
- 16. The process for fabricating a leadless plastic chip carrier according to claim 14 wherein said step of depositing said plurality of layers comprises depositing successive layers of Au, Ni, Cu, Ni, and Au.
- 17. The process for fabricating a leadless plastic chip carrier according to claim 14 wherein said step of depositing said plurality of layers comprises depositing successive layers of Au, Ni, Cu and Ag.
- 18. The process for fabricating a leadless plastic chip carrier according to claim 14 wherein said step of depositing said plurality of layers comprises depositing successive layers of Sn, Cu, Ni and Au.
- 19. The process for fabricating a leadless plastic chip carrier according to claim 14 wherein said step of depositing said plurality of layers comprises depositing successive layers of Sn, Cu and Ag.
- 20. The process for fabricating a leadless plastic chip carrier according to claim 14 wherein said step of depositing said plurality of layers comprises an initial deposition of flash Cu which is etched away during said step of etching back said bottom surface of said leadframe strip to create a cavity, and further including a step of attaching solder balls to said contact pads exposed as a result of said step of etching back said bottom surface.
- 21. The process for fabricating a leadless plastic chip carrier according to claim 20 wherein said initial deposition of flash Cu is followed by depositing layers of Au, Ni, Cu, Ni and Au
- 22. The process for fabricating a leadless plastic chip carrier according to claim 20 wherein said initial deposition of flash Cu is followed by depositing layers of Au, Ni, Cu, and Ag.
- 23. A process for fabricating a leadless plastic chip carrier, having the steps of:
applying a layer of photo-resist on a first surface of a leadframe strip; exposing and developing said layer of photo-resist to define a plurality of die attach pads, at least one row of contact pads and a power/ground ring intermediate said die attach pads and said contact pads between a remainder of said photo-resist; depositing a plurality of layers on portions of said first surface exposed by said exposing and said developing for creating said at least one row of contact pads, said power/ground ring and said plurality of die attach pads; stripping said remainder of said photo-resist; depositing a photo-imageable mask on said first surface and said plurality of die attach pads; imaging and developing said mask to expose a top surface of said plurality of die attach pads; mounting said semi-conductor die to said die attach pads on said top surface; wire bonding said semiconductor die to said contact pads; encapsulating said mask, said layers, and said die between a moulding compound and said first surface of said leadframe strip; etching back a bottom surface of said leadframe strip for exposing said contact pads and said die attach pads; and singulating said leadless plastic chip carrier from said leadframe strip
- 24. The process according to claim 23 wherein said step of depositing a photo-imageable mask on said first surface and said plurality of die attach pads includes depositing said photo-imageable mask on said at least one row of contact pads and said power/ground ring
- 25. The process for fabricating a leadless plastic chip carrier according to claim 23 wherein said photo-imageable mask is also exposed in said etching step.
- 26. The process for fabricating a leadless plastic chip carrier according to claim 23 wherein said step of depositing said plurality of layers comprises depositing successive layers of Au, Ni, Cu, Ni, and Au.
- 27. The process for fabricating a leadless plastic chip carrier according to claim 23 wherein said step of depositing said plurality of layers comprises depositing successive layers of Au, Ni, Cu and Ag.
- 28. The process for fabricating a leadless plastic chip carrier according to claim 23 wherein said step of depositing said plurality of layers comprises depositing successive layers of Sn, Cu, Ni and Au.
- 29. The process for fabricating a leadless plastic chip carrier according to claim 23 wherein said step of depositing said plurality of layers comprises depositing successive layers of Sn, Cu and Ag.
- 30. The process for fabricating a leadless plastic chip carrier according to claim 23 wherein said step of depositing said plurality of layers comprises an initial deposition of flash Cu which is etched away during said step of etching back said bottom surface of said leadframe strip to create a cavity, and further including a step of attaching solder balls to said contact pads exposed as a result of said step of etching back said bottom surface.
- 31. The process for fabricating a leadless plastic chip carrier according to claim 30 wherein said initial deposition of flash Cu is followed by depositing layers of Au, Ni, Cu, Ni and Au
- 32. The process for fabricating a leadless plastic chip carrier according to claim 30 wherein said initial deposition of flash Cu is followed by depositing layers of Au, Ni, Cu, and Ag.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This is a continuation-in-part of U.S. patent application Ser. No. 09/288,352, filed Apr. 8, 1999, which is a continuation-in-part of U.S. patent application Ser. No. 09/095,803, filed Jun. 10, 1998.
Continuation in Parts (2)
|
Number |
Date |
Country |
Parent |
09288352 |
Apr 1999 |
US |
Child |
09802679 |
Mar 2001 |
US |
Parent |
09095803 |
Jun 1998 |
US |
Child |
09288352 |
Apr 1999 |
US |