The present application claims priority from Japanese patent application No. 2004-162854, filed on Jun. 1, 2004, the content of which is hereby incorporated by reference into this application.
This invention relates in general to a semiconductor device and to a method of manufacture thereof, and, more particularly, the invention relates to technology that is applicable to a semiconductor device which has a chip part and to a method of manufacture thereof.
In a conventional electronic device (semiconductor device), an integrated circuit constituent element and a non-integrated circuit constituent element, which constitute a first electric circuit and which are mutually connected, are formed as a standard package, and then covering fabrication is carried out by provision of a covering fabrication layer (for example, refer to Patent Reference 1).
A conventional electric power unit is provided with an energy supply circuit which supplies energy at a predetermined timing, and the provision of a conservation-of-energy circuit which receives the energy supplied from the energy supply circuit is important so that energy is saved (for example, refer to Patent Reference 2).
A conventional semiconductor device can supply power for every circuit part by use of a bus bar for connecting the power supply to every circuit part in a semiconductor chip. By efficiently employing the use of a bus bar which is connectable regardless of the pitch of inner leads, making the pitch of pads smaller than the pitch of the inner leads, and providing an alternating pad arrangement, the number of pads for the supply of power can be increased, or a lead which has been conventionally used for the supply of power can be used for signals (for example, refer to Patent Reference 3).
[Patent Reference 1] Japanese Unexamined Patent Publication No. Hei 10(1998)-209365 (FIG. 1)
[Patent Reference 2] Japanese Unexamined Patent Publication No. 2002-305248 (FIG. 1)
[Patent Reference 3] WO 03/105226 A1 Official Report (FIG. 56)
Generally, since a parasitic element (R/C/L) as used in a semiconductor device tends to become large, a big mounting area, about which a part for the loss is considered, is needed in the circuit in which a semiconductor chip is combined with an external element. That is, in order to prevent the performance from falling due to a parasitic element, a big area is needed for mounting such elements.
This inventor has considered the miniaturization of a semiconductor device which has a chip part. As a result, a problem has been formed in that it is difficult to incorporate a chip part in a general-purpose type semiconductor device, and the package size becomes special as well.
This inventor has found a further problem in that, when an external element is an inductance element especially, if the inductance element is formed on a semiconductor chip, the area occupied by the inductance element will become large and the semiconductor chip will be enlarged, with the result that a cost overrun is caused because the yield of the semiconductor chip drops, or the number of picking of the semiconductor chip decreases.
Although Patent Reference 1 (Japanese Unexamined Patent Publication No. Hei 10(1998)-209365) describes a structure in which chip parts are consolidated with a semiconductor chip, there is no statement therein about technology which aims at effective use of the space in a semiconductor package.
Although Patent Reference 2 (Japanese Unexamined Patent Publication No. 2002-305248) describes technology in which a DC-DC converter is provided in which an inductance element was formed on a semiconductor chip, in an effort to obtain an improvement in the conversion efficiency, there is no statement therein about technology which prevents enlargement of the semiconductor chip.
Although Patent Reference 3 (WO 03/105226 A1 Official Report) describes a structure in which a ring-like bus bar is arranged between chip inner leads and a semiconductor element, there is no statement therein about a structure in which a chip part is embedded in the package.
An object of the present invention is to provide a semiconductor device and a method of manufacture thereof which can attain miniaturization in a semiconductor device which has a chip part.
Another object of the present invention is to provide a semiconductor device and method of manufacture thereof which can attain an improvement in an electrical property in a semiconductor device which has a chip part.
Yet another object of the present invention is to provide a semiconductor device and method of manufacture thereof which can achieve simplification of a mounting process.
The above and other objects and new features of this invention will become clear from the following description and the accompanying drawings.
An outline of a typical aspects and features of the present invention will be briefly explained.
In one aspect of the present invention, there is a semiconductor device, which comprises: a plurality of first leads; a sheet member connected to end part of each of the plurality of first leads; a semiconductor chip, having a semiconductor element and a plurality of electrodes on a main surface thereof, being arranged inside the plurality of leads, and being further connected with the sheet member; a plurality of second leads arranged around the semiconductor chip; a plurality of conductive wires which electrically connect the electrodes of the semiconductor chip and the plurality of second leads, respectively; and a chip part formed as a surface mounting part, which is arranged beneath a wire and is disposed in the area between the semiconductor chip and the plurality of first leads.
In another aspect of the present invention, there is a semiconductor device comprising: a plurality of first leads; a sheet member connected to an end part of each of the plurality of first leads; a semiconductor chip, having a semiconductor element and a plurality of electrodes on a main surface thereof, being arranged inside the plurality of first leads, and being further connected with the sheet member; a plurality of second leads arranged around the semiconductor chip; a plurality of conductive wires which electrically connect the electrodes of the semiconductor chip, and the plurality of second leads, respectively; a sealed body sealing the semiconductor chip and the plurality of wires; and a first passive part, provided with an inductance element, that is arranged outside of the semiconductor chip and inside of the sealed body.
In a further aspect of the present invention, there is a method of manufacture of a semiconductor device, which comprises the steps of: preparing a lead frame to which a sheet member and the end parts of a plurality of leads are connected via insulating adhesive; mounting a chip part as a surface mounting part in an area outside of a chip mounting part and inside of the plurality of leads on the sheet member; after mounting the chip part, mounting a semiconductor chip in the chip mounting part of the sheet member; electrically connecting each of the plurality of leads with a plurality of electrodes of a main surface of the semiconductor chip using a plurality of conductive wires, respectively; performing resin molding of the semiconductor chip and the plurality of leads, and forming a sealed body; and individually separating the plurality of leads from the lead frame.
The effect obtained by typical aspects and features of the invention will be explained briefly.
In a semiconductor device which has a chip part, the empty space beneath a connecting wire can be effectively used by arranging the chip part in the area between a semiconductor chip and a plurality of leads and under a connecting wire. Thereby, miniaturization of a semiconductor device which has a chip part can be attained. By arranging a chip part inside the sealed body of a semiconductor device, as compared with the case where a chip part is mounted outside of a semiconductor device, the loss produced by a parasitic element (R/C/L) can be reduced, and the circuit can be made highly efficient.
In the following description of the embodiments, except for the case where it is especially required, an explanation of the same element or same portion is not repeated in principle.
In the following detailed description, when there is a necessity for the sake of convenience, the subject matter of the present invention will be divided into a plurality of sections or embodiments. However, except for the case where it is clearly evident, they are not mutually unrelated and one has a relation, such that it is a modification, represents details, or is a supplementary explanation, etc. of some or all of the others.
In the following description of the embodiments, when a number of elements (a number, a numerical value, a quantity, a range, etc. are included), etc., is mentioned, except for the case where it is shown especially clearly and where it is theoretically limited to a specific number, the numerical value may be considered as more than the specific number or less than the specific number instead of being limited to the specific number.
Hereafter, various embodiments of the present invention will be explained in detail based on the accompanying drawings. In the all of the drawings, the same reference number is used to identify a component which has the same function, and a repeated explanation thereof is omitted.
The semiconductor device of this Embodiment 1, as shown in
In the case of a QFP 1 with many pins, the area per one lead Which can be provided becomes small as the end part by the side of the chip of each inner lead 5a approaches the semiconductor chip 3, and the lead density becomes high. Therefore, the distance at which the end part of each inner lead 5a can be brought close to the semiconductor chip 3 is limited. As a result, there is a tendency to provide an empty domain or space between the end part of each inner lead 5a and the semiconductor chip 3 in this basis, the QFP 1 of this Embodiment 1 effectively utilizes the empty domain between the end part of each inner lead 5a and the semiconductor chip 3 in the QFP 1 that has many pins. That is, by arranging chip parts in the empty domain or space between the semiconductor chip 3 and the end part of inner leads 5a, the QFP 1 can be miniaturized, and it becomes highly efficient.
This Embodiment 1 is directed to a case where a bar lead 5c, which is a common lead, is formed in the empty domain between the semiconductor chip 3 and the end part of the inner leads 5a.
The detailed composition of the QFP 1 will be explained. The QFP 1 is a semiconductor device which has a semiconductor chip 3, and pads 3c, which are a plurality of electrodes disposed on the main surface 3a thereof, as shown in
For example, in the QFP 1 shown in
As shown in the X section of
Next, as shown in the Y section of
The chip resistor 11, with a dumping resistance element, is arranged on the bar leads 5c like the F chip part of the Y section of
The chip resistor 11 is connected to the bar leads 5c via an insulating adhesive 28. Namely, since the electrode 11a of the chip resistor 11 and the bar leads 5c of the lower part must be insulated from each other in this case, the back 11b of the chip resistor 11 is connected to the far leads 5c via the insulating adhesives 28. Thus, a chip part, such as the chip resistor 11, can be arranged on the bar leads 5c, and the space between the chip inner leads and the semiconductor chips can be utilized effectively.
Next, the chip part of the Z section of
Next, in the modification shown in
Like the F chip part of the Y section of
Therefore, the electrodes 11a do not necessarily need to be formed on both the back and front sides of the chip resistor 11, but can just be formed on the chip resistor 11, in this case, at one side thereof.
Thereby, while being able to reduce the bounce in a signal wave form, since the chip resistor 11 serving as a dumping resistance element is positioned to intervene in the middle of the wire connection between the semiconductor chip 3 and the inner lead 5a, the wire height can be made low, since the wire connection is made to each bar lead 5c, as compared with the wire height of the F chip resistor 11 of the Y section of
The modification shown in
A modification is shown in
A modification is shown in
A protection element also may be an EMC(Electro Magnetic Compatibility) protection element which consists of a ferrite chip and is similarly used as a measure against a power supply/signal noise, for example.
Next, a semiconductor device representing a modification, in which a chip part in which an inductance element has been built, will be explained.
If it is desirable to form an inductance element on a chip in a semiconductor device, the chip area will become large and the yield will drop. Therefore, an inductance element is not formed on a chip, but the chip inductor 14 is arranged outside of the semiconductor chip 3 and inside the sealed body 7 (refer to
An example of the voltage down circuit which includes the circuit composition shown in
The semiconductor device shown in
On the other hand, the chip inductor 14 and the chip capacitor 15 are mounted on the bar lead 5c used for the supply of power, and the capacity of the power supply is strengthened with the voltage down circuit of the semiconductor device shown in
Since the control circuit 21 is included inside of a chip, as shown in
Also, in the composition shown in
According to the semiconductor device of this Embodiment 1, as mentioned above, in the QFP 1 which has chip parts, by arranging the chip parts in the area between the semiconductor chip 3 and the plurality of inner leads 5a, and beneath the wire 6, as shown in
By arranging chip parts inside the sealed body 7 of the QFP 1, the loss by a parasitic element (R/C/L) can be reduced, as compared with the case where chip parts are mounted outside of the QFP 1, and the circuit can be made highly efficient. As a result, improvement in the electrical property of the QFP 1 which has chip parts can be attained.
By arranging chip parts outside of the semiconductor chip 3 and inside of the sealed body 7, in addition to being able to control enlargement of the semiconductor chip 3, a reduction of the number of parts mounted on a mounting board can be attained. Thereby, simplification of the mounting process of the QFP 1 can be attained.
A change of an inductance element accompanying a change of product specification can be easily effected by arranging the chip inductor 14, which is the first passive part that has an inductance element, outside of the semiconductor chip 3 and inside of the sealed body 7.
Furthermore, enlargement of the semiconductor chip 3 can be prevented by arranging the chip inductor 14, which constitutes an inductance element disposed outside of the semiconductor chip 3 and inside of the sealed body 7 (referring to
In the QFP 1, the semiconductor chip 3 is formed of silicon, for example, and the wire 6 is a gold wire, for example. The sealed body 7 is formed of a thermosetting epoxy resin, for example. The inner lead 5a, the outer lead 5b, and the bar lead 5c are formed of a thin plate material in the form of a copper alloy, for example. The sheet member 8 is formed of insulating thin board material, such as a glass epoxy resin and ceramics, for example. However, the sheet member 8 also may be formed using a member in which an insulating adhesive layer is formed on a thin metal plate (heat spreader), for example.
Next, a method of manufacture of the QFP 1 of this Embodiment 1 will be explained.
First, the lead frame 5, which has inner leads 5a and outer leads 5b, constituting a plurality of leads, and a thin sheet member 8, is prepared, as shown in
Along with the lead sequence of a plurality of inner leads 5a, a plurality of bar leads 5c, which are common leads, are arranged in the lead frame 5 of this Embodiment 1 in the area outside of a chip mounting part and inside of the end parts of the plurality of inner leads 5a on the sheet member 8.
Then, chip part attachment, as shown in
In this case, if the chip parts are to be insulated from the bar leads 5c, when mounting the chip parts, such as the chip inductor 14, on the bar leads 5c, the chip inductor 14 is mounted on the bar leads 5c using an insulating adhesive, etc. To connect the chip parts with the bar leads 5c electrically, when mounting the chip parts, such as the chip inductor 14, on the bar leads 5c, the chip inductor 14 is connected on the bar leads 5c using conductive paste material, such as silver paste and solder paste.
When chip parts are mounted via silver paste, processing to bake the silver paste is performed before mounting the semiconductor chip 3, after chip part mounting is complete. On the other hand, when chip parts are mounted via solder paste, reflow processing of the solder paste is performed before mounting the semiconductor chip 3, after chip part mounting is complete.
Then, as shown in
Thus, in this Embodiment 1, since the bake processing and reflow processing after adhesion of the chip parts are performed before mounting the semiconductor chip 3, by mounting the semiconductor chip 3 after completion of mounting of the chip parts, it is possible to prevent pollution of the semiconductor chip 3.
Furthermore, stabilization of the lead frame can be attained by mounting chip parts on the lead frame 5 ahead of the semiconductor chip 3, and, since the potential for generation of defective goods, such as due to a wire short-circuit and wire cutting, is reduced, damage to the wire 6 can be prevented.
Then, wire bonding is performed as shown in
Then, a resin molding is performed, as shown in
Then, while cutting and separating a plurality of outer leads 5b and individually separating them from the lead frame 5, each outer lead 5b is bent in the shape of a gull wing, and the assembly of the QFP 1 is completed.
The semiconductor device of this Embodiment 2, as shown in
Also, in the QFN 26 of this Embodiment 2, like the QFP 1 of Embodiment 1, a chip part, such as the chip inductor 14, is mounted in the empty domain between the semiconductor chip 3 and the end parts of the inner leads 5a, and the same effect as the QFP 1 of Embodiment 1 can be attained.
As for the QFN 26 shown in
As to the other structures in the QFN 26 of this Embodiment 2, since they are the same as those of the QFP 1 of Embodiment 1, a repeated explanation thereof is omitted.
As mentioned above, although the present invention has been specifically explained based on various embodiments of this invention, it cannot be overemphasized that this invention is not limited to the embodiments of the described herein invention, and the invention can be changed variously in a range which does not deviate from the gist of the invention.
For example, as to the attachment of the chip parts in a semiconductor device according to Embodiments 1 and 2, the attachment may be a direct electrical connection using solder or silver paste, or it may be a connection using an insulating adhesion material.
As for the semiconductor device of Embodiments 1 and 2, at least one chip part may be mounted in the area between the semiconductor chip 3 and the inner leads 5a, and the chip part may be a surface mounting part, such as a capacitor, a resistor, or an inductor, etc.
Although the semiconductor device of Embodiments 1 and 2 was described for a case in which the bar lead 5c, which is a common lead, was arranged between the semiconductor chip 3 and the end parts of the inner leads 5a, the common lead of the bar lead 5c, etc., does not necessarily need to be arranged in the said semiconductor device.
The Embodiments 1 and 2 of the semiconductor device has been described for the case where a chip part, such as the chip inductor 14, is arranged between the semiconductor chip 3 and the inner leads 5a on the bar lead 5c. However, on the sheet member 8, the chip part, such as the chip inductor 14, may be arranged between the bar lead 5c and the inner leads 5a, while bringing the bar lead 5c close to the chip side and establishing space in the circumference of the sheet member 8.
This invention is suitable for application to an electronic device and a semiconductor device, and their manufacturing methods.
Number | Date | Country | Kind |
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2004-162854 | Jun 2004 | JP | national |