Patent Grant
10707150
The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a fan-out package-on-package (Fo-PoP) with printed wiring board (PWB) modular vertical interconnect units.
Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays.
Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed operations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
The manufacturing of smaller semiconductor devices relies on implementing improvements to horizontal and vertical electrical interconnection between multiple semiconductor devices on multiple levels, i.e., three dimensional (3-D) device integration. One approach to achieving the objectives of greater integration and smaller semiconductor devices is to focus on 3-D packaging technologies including PoP. However, PoP often requires laser drilling to form interconnect structures, which increases equipment cost and requires drilling through an entire package thickness. Laser drilling increases cycle time and decreases manufacturing throughput. Vertical interconnections formed exclusively by a laser drilling process can result in reduced control for vertical interconnections. Unprotected contacts can also lead to increases in yield loss for interconnections formed with subsequent surface mount technology (SMT). Furthermore, conductive materials used for forming vertical interconnects within PoP, such as copper (Cu), can incidentally be transferred to semiconductor die during package formation, thereby contaminating the semiconductor die within the package.
The electrical interconnection between a PoP and external devices can be accomplished by forming redistribution layers (RDLs) within a build-up interconnect structure over both a front side and a backside of a semiconductor die within the PoP. However, the formation of multiple RDLs over both a front side and a backside of the semiconductor die can be a slow and costly approach for making electrical interconnection between stacked semiconductor devices and can result in higher fabrication costs. The electrical interconnection between a Fo-PoP and external devices can also be accomplished by disposing an interposer over the Fo-PoP. However, using an interposer for electrical interconnection between semiconductor devices results in a thicker overall semiconductor package. In addition, as fabrication technologies improve, the number of input/output (I/O) pins per semiconductor device is increasing while the average semiconductor device size in pitch between adjacent interconnect structures is decreasing. Mounting semiconductor devices with increased I/O density to conventional motherboards can prove difficult because interconnection pads on conventional motherboards are typically configured with a larger pitch.
A need exists for a thin, cost-effective semiconductor package with vertical interconnects formed without laser drilling that will accommodate fine-pitch semiconductor die with high I/O count. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor package including a first semiconductor die and a modular interconnect unit disposed around the first semiconductor die, providing an interposer, disposing the interposer over the semiconductor package, providing a second semiconductor die, and disposing the second semiconductor die over the interposer opposite the semiconductor package.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing an interposer, providing a semiconductor package including a first semiconductor die and a modular interconnect unit disposed around the first semiconductor die, and disposing the semiconductor package over the interposer.
In another embodiment, the present invention is a semiconductor device comprising a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. An interposer is disposed over the first semiconductor die.
In another embodiment, the present invention is a semiconductor device comprising a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die.
The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, those skilled in the art will appreciate that the disclosure is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and the claims' equivalents as supported by the following disclosure and drawings.
Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.
Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices by dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light, the negative photoresist, is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.
Patterning is the basic operation by which portions of the top layers on the semiconductor wafer surface are removed. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle or masks is transferred into a layers of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photoresist or positive-acting photoresist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes the portion of the top layers of semiconductor wafer not covered by the photoresist. The chemistry of photoresists is such that the photoresist remains substantially intact and resists removal by chemical etching solutions while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed. The process of forming, exposing, and removing the photoresist, as well as the process of removing a portion of the semiconductor wafer can be modified according to the particular resist used and the desired results.
In negative-acting photoresists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisoprenes. Removing the soluble portions (i.e., the portions not exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.
In positive-acting photoresists, photoresist is exposed to light and is changed from relatively nonsoluble condition to much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e., the portions exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.
After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.
Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.
Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and then packaging the semiconductor die for structural support and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
Electronic device 50 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 can be a subcomponent of a larger system. For example, electronic device 50 can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, radio frequency (RF) circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.
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In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
For the purpose of illustration, several types of first level packaging, including bond wire package 56 and flipchip 58, are shown on PCB 52. Additionally, several types of second level packaging, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package (DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, and quad flat package 72, are shown mounted on PCB 52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
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BGA 60 is electrically and mechanically connected to PCB 52 with a BGA style second level packaging using bumps 112. Semiconductor die 58 is electrically connected to conductive signal traces 54 in PCB 52 through bumps 110, signal lines 114, and bumps 112. A molding compound or encapsulant 116 is deposited over semiconductor die 58 and carrier 106 to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die 58 to conduction tracks on PCB 52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be mechanically and electrically connected directly to PCB 52 using flipchip style first level packaging without intermediate carrier 106.
An electrically conductive layer 132 is formed over active surface 130 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 132 operates as contact pads electrically connected to the circuits on active surface 130. Conductive layer 132 can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die 124, as shown in
An insulating or passivation layer 134 is conformally applied over active surface 130 using PVD, CVD, screen printing, spin coating, or spray coating. The insulating layer 134 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties. The insulating layer 134 covers and provides protection for active surface 130. A portion of insulating layer 134 is removed by laser direct ablation (LDA) using laser 136 or other suitable process to expose conductive layer 132 and provide for subsequent electrical interconnect.
Semiconductor wafer 120 undergoes electrical testing and inspection as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer 120. Software can be used in the automated optical analysis of semiconductor wafer 120. Visual inspection methods may employ equipment such as a scanning electron microscope, high-intensity or ultra-violet light, or metallurgical microscope. Semiconductor wafer 120 is inspected for structural characteristics including warpage, thickness variation, surface particulates, irregularities, cracks, delamination, and discoloration.
The active and passive components within semiconductor die 124 undergo testing at the wafer level for electrical performance and circuit function. Each semiconductor die 124 is tested for functionality and electrical parameters using a probe or other testing device. A probe is used to make electrical contact with nodes or contact pads 132 on each semiconductor die 124 and provides electrical stimuli to the contact pads. Semiconductor die 124 responds to the electrical stimuli, which is measured and compared to an expected response to test functionality of the semiconductor die. The electrical tests may include circuit functionality, lead integrity, resistivity, continuity, reliability, junction depth, electro-static discharge (ESD), RF performance, drive current, threshold current, leakage current, and operational parameters specific to the component type. The inspection and electrical testing of semiconductor wafer 120 enables semiconductor die 124 that pass to be designated as known good die (KGD) for use in a semiconductor package.
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An optional conductive layer 162 can be formed over the exposed conductive layer 156 using a metal deposition process such as electrolytic plating and electroless plating. Conductive layer 162 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. In one embodiment, conductive layer 162 is a Cu protective layer.
Laminate core 140 with vertical interconnect structures 158 constitute one or more PWB modular vertical interconnect units, which are disposed between semiconductor die or packages to facilitate electrical interconnect for a Fo-PoP.
Carrier 170 can be a round or rectangular panel (greater than 300 mm) with capacity for multiple semiconductor die 124. Carrier 170 may have a larger surface area than the surface area of semiconductor wafer 120. A larger carrier reduces the manufacturing cost of the semiconductor package as more semiconductor die can be processed on the larger carrier thereby reducing the cost per unit. Semiconductor packaging and processing equipment are designed and configured for the size of the wafer or carrier being processed.
To further reduce manufacturing costs, the size of carrier 170 is selected independent of the size of semiconductor die 124 or size of semiconductor wafer 120. That is, carrier 170 has a fixed or standardized size, which can accommodate various size semiconductor die 124 singulated from one or more semiconductor wafers 120. In one embodiment, carrier 170 is circular with a diameter of 330 mm. In another embodiment, carrier 170 is rectangular with a width of 560 mm and length of 600 mm. Semiconductor die 124 may have dimensions of 10 mm by 10 mm, which are placed on the standardized carrier 170. Alternatively, semiconductor die 124 may have dimensions of 20 mm by 20 mm, which are placed on the same standardized carrier 170. Accordingly, standardized carrier 170 can handle any size semiconductor die 124, which allows subsequent semiconductor processing equipment to be standardized to a common carrier, i.e., independent of die size or incoming wafer size. Semiconductor packaging equipment can be designed and configured for a standard carrier using a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 170 lowers manufacturing costs and capital risk by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size. By selecting a predetermined carrier size to use for any size semiconductor die from all semiconductor wafer, a flexible manufacturing line can be implemented.
PWB modular units 164 and 166 from
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An electrically conductive layer or RDL 184 is formed over insulating layer 182 using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layer 184 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer 184 contains Ti/Cu, TiW/Cu, or Ti/NiV/Cu. One portion of conductive layer 184 is electrically connected to contact pads 132 of semiconductor die 124. Another portion of conductive layer 184 is electrically connected to vertical interconnect structures 158 of PWB units 164 and 166. Other portions of conductive layer 184 can be electrically common or electrically isolated depending on the design and function of semiconductor die 124.
An insulating or passivation layer 186 is formed over insulating layer 182 and conductive layer 184 using PVD, CVD, lamination, printing, spin coating, or spray coating. The insulating layer 186 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric with or without filler, or other material having similar insulating and structural properties. A portion of insulating layer 186 is removed by an etching process or LDA to expose conductive layer 184.
An electrically conductive layer or RDL 188 is formed over conductive layer 184 and insulating layer 186 using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layer 188 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer 188 contains Ti/Cu, TiW/Cu, or Ti/NiV/Cu. One portion of conductive layer 188 is electrically connected to conductive layer 184. Other portions of conductive layer 188 can be electrically common or electrically isolated depending on the design and function of semiconductor die 124.
An insulating or passivation layer 190 is formed over insulating layer 186 and conductive layer 188 using PVD, CVD, printing, spin coating, or spray coating. The insulating layer 190 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric with or without filler, or other material having similar insulating and structural properties. A portion of insulating layer 190 is removed by an etching process or LDA to expose conductive layer 188.
The number of insulating and conductive layers included within build-up interconnect structure 180 depends on, and varies with, the complexity of the circuit routing design. Accordingly, build-up interconnect structure 180 can include any number of insulating and conductive layers to facilitate electrical interconnect with respect to semiconductor die 124.
An electrically conductive bump material is deposited over build-up interconnect structure 180 and electrically connected to the exposed portion of conductive layer 188 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 188 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above the material's melting point to form spherical balls or bumps 192. In some applications, bumps 192 are reflowed a second time to improve electrical contact to conductive layer 188. In one embodiment, bumps 192 are formed over an under bump metallization (UBM) layer. Bumps 192 can also be compression bonded or thermocompression bonded to conductive layer 188. Bumps 192 represent one type of interconnect structure that can be formed over conductive layer 188. The interconnect structure can also use bond wire, conductive paste, stud bump, micro bump, or other electrical interconnect.
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PWB modular units 164 and 166 disposed within Fo-PoP 204 can differ in size and shape while still providing through vertical interconnect in the Fo-PoP. PWB modular units 164 and 166 include interlocking footprints having square and rectangular shapes, a cross-shape (+), an angled or “L-shape,” a circular or oval shape, a hexagonal shape, an octagonal shape, a star shape, or any other geometric shape. At the wafer level, i.e., before singulation, PWB modular units 164 and 166 are disposed around semiconductor die 124 in an interlocking pattern such that different sides of the semiconductor die are aligned with, and correspond to, a number of different sides of the PWB units in a repeating pattern. PWB units 164 and 166 may include additional metal layers to facilitate design integration and increased routing flexibility.
PWB modular units 164 and 166 provide a cost effective alternative to using standard laser drilling processes for vertical interconnection in Fo-PoP 204 for a number of reasons. First, PWB units 164 and 166 can be made with low cost manufacturing technology such as substrate manufacturing technology. Second, standard laser drilling includes high equipment cost and requires drilling through an entire package thickness, which increases cycle time and decrease manufacturing throughput. Furthermore, the use of PWB units 164 and 166 for vertical interconnection provides an advantage of improved control for vertical interconnection with respect to vertical interconnections formed exclusively by a laser drilling process.
In another embodiment,
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A central portion of each PWB unit 270 is removed by punching, etching, LDA, or other suitable process to form openings 271. Openings 271 are formed centrally with respect to the vertical interconnect structures 268 of each PWB unit 270 and are formed through PWB units 270 to expose interface layer 224. Openings 271 have a generally square footprint and are formed large enough to accommodate semiconductor die 124 from
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Taken together, insulating layers 304, 310, and 318 as well as conductive layers 308, 316, and conductive bumps 322 form build-up interconnect structure 324. The number of insulating and conductive layers included within build-up interconnect structure 324 depends on, and varies with, the complexity of the circuit routing design. Accordingly, build-up interconnect structure 324 can include any number of insulating and conductive layers to facilitate electrical interconnect with respect to semiconductor die 124. Similarly, PWB units 164 and 166 may include additional metal layers to facilitate design integration and increased routing flexibility. Furthermore, elements that would otherwise be included in a backside interconnect structure or RDL can be integrated as part of build-up interconnect structure 324 to simplify manufacturing and reduce fabrication costs with respect to a package including both front side and backside interconnects or RDLs.
PWB modular units 164 and 166 contain one or multiple rows of vertical interconnect structures 158 that provide through vertical interconnection between opposing sides of the PWB units and are configured to be integrated into subsequently formed Fo-PoP. Vertical interconnect structures 158 include vias 150 that are left void or alternatively filled with filler material 154, e.g., conductive material or insulating material. Filler material 154 is specially selected to be softer or more compliant than conductive layer 152. Filler material 154 reduces the incidence of cracking or delamination by allowing vertical interconnect structures 158 to deform or change shape under stress. In one embodiment, vertical interconnect structures 158 include conductive layer 162 that is a copper protection layer for preventing oxidation of the conductive via, thereby reducing yield loss in SMT applications.
PWB modular units 164 and 166 are disposed within Fo-PoP 328 such that surface 228 of PWB units 166 and a corresponding surface of PWB units 164 are vertically offset with respect to back surface 128 of semiconductor die 124 by a distance D3. The separation of D3 prevents material from vertical interconnect structures 158, such as Cu, from incidentally transferring to, and contaminating a material of, semiconductor die 124, such as Si. Preventing contamination of semiconductor die 124 from material of vertical interconnect structures 158 is further facilitated by exposing conductive layer 162 by LDA or another removal process separate from the grinding operation, shown in
PWB modular units 164 and 166 disposed within Fo-PoP 328 can differ in size and shape from one another, while still providing through vertical interconnect for the Fo-PoP. PWB units 164 and 166 include interlocking footprints having square and rectangular shapes, a cross-shape (+), an angled or “L-shape,” a circular or oval shape, a hexagonal shape, an octagonal shape, a star shape, or any other geometric shape. At the wafer level, and before singulation, PWB units 164 and 166 are disposed around semiconductor die 124 in an interlocking pattern such that different sides of semiconductor die 124 are aligned with, and correspond to, a number of different sides of the PWB units in a repeating pattern. PWB units 164 and 166 may include additional metal layers to facilitate design integration and increased routing flexibility.
PWB modular units 164 and 166 provide a cost effective alternative to using standard laser drilling processes for vertical interconnection in Fo-PoP for a number of reasons. First, PWB units 164 and 166 can be made with low cost manufacturing technology such as substrate manufacturing technology. Second, standard laser drilling includes high equipment cost and requires drilling through an entire package thickness, which increases cycle time and decrease manufacturing throughput. Furthermore, the use of PWB units 164 and 166 for vertical interconnection provides an advantage of improved control for vertical interconnection with respect to vertical interconnections formed exclusively by a laser drilling process.
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Semiconductor die 550 is mounted back surface 552 oriented to substrate 560. Substrate 560 can be a PCB. A plurality of bond wires 562 is formed between conductive layer 556 and trace lines or contact pads 564 formed on substrate 560. An encapsulant 566 is deposited over semiconductor die 550, substrate 560, and bond wires 562. Bumps 568 are formed over contact pads 570 on substrate 560.
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When modular units 580 are mounted to interface layer 224, surface 583 of modular units 580 is coplanar with exposed surface 584 of interface layer 224, such that surface 583 is not embedded within interface layer 224. Thus, surface 583 of modular units 580 is vertically offset with respect to surface 225 of insulating layer 134.
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An electrically conductive layer 603 is patterned and deposited over insulating layer 602, over semiconductor die 124, and within the openings formed through insulating layer 602. Conductive layer 603 is electrically connected to conductive layer 132 of semiconductor die 124. Conductive layer 603 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer 603 contains Ti/Cu, TiW/Cu, or Ti/NiV/Cu. The deposition of conductive layer 603 uses PVD, CVD, electrolytic plating, electroless plating, or other suitable process. Conductive layer 603 operates as an RDL to extend electrical connection from semiconductor die 124 to points external to semiconductor die 124 to laterally redistribute the electrical signals of semiconductor die 124 across the package. Portions of conductive layer 603 can be electrically common or electrically isolated according to the design and function of semiconductor die 124.
An insulating or passivation layer 604 is formed over conductive layer 603 and insulating layer 602. Insulating layer 604 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Insulating layer 604 is deposited using PVD, CVD, printing, spin coating, spray coating, or other suitable process. A portion of insulating layer 604 is removed by LDA, etching, or other suitable process to expose portions of conductive layer 603 for subsequent electrical interconnection.
An electrically conductive layer 605 is patterned and deposited over insulating layer 604, within the openings formed through insulating layer 604, and is electrically connected to conductive layers 603 and 132. Conductive layer 605 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer 605 contains Ti/Cu, TiW/Cu, or Ti/NiV/Cu. The deposition of conductive layer 605 uses PVD, CVD, electrolytic plating, electroless plating, or other suitable process. Conductive layer 605 operates as an RDL to extend electrical connection from semiconductor die 124 to points external to semiconductor die 124 to laterally redistribute the electrical signals of semiconductor die 124 across the package. Portions of conductive layer 605 can be electrically common or electrically isolated according to the design and function of semiconductor die 124.
An insulating layer 606 is formed over insulating layer 604 and conductive layer 605. Insulating layer 606 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Insulating layer 606 is deposited using PVD, CVD, printing, spin coating, spray coating, or other suitable process. A portion of insulating layer 606 is removed by LDA, etching, or other suitable process to form openings to expose portions of conductive layer 605 for subsequent electrical interconnection.
An electrically conductive bump material is deposited over the exposed portion of conductive layer 605 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 605 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps 607. In some applications, bumps 607 are reflowed a second time to improve electrical contact to conductive layer 605. In one embodiment, bumps 607 are formed over a UBM having a wetting layer, barrier layer, and adhesive layer. The bumps can also be compression bonded to conductive layer 605. Bumps 607 represent one type of interconnect structure that can be formed over conductive layer 605. The interconnect structure can also use bond wire, conductive paste, stud bump, micro bump, or other electrical interconnect.
Collectively, insulating layers 602, 604, and 606, conductive layers 603, 605, and conductive bumps 607 constitute a build-up interconnect structure 610. The number of insulating and conductive layers included within build-up interconnect structure 610 depends on, and varies with, the complexity of the circuit routing design. Accordingly, build-up interconnect structure 610 can include any number of insulating and conductive layers to facilitate electrical interconnect with respect to semiconductor die 124. Furthermore, elements that would otherwise be included in a backside interconnect structure or RDL can be integrated as part of build-up interconnect structure 610 to simplify manufacturing and reduce fabrication costs with respect to a package including both front side and backside interconnects or RDLs.
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Backside surface 624 of encapsulant 600 undergoes a grinding operation with grinder 628 to planarize and reduce a thickness of encapsulant 600 and semiconductor die 124. A chemical etch can also be used to planarize and remove a portion of encapsulant 600 and semiconductor die 124. After the grinding operation is completed, exposed back surface 630 of semiconductor die 124 is coplanar with surface 592 of modular units 580 and exposed surface 632 of encapsulant 600.
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Insulating layers 672 are formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layers 672 contain one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Conductive layers 674 are formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layers 674 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. Conductive layers 674 include lateral RDL and vertical conductive vias to provide electrical interconnect through interposer panel 670.
A conductive layer or RDL 676 is formed in surface 678 of interposer panel 670 using a patterning and metal deposition process such as sputtering, electrolytic plating, or electroless plating. Conductive layer 676 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 676 operates as contact pads electrically connected to conductive layers 674 within interposer panel 670. In one embodiment, contact pads 676 have a pitch of 500 μm or less.
A conductive layer or RDL 680 is formed in surface 682 of interposer panel 670 using a patterning and metal deposition process such as sputtering, electrolytic plating, or electroless plating. Conductive layer 680 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 680 operates as contact pads electrically connected to conductive layers 674 within interposer panel 670. In one embodiment, contact pads 680 have a pitch of 300 μm or less and a diameter of approximately 200 μm. Conductive layer 680 is electrically connected to conductive layer 676 through conductive layers 674.
In
Interposer panel 670 is singulated through insulating material 672 using saw blade or laser cutting tool 686 into individual interposers 690.
An electrically conductive bump material is deposited over conductive pillars 702 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material can be reflowed to form a rounded bump cap 704. The combination of conductive pillars 702 and bump cap 704 constitute a composite interconnect structure with a non-fusible portion (conductive pillar 702) and a fusible portion (bump cap 704). In one embodiment, the diameter of conductive pillars 702 ranges from 115 μm to 145 μm and the pitch between adjacent bump caps 704 is 300 μm or less.
PWB modular units 736 and 738 including vertical interconnect structures 740 are disposed around semiconductor die 724, similar to PWB modular units 164 and 166 in
The remaining space in the vias is filled with an insulating or conductive filler material 746. The insulating filler material can be polymer dielectric material with filler and one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. The conductive filler material can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, filler material 746 is a polymer plug. Alternatively, filler material 746 is Cu paste. The vias can also be left void, i.e., without filler material. Filler material 746 is selected to be softer or more compliant than conductive layer 744. Filler material 746 reduces the incidence of cracking or delamination by allowing deformation or change of shape of conductive layer 744 under stress. Alternatively, the vias can be completely filled with conductive layer 744.
A conductive layer 748 is formed over conductive layer 744 and filler material 746 using a metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 748 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. In one embodiment, conductive layer 748 includes a first Cu layer formed by electroless plating, followed by a second Cu layer formed by electrolytic plating.
An insulating or passivation layer 750 is formed over the surface of core substrate 742 and conductive layer 748 using PVD, CVD, printing, spin coating, spray coating, slit coating, rolling coating, lamination, sintering, or thermal oxidation. Insulating layer 750 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, hafnium oxide (HfO2), benzocyclobutene (BCB), polyimide (PI), polybenzoxazoles (PBO), polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties. A portion of insulating layer 750 is removed by LDA, etching, or other suitable process to expose portions of conductive layer 748. In one embodiment, insulating layer 750 is a masking layer.
An electrically conductive layer 752 is formed over conductive layer 744 and filler material 746 opposite conductive layer 748 using a metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 752 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. In one embodiment, conductive layer 752 includes a first Cu layer formed by electroless plating, followed by a second Cu layer formed by electrolytic plating. Conductive layer 752 is electrically connected to conductive layer 748 through conductive layer 744. Conductive layers 744, 748, and 752 form vertical interconnects 740 through core substrate 742.
An insulating or passivation layer 754 is formed over the surface of core substrate 742 and conductive layer 752 using PVD, CVD, printing, spin coating, spray coating, slit coating, rolling coating, lamination, sintering, or thermal oxidation. Insulating layer 754 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties. A portion of insulating layer 754 is removed by LDA, etching, or other suitable process to expose portions of conductive layer 752. In one embodiment, insulating layer 752 is a masking layer. An optional protection layer 756, e.g., a solder cap or Cu organic solderability preservative (OSP), is formed over conductive layer 748. Conductive layer 744, PWB units 736 and 738 may include additional metal layers to facilitate design integration and increased routing flexibility.
PWB modular units 736 and 738 disposed within reconstituted wafer 720 can differ in size and shape from one another, while still providing through vertical interconnect for the Fo-PoP. PWB units 736 and 738 include interlocking footprints having square and rectangular shapes, a cross-shape (+), an angled or “L-shape,” a circular or oval shape, a hexagonal shape, an octagonal shape, a star shape, or any other geometric shape. PWB units 736 and 738 are disposed around semiconductor die 724 in an interlocking pattern such that different sides of semiconductor die 724 are aligned with, and correspond to, a number of different sides of the PWB units in a repeating pattern. PWB modular units 736 and 738 are laterally offset from semiconductor die 724. Back surface 728 of semiconductor die 724 is offset from PWB modular units 736 and 738 by at least 1 μm, similar to
A build-up interconnect structure 762, similar to build-up interconnect structure 180 in
Insulating or passivation layer 764 is formed over semiconductor die 724, PWB units 736 and 738, and encapsulant 758 using PVD, CVD, lamination, printing, spin coating, or spray coating. The insulating layer 764 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric with or without filler, or other material having similar insulating and structural properties. A portion of insulating layer 764 is removed by LDA, etching, or other suitable process to expose portions of conductive layer 752 of PWB units 736 and 738, and conductive layer 732 of semiconductor die 724.
Conductive layer or RDL 766 is formed over insulating layer 764 using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layer 766 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer 766 contains Ti/Cu, TiW/Cu, or Ti/NiV/Cu. One portion of conductive layer 766 is electrically connected to conductive layer 732 of semiconductor die 724. Another portion of conductive layer 766 is electrically connected to vertical interconnect structures 740 of PWB units 736 and 738. Other portions of conductive layer 766 can be electrically common or electrically isolated depending on the design and function of semiconductor die 724.
Insulating or passivation layer 768 is formed over insulating layer 764 and conductive layer 766 using PVD, CVD, lamination, printing, spin coating, or spray coating. The insulating layer 768 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric with or without filler, or other material having similar insulating and structural properties. A portion of insulating layer 768 is removed by LDA, etching, or other suitable process to expose conductive layer 766.
Conductive layer or RDL 770 is formed over insulating layer 768 and conductive layer 766 using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layer 770 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer 770 contains Ti/Cu, TiW/Cu, or Ti/NiV/Cu. One portion of conductive layer 770 is electrically connected to conductive layer 766. Other portions of conductive layer 770 can be electrically common or electrically isolated depending on the design and function of semiconductor die 724.
Insulating or passivation layer 772 is formed over insulating layer 768 and conductive layer 770 using PVD, CVD, printing, spin coating, or spray coating. The insulating layer 772 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric with or without filler, or other material having similar insulating and structural properties. A portion of insulating layer 772 is removed by LDA, etching, or other suitable process to expose conductive layer 770.
The number of insulating and conductive layers included within build-up interconnect structure 762 depends on, and varies with, the complexity of the circuit routing design. Accordingly, build-up interconnect structure 762 can include any number of insulating and conductive layers to facilitate electrical interconnect with respect to semiconductor die 724.
An electrically conductive bump material is deposited over build-up interconnect structure 762 and electrically connected to the exposed portion of conductive layer 770 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 770 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above the material's melting point to form spherical balls or bumps 774. In some applications, bumps 774 are reflowed a second time to improve electrical contact to conductive layer 770. In one embodiment, bumps 774 are formed over a UBM layer. Bumps 774 can also be compression bonded or thermocompression bonded to conductive layer 770. Bumps 774 represent one type of interconnect structure that can be formed over conductive layer 770. The interconnect structure can also use bond wire, conductive paste, stud bump, micro bump, conductive pillar, composite interconnect structure, or other electrical interconnect. In one embodiment, the pitch between adjacent bumps 774 is 400 μm or less.
In
An underfill material 776 is deposited between interposer 690 and reconstituted wafer 720 using a paste printing, jet dispense, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, mold underfill, or other suitable application process. Underfill 776 can be epoxy, epoxy-resin adhesive material, polymeric materials, films, or other non-conductive materials. Underfill 776 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
In another embodiment, continuing from
In
In
Continuing from
In
Semiconductor device 800 is mounted to interposer 690 using pick and place or other suitable operation. Bumps 802 of semiconductor device 800 are aligned with conductive layer 676 of interposer 690. The pitch between bumps 802 coincides with the pitch of conductive layer 676 of interposer 690, e.g., the pitch of both bumps 802 and conductive layer 676 is 500 μm. Bumps 802 are reflowed to metallurgically and electrically connect to conductive layer 676. In some applications, bumps 802 are reflowed a second time to improve electrical contact to conductive layer 676. Bumps 802 are Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof. Bumps 802 can be eutectic Sn/Pb, high-lead solder, or lead-free solder. Bumps 802 represent one type of interconnect structure that can be formed between semiconductor devices 800 and interposer 690. The interconnect structure can also use can also use bond wire, conductive paste, stud bump, micro bump, conductive pillar, composite interconnect structure, or other electrical interconnect. Semiconductor device 800 is electrically connected to semiconductor die 724 through interposer 690, PWB units 736 and 738, and build-up interconnect structure 762. Semiconductor device 800 is tested prior to mounting semiconductor device 800 to interposer 690 to assure that only known good devices are mounted to interposer 690.
Fo-PoP 792, interposer 690, and semiconductor device 800 form a 3-D semiconductor package 804 including a Fo-PoP with semiconductor die interconnected by PWB modular units having vertical interconnect structures.
The thin profile of Fo-PoP 792 reduces the overall thickness of 3-D semiconductor package 804. In one embodiment, a thickness Fo-PoP 792 including bumps 774 is less than 0.4 mm. PWB modular units 736 and 738 are made with low cost manufacturing technology such as substrate manufacturing technology and provide a cost effective alternative to using standard laser drilling processes for vertical interconnection in Fo-PoP 792. Interposer 690 provides a cost effect, reliable electrical interconnection between Fo-PoP 792 and semiconductor device 800 without adding significant thickness to 3-D semiconductor package 804, e.g., interposer 690 has a thickness of 120 μm or less. In one embodiment, a thin flexible circuit sheet is provided for interposer 690 to further reduce the thickness of 3-D semiconductor package 804. Interposer 690 may also provide RF and SiP functions, e.g., interposer 690 may include an embedded thin film capacitor, inductor, and/or passive component, to increase the electrical performance and functionality of 3-D semiconductor package 804 without increasing the footprint of 3-D semiconductor package 804.
Insulating layers 812 are formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layers 812 contain one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. Conductive layers 814 are formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layers 814 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. Conductive layers 814 include lateral RDL and vertical conductive vias to provide electrical interconnect through interposer panel 810. Portions of conductive layers 814 are electrically common or electrically isolated according to the design and function of the semiconductor die or packages that are subsequently mounted to interposer panel 810.
A conductive layer or RDL 816 is formed in surface 818 of interposer panel 810 using a patterning and metal deposition process such as sputtering, electrolytic plating, or electroless plating. Conductive layer 816 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 816 operates as contact pads electrically connected to conductive layers 814 within interposer panel 810. In one embodiment, contact pads 816 have a pitch of 300 μm or less and a diameter of approximately 200 μm.
A conductive layer or RDL 820 is formed in surface 821 of interposer panel 810 using a patterning and metal deposition process such as sputtering, electrolytic plating, or electroless plating. Conductive layer 820 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 820 operates as contact pads electrically connected to conductive layers 814 within interposer panel 810. In one embodiment, contact pads 820 have a pitch of 500 μm or less. Conductive layer 820 is electrically connected to conductive layer 816 through conductive layers 814.
An interconnect structure or solder paste 822 is printed on conductive layer 816 of interposer panel 810. In one embodiment, interconnect structure 822 is formed by depositing a shallow solder cap on conductive layer 816 followed by a flux stencil printing. Solder paste 822 represents one type of interconnect structure that can be formed over conductive layer 816. The interconnect structure can also use bond wire, stud bump, micro bump, conductive pillar, composite interconnect structure, or other electrical interconnect.
In
Fo-PoP 892 includes semiconductor die 824, PWB modular units 836 and 838, and build-up interconnect structure 862. Semiconductor die 824, similar to semiconductor die 124 from
PWB modular units 836 and 838 including vertical interconnects 840 are disposed around semiconductor die 824, similar to PWB modular units 164 and 166 in
A plurality of through vias is formed through core substrate 842 using laser drilling, mechanical drilling, or DRIE. A conductive layer 844 is formed over core 842 and the sidewalls of the vias using a metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 844 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. In one embodiment, conductive layer 844 includes a first Cu layer formed by electroless plating, followed by a second Cu layer formed by electrolytic plating.
The remaining space in the vias is filled with an insulating or conductive filler material 846. The insulating filler material can be polymer dielectric material with filler and one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. The conductive filler material can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, filler material 846 is a polymer plug. Alternatively, filler material 846 is Cu paste. The vias can also be left void, i.e., without filler material. Filler material 846 is selected to be softer or more compliant than conductive layer 844. Filler material 846 reduces the incidence of cracking or delamination by allowing deformation or change of shape of conductive layer 844 under stress. Alternatively, the vias can be completely filled with conductive layer 844.
A conductive layer 848 is formed over conductive layer 844 and filler material 846 using a metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 848 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. In one embodiment, conductive layer 848 includes a first Cu layer formed by electroless plating, followed by a second Cu layer formed by electrolytic plating.
An insulating or passivation layer 850 is formed over the surface of core substrate 842 and conductive layer 848 using PVD, CVD, printing, spin coating, spray coating, slit coating, rolling coating, lamination, sintering, or thermal oxidation. Insulating layer 850 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties. A portion of insulating layer 850 is removed by LDA, etching, or other suitable process to expose portions of conductive layer 848. In one embodiment, insulating layer 850 is a masking layer.
An electrically conductive layer 852 is formed over conductive layer 844 and filler material 846 opposite conductive layer 848 using a metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 852 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material. In one embodiment, conductive layer 752 includes a first Cu layer formed by electroless plating, followed by a second Cu layer formed by electrolytic plating. Conductive layer 852 is electrically connected to conductive layer 848 through conductive layer 844. Conductive layers 844, 848, and 852 form vertical interconnects 840 through core substrate 842.
An insulating or passivation layer 854 is formed over the surface of core substrate 842 and conductive layer 852 using PVD, CVD, printing, spin coating, spray coating, slit coating, rolling coating, lamination, sintering, or thermal oxidation. Insulating layer 854 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties. A portion of insulating layer 854 is removed by LDA, etching, or other suitable process to expose portions of conductive layer 852. In one embodiment, insulating layer 854 is a masking layer. An optional protection layer 856, e.g., a solder cap or Cu OSP, is formed over conductive layer 848.
PWB units 836 and 838 are disposed around semiconductor die 824 in an interlocking pattern such that different sides of semiconductor die 824 are aligned with, and correspond to, a number of different sides of the PWB units in a repeating pattern. PWB modular units 836 and 838 are laterally offset from semiconductor die 824. Back surface 828 of semiconductor die 824 is offset from PWB modular units 836 and 838 by at least 1 μm, similar to
Build-up interconnect structure 862, similar to build-up interconnect structure 180 in
An electrically conductive layer or RDL 866 is formed over insulating layer 864 using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layer 866 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer 866 contains Ti/Cu, TiW/Cu, or Ti/NiV/Cu. One portion of conductive layer 866 is electrically connected to conductive layer 832 of semiconductor die 824. Another portion of conductive layer 866 is electrically connected to vertical interconnect structures 840 of PWB units 836 and 838. Other portions of conductive layer 866 can be electrically common or electrically isolated depending on the design and function of semiconductor die 824.
An insulating or passivation layer 868 is formed over insulating layer 864 and conductive layer 866 using PVD, CVD, lamination, printing, spin coating, or spray coating. The insulating layer 868 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric with or without filler, or other material having similar insulating and structural properties. A portion of insulating layer 868 is removed by LDA, etching, or other suitable process to expose conductive layer 866.
An electrically conductive layer or RDL 870 is formed over insulating layer 868 and conductive layer 866 using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating. Conductive layer 870 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, conductive layer 870 contains Ti/Cu, TiW/Cu, or Ti/NiV/Cu. One portion of conductive layer 870 is electrically connected to conductive layer 866. Other portions of conductive layer 870 can be electrically common or electrically isolated depending on the design and function of semiconductor die 824.
An insulating or passivation layer 872 is formed over insulating layer 868 and conductive layer 870 using PVD, CVD, printing, spin coating, or spray coating. The insulating layer 872 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric with or without filler, or other material having similar insulating and structural properties. A portion of insulating layer 872 is removed by LDA, etching, or other suitable process to expose conductive layer 870.
The number of insulating and conductive layers included within build-up interconnect structure 862 depends on, and varies with, the complexity of the circuit routing design. Accordingly, build-up interconnect structure 862 can include any number of insulating and conductive layers to facilitate electrical interconnect with respect to semiconductor die 824.
An electrically conductive bump material is deposited over build-up interconnect structure 862 and electrically connected to the exposed portion of conductive layer 870 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 870 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above the material's melting point to form spherical balls or bumps 874. In some applications, bumps 874 are reflowed a second time to improve electrical contact to conductive layer 870. In one embodiment, bumps 874 are formed over a UBM layer. Bumps 874 can also be compression bonded or thermocompression bonded to conductive layer 870. Bumps 874 represent one type of interconnect structure that can be formed over conductive layer 870. The interconnect structure can also use bond wire, conductive paste, stud bump, micro bump, conductive pillar, composite interconnect structure, or other electrical interconnect. In one embodiment, bumps 874 have a pitch of 400 μm or less.
In
In
In
In another embodiment, continuing from
An electrically conductive bump material is deposited over conductive pillars 884 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material can be reflowed to form a rounded bump cap 885. The combination of conductive pillars 884 and bump cap 885 constitute a composite interconnect structure with a non-fusible portion (conductive pillar 884) and a fusible portion (bump cap 885). In one embodiment, the diameter of conductive pillars 884 ranges from 115 μm to 145 μm and the pitch between adjacent bump caps 885 is 300 μm or less.
Semiconductor device 888 is disposed over surface 821 of interposer panel 810 using pick and place or other suitable operation. Bumps 890 of semiconductor device 888 are aligned with conductive layer 820 of interposer panel 810. The pitch between bumps 890 coincides with the pitch of conductive layer 820, e.g., the pitch of both bumps 890 and conductive layer 820 is 500 μm. In one embodiment, bumps 890 are formed on conductive layer 820 instead of semiconductor device 888.
In
In
The thin profile of Fo-PoP 892 reduces the overall thickness of 3-D semiconductor package 894. In one embodiment, a thickness Fo-PoP 892 including bumps 874 is less than 0.4 mm. PWB modular units 836 and 838 are made with low cost manufacturing technology such as substrate manufacturing technology and provide a cost effective alternative to using standard laser drilling processes for vertical interconnection in Fo-PoP 892. Interposer 886 provides a cost effect, reliable electrical interconnection between Fo-PoP 892 and semiconductor device 888 without adding significant thickness to 3-D semiconductor package 894, e.g., interposer 886 has a thickness of 120 μm or less. In one embodiment, interposer 886 is a thin flexible circuit sheet to further reduce the thickness of 3-D semiconductor package 894. Interposer 886 may also provide RF and SiP functions, e.g., interposer 886 may include an embedded thin film capacitor, inductor, and/or passive component, to increase the electrical performance and functionality of 3-D semiconductor package 894 without increasing the footprint of 3-D semiconductor package 894.
Semiconductor die 924, similar to semiconductor die 124 from
A plurality of PWB modular units 904 and 906 is disposed around or in a peripheral region of semiconductor die 924. PWB modular units 904 and 906 disposed within reconstituted wafer 908 can differ in size and shape from one another, while still providing through vertical interconnect for the Fo-PoP 964. PWB units 904 and 906 include interlocking footprints having square and rectangular shapes, a cross-shape (+), an angled or “L-shape,” a circular or oval shape, a hexagonal shape, an octagonal shape, a star shape, or any other geometric shape. PWB units 904 and 906 are disposed around semiconductor die 924 in an interlocking pattern such that different sides of semiconductor die 924 are aligned with, and correspond to, a number of different sides of the PWB units in a repeating pattern. In one embodiment, PWB modular units 904 and 906 are a single unit, similar to PWB unit 270 in
PWB units 904 and 906 include a core substrate 912. Core substrate 912 includes one or more laminated layers of polytetrafluoroethylene prepreg, FR-4, FR-1, CEM-1, or CEM-3 with a combination of phenolic cotton paper, epoxy, resin, woven glass, matte glass, polyester, and other reinforcement fibers or fabrics. Alternatively, core substrate 912 includes one or more insulating or passivation layers.
A plurality of through vias is formed through core substrate 912 using laser drilling, mechanical drilling, or DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable deposition process to form z-direction vertical interconnect conductive vias 914. In one embodiment, Cu is deposited over the sidewall of the through vias by electroless plating and electroplating and the through vias are filled with conductive paste or plugging resin with fillers, similar to vertical interconnects 740 in
An electrically conductive layer or RDL 916 is formed over the surface of core substrate 912 and conductive vias 914 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 916 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 916 is electrically connected to conductive vias 914. Conductive layer 916 operates as contact pads electrically connected to conductive vias 914.
An insulating or passivation layer 918 is formed over the surface of core substrate 912 and conductive layer 916 using PVD, CVD, printing, spin coating, spray coating, slit coating, rolling coating, lamination, sintering, or thermal oxidation. Insulating layer 918 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties. A portion of insulating layer 918 is removed by LDA, etching, or other suitable process to expose portions of conductive layer 916. In one embodiment, insulating layer 918 is a masking layer.
An electrically conductive layer or RDL 920 is formed over a surface of core substrate 912 opposite conductive layer 916 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 920 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 920 is electrically connected to conductive vias 914 and conductive layer 916. Conductive layer 920 operates as contact pads electrically connected to conductive vias 914. Alternatively, conductive vias 914 are formed through core substrate 912 after forming conductive layer 916 and/or conductive layer 920.
An insulating or passivation layer 922 is formed over the surface of core substrate 912 and conductive layer 920 using PVD, CVD, printing, spin coating, spray coating, slit coating, rolling coating, lamination, sintering, or thermal oxidation. Insulating layer 922 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties. A portion of insulating layer 922 is removed by LDA, etching, or other suitable process to expose portions of conductive layer 920. In one embodiment, insulating layer 922 is a masking layer. Portions of conductive layer 916, conductive layer 920, and conductive vias 914 are electrically common or electrically isolated according to the design and function of semiconductor die 924 and later mounted semiconductor die or devices.
In
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In
Electrically conductive layer or RDL 944 is formed over insulating layer 942 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 944 can be one or more layers of Al, Ti, TiW, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. One portion of conductive layer 944 is electrically connected to conductive layer 932 of semiconductor die 924. One portion of conductive layer 944 is electrically connected to conductive layer 920 of PWB units 904 and 906. Other portions of conductive layer 944 can be electrically common or electrically isolated depending on the design and function of semiconductor die 924.
Insulating or passivation layer 946 is formed over insulating layer 942 and conductive layer 944 using PVD, CVD, printing, slit coating, spin coating, spray coating, injection coating, lamination, sintering, or thermal oxidation. Insulating layer 946 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric materials, or other material having similar structural and insulating properties. A portion of insulating layer 946 is removed by an exposure and development process, LDA, etching, or other suitable process to expose conductive layer 944.
Electrically conductive layer or RDL 948 is formed over insulating layer 946 and conductive layer 944 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 948 can be one or more layers of Al, Ti, TiW, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. One portion of conductive layer 948 is electrically connected to conductive layer 944. Other portions of conductive layer 948 can be electrically common or electrically isolated depending on the design and function of semiconductor die 924.
Insulating or passivation layer 950 is formed over insulating layer 946 and conductive layer 948 using PVD, CVD, printing, slit coating, spin coating, spray coating, injection coating, lamination, sintering, or thermal oxidation. The insulating layer 950 includes one or more layers of low temperature (less than 250° C.) curing polymer dielectric materials, SiO2, Si3N4, SiON, Ta2O5, Al2O3, polymer dielectric materials, or other material having similar structural and insulating properties. A portion of insulating layer 950 is removed by an exposure and development process, LDA, etching, or other suitable process to expose conductive layer 948.
The number of insulating and conductive layers included within build-up interconnect structure 940 depends on, and varies with, the complexity of the circuit routing design. Accordingly, build-up interconnect structure 940 can include any number of insulating and conductive layers to facilitate electrical interconnect with respect to semiconductor die 924.
An electrically conductive bump material is deposited over build-up interconnect structure 940 and electrically connected to the exposed portion of conductive layer 948 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 948 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above the material's melting point to form spherical balls or bumps 952. In some applications, bumps 952 are reflowed a second time to improve electrical contact to conductive layer 948. In one embodiment, bumps 952 are formed over a UBM layer. Bumps 952 can also be compression bonded or thermocompression bonded to conductive layer 948. Bumps 952 represent one type of interconnect structure that can be formed over conductive layer 948. The interconnect structure can also use bond wire, conductive paste, stud bump, micro bump, conductive pillar, composite interconnect structure, or other electrical interconnect. In one embodiment, bumps 952 have a pitch of 400 μm or less.
In
In
Semiconductor device 970 is disposed over surface 678 of interposer 690 using a pick and place or other suitable operation. Semiconductor device 970 may include filter, memory, or other IC chips, processors, microcontrollers, known-good packages, or any other packaged device containing semiconductor die or other electronic devices or circuitry. In one embodiment, Fo-PoP 964 has an I/O count of 552 and semiconductor device 970 is a memory device with an I/O count of 504 and a bump pitch of approximately 500 μm. Bumps 972 are reflowed to metallurgically and electrically connecting semiconductor device 970 to conductive layer 676 of interposer 690. In some applications, bumps 972 are reflowed a second time to improve electrical contact to conductive layer 676. Bumps 972 are Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof. Bumps 972 can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The pitch between bumps 972 coincides with the pitch of conductive layer 676 of interposer 690, e.g., the pitch of both bumps 972 and conductive layer 676 is 500 μm. Bumps 972 represent one type of interconnect structure that can be formed between semiconductor devices 970 and interposer 690. The interconnect structure can also use bond wire, conductive paste, stud bump, micro bump, conductive pillar, composite interconnect structure, or other electrical interconnect. Semiconductor device 970 is electrically connected to semiconductor die 924 through interposer 690, PWB units 904 and 906, and build-up interconnect structure 940. Fo-PoP 964, interposer 690, and semiconductor device 970 are fabricated separately and can be stacked in any order at either a panel level, i.e., prior to singulation, or as individual components, i.e., after singulation. In one embodiment, an underfill material is deposited between Fo-PoP 964 and surface 682 of interposer 690, and/or between semiconductor device 970 and surface 678 of interposer 690.
Fo-PoP 964, interposer 690, and semiconductor device 970 form a 3-D semiconductor package 980. Semiconductor die 924 is electrically connected through build-up interconnect structure 940 to bumps 952 for connection to external devices. Semiconductor device 970 is electrically connected to semiconductor die 924 and external devices through interposer 690, PWB units 904 and 906, build-up interconnect structure 940, and bumps 952. The components of 3-D semiconductor package 980, i.e., Fo-PoP 964, interposer 690, and semiconductor device 970 are each fabricated separately. Forming Fo-PoP 964, interposer 690, and semiconductor device 970 separately allows each component to utilize a standardized infrastructure and fabrication process. For example, standardized materials and fabrication tools are employed to mass-produce Fo-PoP 964 for incorporation into 3-D semiconductor package 980 and a variety of other semiconductor packages. Incorporating standardized components within 3-D semiconductor package 980 lowers manufacturing costs, capital risk, and cycle time by reducing or eliminating the need for specialized semiconductor processing lines. Forming Fo-PoP 964, interposer 690, and semiconductor device 970 independent from one another also allows Fo-PoP 964, interposer 690, and semiconductor device 970 to be tested prior to incorporating each component into 3-D semiconductor package 980. Thus, only known good components are included in 3-D semiconductor package 980. By using only known good components, manufacturing steps and materials are not wasted making defective packages and the overall cost of 3-D semiconductor package 980 is reduced.
The thin profile of Fo-PoP 964 reduces the overall thickness of 3-D semiconductor package 980. In one embodiment, a thickness Fo-PoP 964 including bumps 952 is less than 0.4 mm. PWB modular units 904 and 906 are made with low cost manufacturing technology such as substrate manufacturing technology and provide a cost effective alternative to using standard laser drilling processes for vertical interconnection in Fo-PoP 964. Interposer 690 provides a cost effect, reliable electrical interconnection between Fo-PoP 964 and semiconductor device 970 without adding significant thickness to 3-D semiconductor package 980, e.g., interposer 690 has a thickness of 120 μm or less. In one embodiment, interposer 690 is a thin flexible circuit sheet to further reduce the thickness of 3-D semiconductor package 980. Interposer 690 may also provide RF and SiP functions, e.g., interposer 690 may include an embedded thin film capacitor, inductor, and/or passive component, to increase the electrical performance and functionality of 3-D semiconductor package 980 without increasing the footprint of 3-D semiconductor package 980.
PWB modular units 1010 are disposed around semiconductor die 1024, similar to PWB modular units 904 and 906 in
A plurality of through vias is formed through core substrate 1012 using laser drilling, mechanical drilling, or DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable deposition process to form z-direction vertical interconnect conductive vias 1014. In one embodiment, Cu is deposited over the sidewall of the through vias by electroless plating and electroplating and the through vias are filled with conductive paste or plugging resin with fillers, similar to vertical interconnects 740 in
Encapsulant or molding compound 1016 is deposited over semiconductor die 1024 and PWB units 1010 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 1016 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 1016 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. Encapsulant 1016 also protects semiconductor die 1024 from degradation due to exposure to light. A portion of encapsulant 1016 is removed in a grinding operation. The grinding operation exposes conductive vias 1114, planarizes the surface of encapsulant 1116 and semiconductor die 1024, and reduces an overall thickness of 3-D semiconductor package 990. In one embodiment, a portion of back surface 1028 of semiconductor die 1024 is also removed by the grinding operation.
Build-up interconnect structure 1040 is formed over conductive layer 1032 and insulating layer 1034 of semiconductor die 1024, PWB units 1010, and encapsulant 1016. Build-up interconnect structure 1040 includes insulating layer 1042, conductive layer 1044, insulating layer 1046, conductive layer 1048, and insulating layer 1050.
Insulating or passivation layer 1042 is formed over conductive layer 1032, insulating layer 1034, PWB units 1010, and encapsulant 1116 using PVD, CVD, printing, slit coating, spin coating, spray coating, injection coating, lamination, sintering, or thermal oxidation. The insulating layer 1042 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric materials, or other material having similar insulating and structural properties. A portion of insulating layer 1042 is removed by an exposure and development process, LDA, etching, or other suitable process to expose conductive vias 1014 of PWB units 1010, and conductive layer 1032 of semiconductor die 1024.
Electrically conductive layer or RDL 1044 is formed over insulating layer 1042 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 1044 can be one or more layers of Al, Ti, TiW, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. One portion of conductive layer 1044 is electrically connected to conductive layer 1032 of semiconductor die 1024. One portion of conductive layer 1044 is electrically connected to conductive vias 1014 of PWB units 1010. Other portions of conductive layer 1044 can be electrically common or electrically isolated depending on the design and function of semiconductor die 1024.
Insulating or passivation layer 1046 is formed over insulating layer 1042 and conductive layer 1044 using PVD, CVD, printing, slit coating, spin coating, spray coating, injection coating, lamination, sintering, or thermal oxidation. Insulating layer 1046 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, low temperature (less than 250° C.) curing polymer dielectric materials, or other material having similar structural and insulating properties. A portion of insulating layer 1046 is removed by an exposure and development process, LDA, etching, or other suitable process to expose conductive layer 1044.
Electrically conductive layer or RDL 1048 is formed over insulating layer 1046 and conductive layer 1044 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 1048 can be one or more layers of Al, Ti, TiW, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. One portion of conductive layer 1048 is electrically connected to conductive layer 1044. Other portions of conductive layer 1048 can be electrically common or electrically isolated depending on the design and function of semiconductor die 1024.
Insulating or passivation layer 1050 is formed over insulating layer 1046 and conductive layer 1048 using PVD, CVD, printing, slit coating, spin coating, spray coating, injection coating, lamination, sintering, or thermal oxidation. The insulating layer 1050 includes one or more layers of low temperature (less than 250° C.) curing polymer dielectric materials, SiO2, Si3N4, SiON, Ta2O5, Al2O3, polymer dielectric materials, or other material having similar structural and insulating properties. A portion of insulating layer 1050 is removed by an exposure and development process, LDA, etching, or other suitable process to expose conductive layer 1048.
The number of insulating and conductive layers included within build-up interconnect structure 1040 depends on, and varies with, the complexity of the circuit routing design. Accordingly, build-up interconnect structure 1040 can include any number of insulating and conductive layers to facilitate electrical interconnect with respect to semiconductor die 1024.
An electrically conductive bump material is deposited over build-up interconnect structure 1040 and electrically connected to the exposed portion of conductive layer 1048 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 1048 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above the material's melting point to form spherical balls or bumps 1052. In some applications, bumps 1052 are reflowed a second time to improve electrical contact to conductive layer 1048. In one embodiment, bumps 1052 are formed over a UBM layer. Bumps 1052 can also be compression bonded or thermocompression bonded to conductive layer 1048. Bumps 1052 represent one type of interconnect structure that can be formed over conductive layer 1048. The interconnect structure can also use bond wire, conductive paste, stud bump, micro bump, conductive pillar, composite interconnect structure, or other electrical interconnect. In one embodiment, bumps 1052 have a pitch or 400 μm or less.
Interposer 690 from
Semiconductor device 994 is disposed over surface 678 of interposer 690. Semiconductor device 994 may include filter, memory, or other IC chips, processors, microcontrollers, known-good packages, or any other packaged device containing semiconductor die or other electronic devices or circuitry. In one embodiment, Fo-PoP 992 has an I/O count of 552 and semiconductor device 994 is a memory device with an I/O count of 504 and a bump pitch of approximately 500 μm. Bumps 996 are reflowed to metallurgically and electrically connect semiconductor device 994 to conductive layer 676 of interposer 690. In some applications, bumps 996 are reflowed a second time to improve electrical contact to conductive layer 676. Bumps 996 are Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof. Bumps 996 can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The pitch between bumps 996 coincides with the pitch of conductive layer 676 of interposer 690, e.g., the pitch of both bumps 996 and conductive layer 676 is 500 μm. Bumps 996 represent one type of interconnect structure that can be formed between semiconductor devices 994 and interposer 690. The interconnect structure can also use bond wire, conductive paste, stud bump, micro bump, conductive pillar, composite interconnect structure, or other electrical interconnect. Semiconductor device 994 is electrically connected to semiconductor die 1024 through interposer 690, PWB units 1010, and build-up interconnect structure 1040. Fo-PoP 992, interposer 690, and semiconductor device 994 are fabricated separately and can be stacked in any order at either a panel level, i.e., prior to singulation, or as individual components, i.e., after singulation. In one embodiment, an underfill material is deposited between Fo-PoP 992 and surface 682 of interposer 690, and/or between semiconductor device 994 and surface 678 of interposer 690.
Fo-PoP 992, interposer 690, and semiconductor device 994 form a 3-D semiconductor package 990. Semiconductor die 1024 is electrically connected through build-up interconnect structure 1040 to bumps 1052 for connection to external devices. Semiconductor device 994 is electrically connected to semiconductor die 1024 and external devices through interposer 690, PWB units 1010, build-up interconnect structure 1040, and bumps 1052. The components of 3-D semiconductor package 990, i.e., Fo-PoP 992, interposer 690, and semiconductor device 994 are each fabricated separately. Forming Fo-PoP 992, interposer 690, and semiconductor device 994 separately allows each component to utilize a standardized infrastructure and fabrication process. For example, a separate set of standardized materials and fabrication tools are employed to mass-produce Fo-PoP 992 for incorporation into 3-D semiconductor package 990 and a variety of other semiconductor packages. Incorporating standardized components within 3-D semiconductor package 990 lowers manufacturing costs, capital risk, and cycle time by reducing or eliminating the need for specialized semiconductor processing lines. Forming Fo-PoP 992, interposer 690, and semiconductor device 994 independent from one another also allows Fo-PoP 992, interposer 690, and semiconductor device 994 to be tested prior to incorporating each component into 3-D semiconductor package 990. Thus, only known good components are included in 3-D semiconductor package 990. By using only known good components, manufacturing steps and materials are not wasted making defective packages and the overall cost of 3-D semiconductor package 990 is reduced.
The thin profile of Fo-PoP 992 reduces the overall thickness of 3-D semiconductor package 990. In one embodiment, a thickness Fo-PoP 992 including bumps 1052 is less than 0.4 mm. PWB modular units 1010 are made with low cost manufacturing technology such as substrate manufacturing technology and provide a cost effective alternative to using standard laser drilling processes for vertical interconnection in Fo-PoP 992. Interposer 690 provides a cost effect, reliable electrical interconnection between Fo-PoP 992 and semiconductor device 994 without adding significant thickness to 3-D semiconductor package 990, e.g., interposer 690 has a thickness of 120 μm or less. In one embodiment, interposer 690 is a thin flexible circuit sheet to further reduce the thickness of 3-D semiconductor package 990. Interposer 690 may also provide RF and SiP functions, e.g., interposer 690 may include an embedded thin film capacitor, inductor, and/or passive component, to increase the electrical performance and functionality of 3-D semiconductor package 990 without increasing the footprint of 3-D semiconductor package 990.
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
The present application is a division of U.S. patent application Ser. No. 14/061,244, now U.S. Pat. No. 10,049,964, filed Oct. 23, 2013, which is a continuation-in-part of U.S. patent application Ser. No. 13/477,982, now abandoned, filed May 22, 2012, which is a continuation-in-part of U.S. patent application Ser. No. 13/429,119, now U.S. Pat. No. 8,810,024, filed Mar. 23, 2012, which applications are incorporated herein by reference.
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