Semiconductor-element mounting substrate, semiconductor device, and electronic equipment

Information

  • Patent Application
  • 20070158855
  • Publication Number
    20070158855
  • Date Filed
    December 01, 2006
    17 years ago
  • Date Published
    July 12, 2007
    17 years ago
Abstract
A semiconductor-element mounting substrate is a substrate for mounting a semiconductor element, and includes a substrate body. The substrate body has a mounting surface, and the center portion of the mounting surface is provided with a die pattern. Through conductors are provided in a portion of the substrate body located outside the die pattern to penetrate the substrate body in the thicknesswise direction. First terminals and second terminals are connected to the through conductors, respectively. The first terminals each extend toward the outer edge of the mounting surface, and they are electrically connected to the semiconductor element. The second terminals are provided on a surface of the substrate body opposite to the mounting surface.
Description

BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1A is a plan view showing the structure of a semiconductor-element mounting substrate according to a first embodiment of the present invention.



FIG. 1B is a sectional view of the substrate taken along the line IB-IB in FIG. 1A.



FIG. 2A is a plan view showing the structure of a semiconductor device according to the first embodiment of the present invention.



FIG. 2B is a sectional view of the device taken along the line IIB-IIB in FIG. 2A.



FIG. 3A is a top view of a power amplifier circuit module in which a semiconductor chip of silicon and a semiconductor chip of gallium arsenide are used as IC chips.



FIG. 3B is a right side view of the power amplifier circuit module shown in FIG. 3A.



FIG. 3C is a front view of the power amplifier circuit module shown in FIG. 3A.



FIG. 3D is a bottom view of the power amplifier circuit module shown in FIG. 3A.



FIG. 4A is a plan view showing the structure of a semiconductor-element mounting substrate according to a second embodiment of the present invention.



FIG. 4B is a sectional view of the substrate taken along the line IVB-IVB in FIG. 4A.



FIG. 5A is a plan view showing the structure of a semiconductor device according to the second embodiment of the present invention.



FIG. 5B is a sectional view of the device taken along the line VB-VB in FIG. 5A.



FIG. 6A is a plan view showing the structure of a semiconductor-element mounting substrate according to a third embodiment of the present invention.



FIG. 6B is a sectional view of the substrate taken along the line VIB-VIB in FIG. 6A.



FIG. 7A is a plan view showing the structure of a semiconductor device according to the third embodiment of the present invention.



FIG. 7B is a sectional view of the device taken along the line VIIB-VIIB in FIG. 7A.



FIG. 8A is a top view of a power amplifier circuit module in which a semiconductor chip of silicon and a semiconductor chip of gallium arsenide are used as IC chips.



FIG. 8B is a right side view of the power amplifier circuit module shown in FIG. 8A.



FIG. 8C is a front view of the power amplifier circuit module shown in FIG. 8A.



FIG. 8D is a bottom view of the power amplifier circuit module shown in FIG. 8A.



FIG. 9 is a side view of electronic equipment according to the present invention.



FIG. 10A is a top view of a power amplifier circuit module in which a semiconductor chip of silicon and a semiconductor chip of gallium arsenide are used as IC chips.



FIG. 10B is a sectional view of the module taken along the XB-XB shown in FIG. 10A.



FIG. 11 is a view schematically showing the points of exfoliation of the conventional semiconductor device shown in FIG. 10 which occur when a soldering heat resistance test was conducted on the device.


Claims
  • 1. A semiconductor-element mounting substrate comprising: a substrate body having a mounting surface above which a semiconductor element is mounted;a die pattern provided on the mounting surface and electrically connected to the semiconductor element;a plurality of through conductors provided in a portion of the substrate body located outside the die pattern to penetrate the substrate body in the thicknesswise direction;a plurality of first terminals which are provided on the mounting surface to extend from the through conductors toward the outer edge of the mounting surface and which are electrically connected to the semiconductor element; anda plurality of second terminals which are provided on a surface of the substrate body opposite to the mounting surface and which are connected to the through conductors to make electrical connection to the first terminals, respectively.
  • 2. The substrate of claim 1, wherein at least one of the plurality of first terminals is a first grounding terminal for grounding the die pattern, andthe substrate further comprises a conductive interconnect for electrically connecting the first grounding terminal to the die pattern.
  • 3. The substrate of claim 1, wherein the plurality of first terminals are arranged radically from the die pattern.
  • 4. The substrate of claim 2, wherein a gold film is provided on the conductive interconnect.
  • 5. The substrate of claim 1, wherein at least an insulative coating is provided over a portion of the substrate body which surrounds the die pattern and which is located closer to the mounting surface than the through conductors.
  • 6. The substrate of claim 5, wherein the insulative coating is provided to expand from the top of the die pattern to the surrounding of the die pattern, andin a portion of the insulative coating provided over the die pattern, at least one hole penetrates the portion in the thicknesswise direction to reach the die pattern.
  • 7. The substrate of claim 5, wherein a plurality of insulative coatings are further provided on the die pattern to be arranged separately from each other.
  • 8. The substrate of claim 7, wherein the plurality of insulative coatings are arranged on the die pattern in an array pattern.
  • 9. The substrate of claim 5, wherein a gold film is provided on a portion of the die pattern not provided with the insulative coating, the first and second terminals, and the through conductors.
  • 10. The substrate of claim 1, wherein the substrate body is made of resin.
  • 11. The substrate of claim 1, wherein the insulative coating is made of a photosensitive resin material.
  • 12. A semiconductor device which has a semiconductor element mounted above a semiconductor-element mounting substrate, wherein the semiconductor-element mounting substrate comprising:a substrate body having a mounting surface above which the semiconductor element is mounted;a die pattern provided on the mounting surface and electrically connected to the semiconductor element;a plurality of through conductors provided in a portion of the substrate body located outside the die pattern to penetrate the substrate body in the thicknesswise direction;a plurality of first terminals which are provided on the mounting surface to extend from the through conductors toward the outer edge of the mounting surface and which are electrically connected to the semiconductor element; anda plurality of second terminals which are provided on a surface of the substrate body opposite to the mounting surface and which are connected to the through conductors to make electrical connection to the first terminals, respectively.
  • 13. The device of claim 12, wherein at least one of the plurality of first terminals is a first grounding terminal for grounding the die pattern, andthe semiconductor-element mounting substrate further comprises a conductive interconnect for electrically connecting the first grounding terminal to the die pattern.
  • 14. The device of claim 12, wherein the plurality of first terminals are arranged radically from the die pattern.
  • 15. The device of claim 13, wherein a gold film is provided on the conductive interconnect.
  • 16. The device of claim 12, wherein the outside dimensions of the die pattern are smaller than those of the semiconductor element.
  • 17. The device of claim 12, wherein at least an insulative coating is provided over a portion of the substrate body which surrounds the die pattern and which is located closer to the mounting surface than the through conductors.
  • 18. The device of claim 17, further comprising a sealing resin for sealing the semiconductor element, wherein the sealing resin is bonded to the insulative coating.
  • 19. The device of claim 17, wherein the insulative coating is provided to expand from the top of the die pattern to the surrounding of the die pattern, andin a portion of the insulative coating provided over the die pattern, at least one hole penetrates the portion in the thicknesswise direction to reach the die pattern.
  • 20. The device of claim 17, wherein a plurality of insulative coatings are further provided on the die pattern to be arranged separately from each other.
  • 21. The device of claim 20, wherein the plurality of insulative coatings are arranged on the die pattern in an array pattern.
  • 22. The device of claim 17, wherein a gold film is provided on a portion of the die pattern not provided with the insulative coating, the first and second terminals, and the through conductors.
  • 23. The device of claim 12, wherein the substrate body is made of resin.
  • 24. The device of claim 12, wherein the insulative coating is made of a photosensitive resin material.
  • 25. The device of claim 12, wherein the semiconductor element is provided in plural.
  • 26. The device of claim 25, wherein the device is a power amplifier circuit module including a semiconductor element of silicon and a semiconductor element of gallium arsenide.
  • 27. The device of claim 12, further comprising a wire lead for electrically connecting each of the plurality of first terminals and the semiconductor element.
  • 28. Electronic equipment comprising the semiconductor device of claim 12.
Priority Claims (1)
Number Date Country Kind
2006-001586 Jan 2006 JP national