The present invention relates in general to semiconductor devices and, more particularly, semiconductor devices with a wire bonding structure that eliminates the requirement for a wire bonding finish and reduces bonding pitch on substrates.
Semiconductor devices are found in many products used in modern society. Semiconductors find applications in consumer items such as entertainment, communications, and household items markets. In the industrial or commercial market, semiconductors are found in military, aviation, automotive, industrial controllers, and office equipment.
The manufacture of semiconductor devices begins with formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other electrical devices for performing one or more electrical functions. For a given wafer, each die from the wafer performs the same electrical function. Front-end manufacturing generally refers to formation of the transistors on the wafer. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
The package has external metal contacts for propagating electrical signals into and out of the die. The die has a number of bonding pads which are connected to the external contacts of the package by wire bonds. Wire bonding provides an electrical interconnect between the semiconductor device and other circuitry external to the semiconductor package. The wire bonds are used to make connections between pads at the active surface of the die and bond sites on a lead frame or bond fingers on the substrate.
Wire bonding typically involves an electrolytic plating process that uses a plating buss to apply a layer of gold (bout 0.5 microns) over a layer of nickel (about 5-10 microns). Unfortunately, the plating buss occupies space, which is problematic in high density designs. In addition, the plating buss causes undesirable parasitic effects and requires another processes step to remove the buss. It is desirable to eliminate the nickel-based electroplating process and platting buss from the wire bonding requirements.
In one embodiment, the present invention is a semiconductor package comprising a substrate and a semiconductor die disposed on the substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The second bonding site has a bond finger formed on the substrate, a copper layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the copper layer to conduct an electrical signal from the semiconductor die to the bond finger.
In another embodiment, the present invention is a semiconductor package comprising a substrate and a semiconductor die disposed on the substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger.
In another embodiment, the present invention is a semiconductor package bonding site comprising a bond wire, a bond finger, a conductive layer in contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal.
In another embodiment, the present invention is a method of making a semiconductor package comprising the steps of forming a substrate, disposing a semiconductor die on the substrate, and connecting a bond wire between a first bonding site on the semiconductor die and a second bonding site on the substrate. The step of connecting the bond wire includes forming a bond finger on the substrate, forming a conductive layer in direct physical contact with the bond finger, and forming a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger.
The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
The manufacture of semiconductor devices begins with the formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other electrical devices for performing one or more electrical functions. For a given wafer, each die from the wafer performs the same electrical function. Front-end manufacturing generally refers to formation of the transistors on the wafer. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
The package has external metal contacts for propagating electrical signals into and out of the die. The die has a number of bonding pads which are connected to the external contacts of the package by wire bonds. Wire bonding provides an electrical interconnect between the semiconductor device and other circuitry external to the semiconductor package. The wire bonds are used to make connections between pads at the active surface of the die and bond sites on a lead frame or bond fingers on the substrate.
In
Wire bond 26 is formed using machinery including a capillary bonding tool, a support for the device to be wire-bonded, a source of heat, a source and transducer to impart ultrasound vibration to the capillary bonding tool, and automated control for coordinating the movement and function of these machinery elements. A wire, typically of aluminum or gold, is carried in the lumen of the capillary, and the machinery controls the movement of the wire through the tip of the capillary. To form a wire bond as shown for example in
To form the ball bond, an electric arc is struck to form a molten ball at the projecting end of the wire. The capillary moved over the die and substrate so that the tip is aligned in the x-y plane over the target bonding site, e.g., the die pad. Tension is drawn on the wire to pull the ball back into a chamfer in the capillary tip as the capillary is lowered to bring the ball into contact with the target bonding site. The capillary is moved in the “z”-direction to press the ball against the bonding site, and the transducer is activated to impart an ultrasonic vibration to the capillary. The capillary tip, and in particular the chamfer which grips the ball, imparts a vibration to the ball as it is compressed against the target. A metallurgic bond is formed between the ball and target, completing the ball bond.
To form the wire loop, the wire is fed through the capillary, which is raised away from the target, and then moved in a controlled path in relation to the die and substrate toward a position where it is aligned in the x-y plane over the second target bonding site to control the eventual shape of the completed wire bond.
To form a stitch bond to bond finger 32, the capillary is lowered to press the wire against the bonding finger site, and again the transducer is activated to impart a vibration to the wire as it is squashed against the target site, forming a metallurgic bond between the wire and target site. The capillary is moved along the bond site, and is then raised, forming a tail of wire projecting from the capillary tip. Finally, the wire is gripped as the capillary is raised further, causing the wire to break near the second bond and leaving the tail of wire projecting from the capillary tip, ready for formation of a subsequent ball by electric arc at the wire end.
The ball bond is shown in two views at
As is shown particularly in
The process described above is often referred to as a forward wire bonding process, by contrast with a reverse wire bonding process. In a reverse wire bonding process, the ball bond is formed on the lead finger flat or pad, and the stitch bond is formed on the die pad. It may be advisable where a reverse wire bonding process connects a substrate with a die, to raise the second end of the wire, near the stitch bond, to avoid contact of the wire with the active surface of the die. Accordingly in a reverse wire bonding process a ball may be formed on the die pad, upon which the stitch bond is formed. Such a procedure is shown in U.S. Pat. No. 6,561,411.
An illustrative example of a reverse wire bond interconnect is shown in
Where forward wire bonding is employed, it might be possible in principle to make the pitch of the interconnections on the substrate smaller by reducing the width of the bonding sites. Proper alignment and consequences of misalignment of a stitch bond with a narrower bond finger are illustrated in
Where the alignment is sufficiently precise, as illustrated in an ideal case in
Where the alignment is less than perfect, as illustrated in
The bond finger is narrow at the stitch bond site, a pedestal is formed on the narrow bond site, and the stitch bond is formed on the pedestal. The pedestal can be formed as a ball in the manner of forming a stud bump. That is, wire bonding apparatus is employed to form a ball on the narrow bond finger as if forming a ball bond interconnection, but then, instead of drawing the wire to form a loop, the wire is clamped as the capillary is moved upward, so that the wire breaks off just above the ball, leaving a tail. The top of the ball, including the wire tail, may be flattened by coining to form a generally flattened surface before the stitch bond is formed. The stitch bond is formed generally as described above with reference to
A resulting second bond is shown in
Inasmuch as the wire length and substrate area depend upon the lead finger bond pitch, reduction of the bond pitch can result in significant shortening of wire lengths and reduction of substrate area.
As may be appreciated, the feature width may vary among the various leads and lead fingers on the substrate, and may vary along the length of a given lead or lead finger, the lead finger is less than the support pedestal diameter at the bond site, that is, at the place along the length of the lead where the support pedestal is formed; the trace may be narrower or wider at other points, so long as the desired lead finger density and lead finger bond pitch is obtained.
Referring to
In practice, even where the lead finger width at the bond site is minimized as shown in
A first row of support pedestals 72 are formed at the exposed lead finger bond sites of lead fingers 71 on the lower tier of substrate 112, and a second row of support pedestals 172 are formed at the lead finger bond sites of lead fingers 171 on the upper tier of substrate 112. Wire bonds are formed between the die pads 22 and the respective bond fingers, alternately 71, 171, by forming a ball bond 24 on die pad 22, drawing wire 66, 166 to the respective lead finger 71, 171 bond site, and forming stitch bond 74, 174 on support pedestal 72, 172, as described with reference to
Stages in a generalized process for making a wire bind interconnect are illustrated in
The above stitch bond requires additional manufacturing steps to plate the Ni layer, or other finish like silver (Ag) or palladium (Pd) over the Cu layer to render the surface wire bondable. The stitch bond requires a plating buss for the plating process, which must be later removed. The Ni layer increases the bond finger pitch by plating the side walls and forming stubs which remain from the plating buss. It is desirable to eliminate electrolytic nickel-gold plating as well as the plating buss from the wire bonding process to reduce manufacturing steps, space requirements, bonding finger pitch, and parasitic effects.
In
Further detail of interconnect pad 242 is shown in
While bonding to bare copper layer 250 remains the preferred embodiment, it remains an option in some cases to add a very thin protective finish to bond finger 234, although not by electroplating. The protective finish may be tin (Sn), Au, Ni, Pd, or combination thereof, deposited by an electroless or immersion process, which still avoids the need for a plating buss. The protective finish can also be an oxide layer, which is deposited as a thin film or grown on the copper surface. For example, the oxide can be black oxide or indium tin oxide (ITO). The thickness of the protective finish is 0.005-0.05 microns.
Nonetheless, the direct application of stitch bond stud 252 on copper layer 250 remains the optimal solution and eliminates the plating tie bars on the substrate, which frees up real estate for routing and prevents electrical parasitics arising from the tie bars and reduces the effective bond finger pitch for wire bonding which could result in shorter wires and smaller package size. The bonding process disclosed herein maximizes density, minimizes final bond finger pitch, and reduces manufacturing costs. The technique is most appealing for laminate substrates; however, it could be applied to leadframes wherein selective Ag plating steps could be eliminated.
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
The present invention is a continuation of co-pending U.S. patent application Ser. No. 11/839,020 filed Aug. 15, 2007, which is a continuation-in-part application of and claims priority from U.S. patent application Ser. No. 11/273,635, filed Nov. 14, 2005, now U.S. Pat. No. 7,453,156, which claims priority from U.S. Provisional Patent Application Ser. No. 60/627,650, filed Nov. 12, 2004.
Number | Name | Date | Kind |
---|---|---|---|
4521476 | Asai et al. | Jun 1985 | A |
4742023 | Hasegawa | May 1988 | A |
5007576 | Congleton et al. | Apr 1991 | A |
5328079 | Mathew et al. | Jul 1994 | A |
5329157 | Rosotker | Jul 1994 | A |
5340770 | Allman et al. | Aug 1994 | A |
5444303 | Greenwood et al. | Aug 1995 | A |
5465899 | Quick et al. | Nov 1995 | A |
5561086 | Rostoker | Oct 1996 | A |
5578981 | Tokuda | Nov 1996 | A |
5654585 | Nishikawa | Aug 1997 | A |
5686762 | Langley | Nov 1997 | A |
5734559 | Banerjee et al. | Mar 1998 | A |
5735030 | Orcutt | Apr 1998 | A |
5818144 | Kim | Oct 1998 | A |
5904288 | Humphrey | May 1999 | A |
5960262 | Torres et al. | Sep 1999 | A |
5976964 | Ball | Nov 1999 | A |
5994169 | Lamson et al. | Nov 1999 | A |
6008532 | Carichner | Dec 1999 | A |
6008542 | Takamori | Dec 1999 | A |
6034440 | Ball | Mar 2000 | A |
6046075 | Manteghi | Apr 2000 | A |
6114239 | Lake et al. | Sep 2000 | A |
6137168 | Kirkman | Oct 2000 | A |
6158647 | Chapman et al. | Dec 2000 | A |
6165887 | Ball | Dec 2000 | A |
6194786 | Orcutt | Feb 2001 | B1 |
6294830 | Fjelstad | Sep 2001 | B1 |
6329278 | Low et al. | Dec 2001 | B1 |
6333562 | Lin | Dec 2001 | B1 |
6359341 | Huang et al. | Mar 2002 | B1 |
6420256 | Ball | Jul 2002 | B1 |
6462414 | Anderson | Oct 2002 | B1 |
6495773 | Nomoto et al. | Dec 2002 | B1 |
6541848 | Kawahara et al. | Apr 2003 | B2 |
6561411 | Lee | May 2003 | B2 |
6597065 | Efland | Jul 2003 | B1 |
6624059 | Ball | Sep 2003 | B2 |
6713881 | Umehara et al. | Mar 2004 | B2 |
6787926 | Chen et al. | Sep 2004 | B2 |
6815836 | Ano | Nov 2004 | B2 |
6849931 | Nakae | Feb 2005 | B2 |
6927479 | Ramakrishna | Aug 2005 | B2 |
6956286 | Kuzawinski et al. | Oct 2005 | B2 |
7005752 | Bojkov et al. | Feb 2006 | B2 |
7135759 | Efland et al. | Nov 2006 | B2 |
7190060 | Chiang | Mar 2007 | B1 |
7375978 | Conner et al. | May 2008 | B2 |
7582966 | Lin et al. | Sep 2009 | B2 |
7665652 | Mis et al. | Feb 2010 | B2 |
8030775 | Lin | Oct 2011 | B2 |
20020043712 | Efland | Apr 2002 | A1 |
20020043723 | Shimizu et al. | Apr 2002 | A1 |
20020177296 | Ball | Nov 2002 | A1 |
20030015784 | Liaw et al. | Jan 2003 | A1 |
20030057559 | Mis et al. | Mar 2003 | A1 |
20030089521 | Lee et al. | May 2003 | A1 |
20040152292 | Babinetz et al. | Aug 2004 | A1 |
20050133928 | Howard et al. | Jun 2005 | A1 |
20060049523 | Lin | Mar 2006 | A1 |
20060102694 | Lee et al. | May 2006 | A1 |
20060113665 | Lee et al. | Jun 2006 | A1 |
20070026631 | Lin et al. | Feb 2007 | A1 |
20080042280 | Lin et al. | Feb 2008 | A1 |
20080054457 | Lin et al. | Mar 2008 | A1 |
20090206486 | Lin | Aug 2009 | A1 |
Number | Date | Country |
---|---|---|
09082742 | Mar 1997 | JP |
2003234427 | Aug 2003 | JP |
Number | Date | Country | |
---|---|---|---|
20110089566 A1 | Apr 2011 | US |
Number | Date | Country | |
---|---|---|---|
60627650 | Nov 2004 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 11839020 | Aug 2007 | US |
Child | 12973410 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 11273635 | Nov 2005 | US |
Child | 11839020 | US |