Patent Application
20250046753
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging, for example.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Various embodiments provide methods applied to forming a 3D integrated chip (3DIC) package, such as a system on integrated chip (SoIC) package. Forming the integrated chip package comprises bonding two or more semiconductor dies (e.g., top dies) to a semiconductor wafer (e.g., a bottom die). A dielectric layer (e.g., an oxide) is formed on top surfaces and sidewalls of the semiconductor dies, and on bottom surfaces of gaps between the semiconductor dies. A molding compound is then formed to fill the remainder of the gaps. Advantageous features of one or more embodiments disclosed herein may include better bonding strength of the dielectric layer as compared to the molding compound, allowing improved bonding of the semiconductor dies to the semiconductor wafer. In addition, the dielectric layer has a lower thermal expansion than the molding compound during a thermal process that is used to cure the molding compound. As a result, each semiconductor die has a better bending resistance at each die corner, and a risk of delamination of the semiconductor die is reduced. This further results in a more robust integrated chip package, with better electrical connection to any external devices (e.g., a package substrate), which allows for an enhancement in device reliability.
The substrate 117 of the wafer 10 may include a crystalline silicon wafer. The substrate 117 may include various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for n-type Fin-type Field Effect Transistors (FinFETs) and/or p-type FinFETs. In some alternative embodiments, the substrate 117 may comprise an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 117 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.
Active and/or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the substrate 117. The devices may be interconnected by the interconnect structure 119. The interconnect structure 119 electrically connects the devices on the substrate 117 to form one or more integrated circuits. The interconnect structure 119 may include one or more dielectric layers (for example, one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, or the like) and interconnect wirings or metallization patterns embedded in the one or more dielectric layers. The material of the one or more dielectric layers may include silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0), or other suitable dielectric material. The interconnect wirings may include metallic wirings. For example, the interconnect wirings include copper wirings, copper pads, aluminum pads or combinations thereof that are formed by one or more single damascene processes, dual damascene processes, or the like. The side of the wafer 10 comprising an exposed back side surface of the substrate 117 may also be referred to subsequently as the back side of the wafer 10.
The bonding layer 121 may comprise a dielectric layer. Bonding pads 123 are embedded in the bonding layer 121, and the bonding pads 123 allow connections to be made to the interconnect structure 119 and the devices on the substrate 117. The material of the bonding layer 121 may be silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0), tetraethyl orthosilicate (TEOS), or other suitable dielectric material, and the bonding pads 123 may comprise conductive pads (e.g., copper pads), conductive vias (e.g., copper vias), or combinations thereof. The bonding layer 121 may be formed by depositing a dielectric material over the interconnect structure 119 using a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process); patterning the dielectric material to form the bonding layer 121 including openings or through holes; and filling conductive material in the openings or through holes defined in the bonding layer 121 to form the bonding pads 123 embedded in the bonding layer 121.
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After the thinning process described above, the wafer 10 is then mounted to a tape (not shown in the
A blade dicing process 128 is then performed along dicing paths 129 (indicated by the dashed lines in
Each singulated semiconductor die 150 comprises a top portion of the semiconductor die 150A and a bottom portion of the semiconductor die 150B. The bottom portion of the semiconductor die 150B may have a larger width W1 than a width W2 of the top portion of the semiconductor die 150A. In this way, each sidewall of the bottom portion of the semiconductor die 150B is offset from a respective sidewall of the top portion of the semiconductor die 150A by a width W3. Each of the semiconductor dies 150 may have stepped surfaces 117A, which also define top surfaces of the bottom portion of the semiconductor die 150B. Each stepped surface 117A may have the width W3. In an embodiment, the stepped surfaces 117A may be rounded or be a curved surface. A cleaning process or rinse may then be performed to clean surfaces of the semiconductor dies 150. In an embodiment, the cleaning process may comprise exposing the surfaces of the semiconductor dies 150 to a cleaning solution, de-ionized water, or the like.
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A bonding layer 221 is disposed on the interconnect structure 219, and bonding pads 223 are disposed in the bonding layer 221. The bonding pads 223 allow connections to be made to the interconnect structure 219 and the devices on the substrate 217. The wafer 20 further includes through substrate vias (TSVs) 211 which may be electrically connected to the metallization patterns in the interconnect structure 219. The TSVs 211 may be formed by forming recesses in the substrate 217 by, for example, etching, milling, laser techniques, a combination thereof, and/or the like. A thin barrier layer may be conformally deposited over the front side of the substrate 217 and in the openings, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and/or the like. The barrier layer may comprise a nitride or an oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, and/or the like. A conductive material is deposited over the thin barrier layer and in the openings. The conductive material may be formed by an electro-chemical plating process, CVD, ALD, PVD, a combination thereof, and/or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, and/or the like. Excess conductive material and barrier layer may be removed from the front side of the substrate 217 by, for example, chemical mechanical polishing. Thus, in some embodiments, the TSVs 211 may comprise a conductive material and a thin barrier layer between the conductive material and the substrate 217. In subsequent processing steps, the substrate 217 may be thinned to expose the TSVs 211 (see
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As an example hybrid bonding process starts with aligning the semiconductor dies 150 with the wafer 20, for example, by applying a surface treatment to one or more of the bonding layer 121 or the bonding layer 221. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water, or the like) that may be applied to one or more of the bonding layer 121 or the bonding layer 221. The hybrid bonding process may then proceed to aligning the bonding pads 123 to the bonding pads 223. Next, the hybrid bonding includes a pre-bonding step, during which the semiconductor dies 150 are put in contact with the wafer 20. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). The hybrid bonding process continues with performing an anneal, for example, at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, so that the metal in bonding pads 123 (e.g., copper) and the metal of the bonding pads 223 (e.g., copper) inter-diffuses to each other, and hence the direct metal-to-metal bonding is formed. Although four semiconductor dies 150 are illustrated as being bonded to the wafer 20, other embodiments may include any number of semiconductor dies 150 bonded to the wafer 20. After bonding the semiconductor dies 150 to the wafer 20, gaps 127 may be disposed between sidewalls of adjacent semiconductor dies 150. For example a lower portion of each gap 127B may be disposed between sidewalls of adjacent bottom portions of the semiconductor dies 150B, while an upper portion of each gap 127A may be disposed between sidewalls of adjacent top portions of the semiconductor dies 150A. The upper portion of the gap 127A may have a larger width than the lower portion of the gap 127B.
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Advantages can be achieved by forming the dielectric layer 130 on the top surfaces and sidewalls of the semiconductor dies 150, as well as within the gaps 127, with the dielectric layer 130 having the thickness T1 that is in a range from 0.1 μm to 2 μm. These advantages include the dielectric layer 130 having high bonding strength which results in improved bonding of the semiconductor dies 150 to the semiconductor wafer 20. As a result, each semiconductor die 150 has a better bending resistance at each die corner, and a risk of delamination of the semiconductor die 150 is reduced. For example, the dielectric layer 130 having a thickness that is lower than 0.1 μm would result in an insufficient bonding strength between the semiconductor dies 150 and the semiconductor wafer 20, resulting in an increased risk of delamination of the semiconductor dies 150. Additional advantages may be achieved by forming the dielectric layer 130 over the stepped surfaces 117A of the semiconductor dies 150. These include allowing for more dielectric material to be deposited on each semiconductor die 150 as a result of the increased surface area available due to the step structure of the stepped surfaces 117A. This allows for even better bonding strength and improves the bonding between the semiconductor dies 150 to the semiconductor wafer 20.
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Advantages can be achieved by forming the dielectric layer 130 and the molding material 132 within the gaps 127, such that the dielectric layer 130 is disposed between the sidewalls of the semiconductor dies 150 and the molding material 132, and between the wafer 20 and the molding material 132, wherein the dielectric layer 130 has the thickness Ti that is in a range from 0.1 μm to 2 μm. These advantages include the dielectric layer 130 having a lower co-efficient of thermal expansion than the molding material 132, the co-efficient of thermal expansion of the dielectric layer 130 being in a range from 0.1 μm/m·° C. to 5 μm/m·° C., such that during the curing process described above that is used to cure the molding material 132, the dielectric layer 130 undergoes a smaller amount of thermal expansion. As a result, each semiconductor die 150 has a better bending resistance at each die corner, and a risk of delamination of the semiconductor die 150 is reduced. For example, the dielectric layer 130 having a thickness that is lower than 0.1 μm would allow the molding material to be excessively close to the die corners of the semiconductor dies 150, and the thermal expansion of this molding material 132 would result in an increased risk of delamination of the semiconductor dies 150. Therefore, forming the dielectric layer 130 and the molding material 132 within the gaps 127 as described above, wherein the dielectric layer 130 has the thickness T1 that is in a range from 0.1 μm to 2 μm, results in a more robust integrated chip package 100, with better electrical connection to any external devices (e.g., a package substrate), which allows for an enhancement in device reliability.
After the formation of the molding material 132, a planarization process is performed to remove excess portions of the molding material 132. In addition, during the planarization process, portions of the dielectric layer 130 are also removed to expose top surfaces of the semiconductor dies 150. The planarization process may comprise a grinding process, a CMP process, or the like. As illustrated in
After the planarization process, a carrier substrate 136 is attached to the planarized surfaces of the semiconductor dies 150, the dielectric layer 130, and the molding material 132. In an embodiment the carrier substrate 136 comprises, for example, silicon based materials, such as glass or silicon oxide, or other materials, such as aluminum oxide, combinations of any of these materials, or the like. The carrier substrate 136 is planar in order to accommodate the attachment of the semiconductor dies 150, the dielectric layer 130, and the molding material 132, which may be attached using a release layer 134. The release layer 134 may be formed of a polymer-based material, which may be removed along with the carrier substrate 136 from the underlying structures in subsequent steps. In some embodiments, the release layer 134 is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 134 may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer 134 may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate 136, or the like. The top surface of the release layer 134 may be leveled and may have a high degree of planarity.
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In another embodiment, the polymer layer 234 may be patterned to form the openings that expose the TSVs 211 by initially applying a photoresist (not individually illustrated in
Conductive connectors 238 are then formed over the polymer layer 234 and in the openings of the polymer layer 234. The conductive connectors 238 are electrically coupled to the semiconductor dies 150 through the TSVs 211. The conductive connectors 238 may comprise controlled collapse chip connection (C4) bumps, ball grid array (BGA) connectors, solder balls, or the like. The conductive connectors 238 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 238 are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes.
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The substrate core 260 may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the device stack. The devices may be formed using any suitable methods.
The substrate core 260 may also include metallization layers and vias (not shown), with the bond pads 246 being physically and/or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric material (e.g. low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate core 260 is substantially free of active and passive devices.
In some embodiments, the conductive connectors 238 are reflowed to attach the singulated device stack from one of the first package region 200A or the second package region 200B to the bond pads 246. The conductive connectors 238 electrically and/or physically couple the package substrate 240, including metallization layers in the substrate core 260, to the singulated device stack. In some embodiments, a solder resist 248 is formed on the substrate core 260. The conductive connectors 238 may be disposed in openings in the solder resist 248 to be electrically and mechanically coupled to the bond pads 246. The solder resist 248 may be used to protect areas of the substrate core 260 from external damage.
The conductive connectors 238 may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the singulated device stack is attached to the package substrate 240. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from reflowing the conductive connectors 238. In some embodiments, an underfill 250 may be formed between the singulated device stack and the package substrate 240, and surrounding the conductive connectors 238. The underfill 250 may be formed by a capillary flow process after the coupling of the singulated device stack to the package substrate 240 or may be formed by a suitable deposition method before the package substrate 240 is coupled to the singulated device stack.
In an embodiment, the package substrate 240 may comprise bond pads 252 over the substrate core 260. Conductive connectors 254 may be coupled to the bond pads 252 to allow for the electrical coupling of the package substrate 240 to external circuits or devices. The conductive connectors 254 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors 254 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the solder resist 248 is formed on the substrate core 260 and the conductive connectors 254 may be disposed in openings in the solder resist 248 to be electrically and mechanically coupled to the bond pads 252. The solder resist 248 may be used to protect areas of the substrate core 260 from external damage.
In some embodiments, passive devices (e.g., surface mount devices (SMDs), not shown) may also be attached to the package substrate 240 (e.g., to the bond pads 246). For example, the passive devices may be bonded to a same surface of the package substrate 240 as the conductive connectors 238.
The embodiments of the present disclosure have some advantageous features. The embodiments include a method for the formation of an integrated chip package. Forming the integrated chip package comprises bonding two or more semiconductor dies (e.g., top dies) to a semiconductor wafer (e.g., a bottom die). A dielectric layer (e.g., an oxide) is formed on top surfaces and sidewalls of the semiconductor dies, and on bottom surfaces of gaps between the semiconductor dies. A molding compound is then formed to fill the remainder of the gaps. As a result, the better bonding strength of the dielectric layer as compared to the molding compound allows for improved bonding of the semiconductor dies to the semiconductor wafer. In addition, the dielectric layer has a lower thermal expansion than the molding compound during a thermal process that is used to cure the molding compound. As a result, each semiconductor die has a better bending resistance at each die corner, and a risk of delamination of the semiconductor die is reduced. This further results in a more robust integrated chip package, with better electrical connection to any external devices (e.g., a package substrate), which allows for an enhancement in device reliability.
In accordance with an embodiment, a method of manufacturing a semiconductor device includes singulating a first wafer to separate a first die of the first wafer from a second die of the first wafer; bonding the first die and the second die to a first side of a second wafer, where after bonding the first die and the second die to the first side of the second wafer, a gap is disposed between the first die and the second die, where a first dielectric layer of each of the first die and the second die is directly bonded to a second dielectric layer of the second wafer, and where a first portion of the gap has a first width that is larger than a second width of a second portion of the gap; depositing a third dielectric layer on top surfaces and sidewalls of the first die and the second die, as well as on a bottom surface within the gap; forming a molding material over the third dielectric layer to fill the gap; performing a planarization process to expose top surfaces of the first die and the second die; and coupling a package substrate to a second side of the second wafer using conductive connectors, the second side of the second wafer being an opposite side of the second wafer as the first side of the second wafer. In an embodiment, the third dielectric layer includes silicon oxide, silicon oxynitride, silicon carbon nitride or tetraethyl orthosilicate. In an embodiment, a thickness of the third dielectric layer is in a range from 0.1 μm to 2 μm. In an embodiment, a material of the third dielectric layer is different from a material of the first dielectric layer and the second dielectric layer. In an embodiment, performing the planarization process further includes removing a portion of the third dielectric layer and a portion of the molding material, where after performing the planarization process, the top surfaces of the first die and the second die are level with top surfaces of the third dielectric layer and the molding material. In an embodiment, the method further includes after performing the planarization process, attaching a carrier substrate to the top surfaces of the first die and the second die, and the planarized surfaces of the third dielectric layer and the molding material; and thinning a back side of a substrate of the second wafer to expose through substrate vias (TSVs) within the second wafer. In an embodiment, singulating the first wafer to separate the first die of the first wafer from the second die of the first wafer includes performing a plasma dicing process on a first side of the first wafer to form a first groove and a second groove that are disposed between adjacent sidewalls of the first die and the second die; and performing a blade dicing process on a second side of the first wafer to form a trench, where the trench overlaps and connects to the first groove and the second groove.
In accordance with an embodiment, a method of manufacturing a semiconductor device includes bonding a plurality of dies to a wafer, where after bonding the plurality of dies to the wafer, a gap is disposed between adjacent dies of the plurality of dies, where a top portion of the gap has a larger width than a width of a bottom portion of the gap; depositing a first dielectric layer on sidewalls of the adjacent dies within the gap, as well as on a bottom surface of the gap, where the first dielectric layer fills the bottom portion of the gap; forming a molding material to fill the top portion of the gap; and planarizing the molding material such that a top surface of the molding material is level with top surfaces of the adjacent dies of the plurality of dies. In an embodiment, the first dielectric layer isolates the molding material from the sidewalls of the adjacent dies, and from a top surface of the wafer within the gap. In an embodiment, a thickness of the first dielectric layer is in a range from 0.1 μm to 2 μm. In an embodiment, the method further includes planarizing the first dielectric layer such that a top surface of the first dielectric layer is level with the top surface of the molding material and the top surfaces of the adjacent dies of the plurality of dies. In an embodiment, each of the plurality of dies includes a top portion having a first width; and a bottom portion having a second width, the second width being larger than the first width. In an embodiment, after planarizing the molding material, the first dielectric layer is in physical contact with top surfaces of the bottom portion of each of the plurality of dies. In an embodiment, the first dielectric layer includes an oxide.
In accordance with an embodiment, a package includes a first die and a second die over and bonded to a first side of a third die, where the first die and the second die include top portions; and bottom portions, where each top portion has a first width, and each bottom portion has a second width that is larger than the first width; a first dielectric layer disposed on adjacent sidewalls of the top portions and on adjacent sidewalls of the bottom portions; and a molding material over the first dielectric layer, where the molding material is disposed above the bottom portions of the first die and the second die, and where a top surface of the molding material is level with a top surface of the first dielectric layer. In an embodiment, a thickness of the first dielectric layer is in a range from 0.1 μm to 2 μm. In an embodiment, the first dielectric layer isolates the molding material from the first die and the second die. In an embodiment, a co-efficient of thermal expansion of the first dielectric layer is lower than a co-efficient of thermal expansion of the molding material. In an embodiment, the first dielectric layer is in physical contact with top surfaces of the bottom portions of the first die and the second die. In an embodiment, the package further includes a package substrate coupled to a second side of the third die using conductive connectors.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
