Patent Application
20140252632
The present disclosure relates generally to semiconductor devices.
In three-dimensional (3D) chip stacks, two or more semiconductor chips may be stacked on top of each other. Adjacent chips in the stack may be electrically coupled to one another via an interface. The physical design of the interface may be predetermined or fixed according to a given standard. For example, geometric dimensions of the interface, such as length, width, pad pitch, etc., may be prescribed by the standard. For example with increasing scaling in semiconductor technology, chip sizes may come close to or become even smaller than the prescribed geometric dimensions of the interface. For example, a chip may have a length that is smaller than a length of the interface as prescribed by the standard. In this case, it may be desirable to modify the chip to fit to the partly larger interface.
A semiconductor device is provided which may include: a semiconductor chip; an extension layer extending laterally from a boundary of the semiconductor chip; a redistribution layer disposed over at least one side of the extension layer and the semiconductor chip, wherein the redistribution layer electrically couples at least one contact of the semiconductor chip to at least one contact of an interface, wherein at least a part of the interface extends laterally beyond the boundary of the semiconductor chip.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects are described with reference to the following drawings, in which:
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects of this disclosure in which the invention may be practiced. These aspects of this disclosure are described in sufficient detail to enable those skilled in the art to practice the invention. Other aspects of this disclosure may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects of this disclosure are not necessarily mutually exclusive, as some aspects of this disclosure can be combined with one or more other aspects of this disclosure to form new aspects.
The word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface, may be used to mean that the feature, e.g. the layer, may be disposed or formed “directly on”, e.g. in direct contact with, the implied side or surface. The word “over”, used herein to describe forming a feature, e.g. a layer “over” a side or surface, may be used to mean that the feature, e.g. the layer, may be disposed or formed “indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the formed layer.
The terms “coupled” and/or “electrically coupled” and/or “connected” and/or “electrically connected”, used herein to describe a feature being connected to at least one other implied feature, are not meant to mean that the feature and the at least one other implied feature must be directly coupled or connected together; intervening features may be provided between the feature and at least one other implied feature.
The terms “at least one” and “one or more” may be understood to include any integer number greater than or equal to one, i.e. “one”, “two”, three”, “four”, etc.
The term “a plurality of” may be understood to include any integer number greater than or equal to two, i.e. “two”, “three”, “four”, “five”, etc.
The term “standardized” as used herein may, for example, be understood as meaning “according to a standard” or “defined by a standard”, for example according to or defined by a standard developed by a standardization committee, body or organization such as JEDEC (Joint Electron Device Engineering Council) or others.
In one or more aspects, the present disclosure relates to three-dimensional (3D) chip stacks such as, for example, stacks of logic and memory chips. The following description will mainly refer to logic/memory chip stacks as an example, however the present disclosure is not limited to this case and may be applied to stacking of any two or more chips in general. For example, the stacking of logic chips on logic chips; the stacking of logic chips with RF chips, analog/mixed signal chips or power chips; the stacking of chips with sensors, with micro electro mechanical systems (MEMS) or CMOS image sensors, and any other combination of 3D stacks.
Memory chips or a stack of memory chips may, for example, include or consist of dynamic random access memory (DRAM) memory chips with a ‘Wide I/O (Input/Output)’ interface (JEDEC standard). As will be readily understood, the present disclosure may not be limited to this particular case.
One important aspect of 3D logic/memory chip stacks with ‘wide I/O’ interface is the fact that the size of the logic/memory interface is fixed to 0.52 mm×5.25 mm according to the JEDEC standard.
However, especially in mobile applications many logic chips (especially in future technology nodes beyond 28 nm) may have a chip size that may come close to or even smaller as compared to the length (5.25 mm) of the ‘wide I/O’ standard. Therefore a cost effective solution may be needed to modify a small logic chip to fit to the partly larger ‘wide I/O’ interface stacked on top.
As shown in
Details of the ‘wide I/O’ interface of a typical DRAM memory, such as memory 204, as defined by the JEDEC standard, include, for example:
That is, the ‘wide I/O’ interface according to the JEDEC standard may have a length of 5.25 mm and a width of 0.52 mm.
If, for example, the respective size of the logic chip 101 in
The conventional approach to extend the chip size, as shown in
In one or more aspects, the present disclosure provides a relatively cheap (cost effective) way to increase the size (area) of the logic chip, or in general, of any first chip that shall be coupled to a second chip via an interface that is partly larger than the chip size of the first chip. For example, semiconductor devices in accordance with one or more aspects described herein may apply a relatively cheap (cost effective) fan-out WLP (wafer level package) or eWLB (embedded wafer level package ball grid array) approach to gain enough space for the interface or for the placement of one or more electrically conductive contacts (e.g. pads) connecting to the interface (e.g. logic-memory interface, e.g. ‘wide I/O’ interface).
In particular, an extension layer including or composed of a relatively cheap chip encapsulation material (e.g. a plastic material such as a molding material, or the like) may be used to increase the chip size or area, and a redistribution layer (RDL) disposed over the extension layer may be used to reroute one or more interface connections disposed outside (e.g. at least partially outside, e.g. fully outside) a boundary of the chip (in other words, outside the original chip area) to one or more electrically conductive contacts of the chip inside the boundary of the chip (inside the original chip area). The RDL may be a single level RDL or a multi-level RDL (i.e. an RDL having two or more levels or layers). A multi-level RDL may, for example, be used in cases where a relatively large number of interface interconnections lie outside the boundary of the chip (outside the original chip area).
According to one or more aspects, the present disclosure proposes for chips (e.g. logic chips) that are smaller than the extension of a standardized chip-to-chip interface (e.g. standardized logic-memory interface, e.g. ‘wide I/O’ memory interface according to JEDEC standard) to make use of a fan-out WLP (eWLB) chip extension with a single-level or multi-level RDL to provide the connection to the larger interface (e.g. memory interface). This approach may be significantly more cost effective (cheaper) than the conventional approach to increase the area of the chip, e.g. increase the silicon area of a highly advanced logic chip.
The eWLB RDL is able to reroute one or more interface connections (e.g. ‘wide I/O’ connections) to appropriate areas of the small chip, where the placement of a through-via (e.g. through-silicon via (TSV)) or an array of through-vias (e.g. TSVs) is possible.
The fan-out eWLB RDL may be disposed over one side (e.g. back side) of the chip only or, alternatively, may be disposed over both sides of the chip (i.e. over the back side and over the front side of the chip (e.g. logic chip)).
As an alternative to the through-via (e.g. TSV) connections on the chip (e.g. logic chip), all or a part of the connections may be provided by through-vias (e.g. through mold vias (TMVs)) extending through the extension layer (e.g. mold compound) in the fan-out area of the eWLB package. These through-vias (e.g. TMVs) in combination with the RDL levels are able to connect the interface contacts (e.g. ‘wide I/O’ pads) with the front side (active circuit area) of the small chip (e.g. logic chip) and to an interposer (e.g. laminate interposer) (if necessary even bypassing the small chip (e.g. logic chip)).
The semiconductor device may include a first semiconductor chip 401. According to the example shown, the first semiconductor chip 401 may be a (small) logic chip, similar to logic chip 301 in
The first semiconductor chip 401 is to be electrically coupled to a second semiconductor chip 404 via a standardized chip-to-chip interface 403. According to the example shown, the second semiconductor chip 404 may be a memory chip (e.g. a DRAM chip). Accordingly, the chip-to-chip interface 403 may be a logic-memory interface, e.g. a ‘wide I/O’ logic-memory interface, similar to interface 103 shown in
As shown in
Thus, as may be seen from
As shown, the semiconductor device may further include an extension layer 405 extending laterally from the boundary 401a of the first semiconductor chip 401. As shown in
In general, the extension layer 405 may be formed such that the combined area of the first semiconductor chip 401 and the extension layer 405 may be large enough to fit the size or area of the standardized chip-to-chip interface 403, for example the size or area of a ‘wide I/O’ logic-memory interface. For example, according to the examples shown in
The extension layer 405 may include or may be composed of a material (or materials) different from the first semiconductor chip 401, for example an insulating material, for example a chip encapsulant material, e.g. a plastic material, e.g. a molding material (mold compound). For example, the molding material (mold compound) may be a composite material consisting of a resin (e.g. epoxy resin) and a filler material (e.g. fused silica).
The extension layer 405 may serve as a fan-out extension (fan-out region) of the first semiconductor chip 401 to accommodate one or more electrically conductive contacts (e.g. pads) to be coupled to one or more electrically conductive contacts (e.g. pads) of the interface 403 that lie outside the chip 401's boundary 401a. In other words, electrically conductive contacts of the interface 403 that would no longer fit onto the semiconductor chip 401 because of the first semiconductor chip 401's small size may now be coupled to electrically conductive contacts disposed over the extension layer 405, and a redistribution layer (not shown in
In accordance with one or more aspects, a fan-out WLP (eWLB) package may be provided, which may have a single level or, if needed, a multi-level redistribution layer (RDL) with electrically conductive contacts (e.g. contact pads) in the top RDL metallization level. By this approach it becomes possible to place all necessary contacts (e.g. pads) to a standardized chip-to-chip interface (e.g. logic-memory interface, e.g. ‘wide I/O’ interface (of the memory chip or chip stack)) in the RDL of the chip (e.g. logic chip) either over the fan-out region or over the original chip area. On the original chip (e.g. logic chip) the non-fitting electrically conductive contacts (e.g. non-fitting ‘wide I/O’ pads) may be shifted or rearranged elsewhere and may be connected by the single- or multi-level RDL wiring, as described herein below with reference to
Illustratively, as shown in
The semiconductor device may include the first semiconductor chip 401, which may be configured as a logic chip (e.g. central processing unit (CPU), graphics processing unit (GPU), application processor (AP), base band modem, micro controller, or the like), and the second semiconductor chip 404, which may be configured as a memory chip, e.g. as a DRAM chip, and coupled to the first semiconductor chip 401 via the standardized chip-to-chip interface 403, which may be a logic-memory interface (e.g. a ‘wide I/O logic-memory interface). The second semiconductor chip 404 may be part of a chip stack 804, e.g. a memory chip stack, e.g. a ‘wide I/O’ memory stack, e.g. a DRAM stack, including at least one additional semiconductor chip (e.g. memory chip, e.g. DRAM chip) stacked on top of the second semiconductor chip 404. In the example shown in
The logic-memory interface (e.g. ‘wide I/O’ interface) 403 may extend over the original logic chip size. In other words, the interface 403 may extend beyond the (lateral) boundary 401a of the first semiconductor chip 401, as shown. An extension layer 405 (e.g. fan-out eWLB extension) may extend laterally from the boundary 401a of the small logic chip 401 to increase the chip area of the logic chip 401. A part of the extension layer 405 may be disposed between the first semiconductor chip 401 and the second semiconductor chip 404, for example over a first side 401b of the logic chip 401 facing the second semiconductor chip 404. The first side 401b may be a back side of the first semiconductor chip 401. That is, the first semiconductor chip 401 may be arranged as in a typical flip chip arrangement with a second side 401c (front side or active side) of the first semiconductor chip 401 facing down (facing away from the interface 403 in this case), e.g. towards a ball grid array as shown in
A single-level redistribution layer (RDL) 409 may be disposed over the extension layer 405 for rerouting interface connections (e.g. ‘wide I/O’ connections), e.g. electrically conductive contacts (e.g. pads), 410 (see
The redistribution layer 409, or one or more electrically conductive contacts (e.g. pads) 409a of the redistribution layer 409, may be coupled to corresponding electrically conductive contacts (e.g. pads) 411a, 411b of the first semiconductor chip 401 by means of one or more through-vias 412 (e.g. through-encapsulant vias, e.g. through-mold vias (TMVs)) in the extension layer 405. The electrically conductive contact(s) 411a, 411b of the first semiconductor chip 401 coupled to the redistribution layer 409 (or to the electrically conductive contact(s) 409a of the redistribution layer 409) may be disposed over the first side 401b (e.g. back side) of the first semiconductor chip 401 facing the second semiconductor chip 404, as shown. The first semiconductor chip 401 may include one or more through-vias 417 (e.g. through-silicon vias (TSVs)) coupled to the electrically conductive contact(s) 411a, 411b disposed over the first side 401b and extending to the second side 401c (e.g. front side) of the first semiconductor chip 401 opposite the first side 401b.
The chips of the chip stack 804, e.g. ‘wide I/O’ memory stack, (except for the topmost chip), i.e. the second semiconductor chip 404 and the additional semiconductor chips 404′ and 404″, may also include one more through-vias 418 (e.g. through-silicon vias (TSVs)) extending in each case from a front side to a back side of the respective chip 404, 404′, 404″ to allow for electrical coupling between the individual chips of the chip stack 804 and thus to the first semiconductor chip 401 via the interface 403.
The through-vias 417 through the first semiconductor chip 401 and the through-vias 418 through the chip stack 804 (e.g. ‘wide I/O’ memory stack) as well may be located underneath (or above) the respective electrically conductive contacts (e.g. pads) of the interface 403 (e.g. the ‘wide I/O’ logic/memory interface with 40 μm×50 μm pad pitch), as shown in
However, the through-vias 417 may be located elsewhere and the connection between the electrically conductive contacts (e.g. pads) of the interface 403 (e.g. ‘wide I/O’ interface pads) and the respective through-vias 417 may be provided by a rerouting in the single- or multi-level RDL 409 of the fan-out eWLB package and/or by a back side metallization of the first semiconductor chip 401. By using the rerouting capability of the RDL layers and/or the back side metallization it may be possible to put the through-vias 417 or through-via arrays on any arbitrary and user-defined location on the chips. In addition, by this approach much smaller through-vias (i.e. with smaller diameter) and/or smaller through-via pitches (independent of the interface pad pitch (e.g. ‘wide I/O’ pad pitch)) may be achieved (for example by using through-via diameters of less than 5 μm and/or through-via pitches of less than 10 μm). By this approach a significant amount of precious chip area may be saved.
As in a typical flip chip arrangement, the first semiconductor chip 401 (e.g. the second side, e.g. front side, 401c of the chip 401) may be coupled to a (e.g. multi-level) ball grid array (BGA) package, including for example, an interposer 413 (e.g. a laminate interposer having one or more metallization or interconnect levels) connected to one or more electrically conductive contacts (e.g. pads) on the second side (e.g. front side) 401c of the first semiconductor chip 401 by means of one or more electrical connectors 414 (e.g. solder bumps (as shown), or metal (e.g. Cu) pillars), and a printed circuit board (PCB) 415 connected to the interposer 413 by means of one or more electrical connectors 416 (e.g. solder bumps, as shown).
Alternatively to the flip chip arrangement where the front side (or active side) of the first semiconductor chip 401 faces the ball grid array (BGA), the semiconductor chip 401 may also be arranged such that its front side (or active side) faces away from the BGA and towards the second semiconductor chip 404 or chip stack 804.
In another example, a double-sided eWLB extension with single or multi-level RDL on both sides may be used. This means that an eWLB RDL may be used on the back side of the first semiconductor chip (e.g. logic chip) connecting to the standardized interface 403, e.g. logic-memory interface, e.g. ‘wide I/O memory interface’ (as shown in
As in the example of
One or more electrically conductive contacts (e.g. pads) 410 of the standardized interface 403 may be rerouted via the redistribution layer 409. The contacts 410 may include one or more contacts 410a lying at least partially outside, e.g. fully outside, the boundary 401a of the first semiconductor chip 401, and may possibly also include one or more contacts 410b that lie inside the chip boundary 401a but close to the chip boundary 401a, as described above.
One or more through-vias 412c (e.g. through-encapsulant vias, e.g. through-mold vias (TMVs)) may be provided in the extension layer 405 to electrically couple the rerouted contacts 410 (e.g. contacts 410a and/or 410b) to one or more electrically conductive contacts (e.g. pads) of the first semiconductor chip 401 disposed over the second side (e.g. front side) 401c. To this end, the respective through-via(s) 412c may be coupled to the first portion 409′ of the redistribution layer 409 disposed over the first side 401b of the first semiconductor chip 401 and to the second portion 409″ of the redistribution layer 409 disposed over the second side 401c of the first semiconductor chip 401, and the second portion 409″ of the redistribution layer 409 may further be coupled to the one or more electrically conductive contacts (e.g. pads) of the first semiconductor chip 401 disposed over the second side 401c of the first semiconductor chip 401, for example by means of one or more through-vias 412b (e.g. through-encapsulant vias, e.g. through-mold vias (TMVs)) disposed in the part of the extension layer 405 that is disposed over the second side 401c of the first semiconductor chip 401, i.e. between the first semiconductor chip 401 and the second portion 409″ of the redistribution layer 409. The second portion 409″ of the redistribution layer 409 (or at least a part of the second portion 409″ of the redistribution layer 409) may further be coupled to the interposer 413, e.g. via one or more electrical connectors 414 such as solder bumps (as shown) or metal pillars (e.g. Cu pillars), to provide electrical coupling of the semiconductor device to external devices.
It also be possible, that one or more of the through-vias 412c leading through the extension layer 405 are coupled to a part of the second portion 409″ of the redistribution layer 409 that may be coupled to the interposer 413 but not to the first semiconductor chip 401. For example, in the example shown
One or more electrically conductive contacts (e.g. pads) 410c of the interface 403 that lie well inside the chip boundary 401a (e.g. having a distance of greater than or equal to about 5 μm, e.g. greater than or equal to about 10 μm, from the chip boundary 401a) may be coupled to one or more electrically conductive contacts 411b of the first semiconductor chip 401 that are disposed over the first side (e.g. back side) 401b of the first semiconductor chip 401, e.g. by means of one or more through-vias (e.g. TMVs) 412a disposed in the part of the extension layer 405 that is disposed over the first side (e.g. back side) 401b of the first semiconductor chip 401.
Illustratively,
The examples described herein above in connection with the figures mainly discuss the case that only one lateral dimension (e.g. the length) of the first semiconductor chip is smaller than the respective dimension of the standardized chip-to-chip interface. However, as will be readily understood, one or more aspects described herein may equally apply to the case where more than one lateral dimension of the first semiconductor chip (e.g. length and width) is smaller than the respective dimension of the standardized chip-to-chip interface. For example, if both a length and a width of the first semiconductor chip are smaller than a respective length and width of the standardized interface the extension layer (e.g. eWLB fan-out region) may be configured to increase the original chip area such that the interface fits onto the chip having the extension.
The extension layer and redistribution layer may, for example, be formed using known manufacturing processes for manufacturing eWLB packages.
In accordance with one or more aspects, a semiconductor device may include: a semiconductor chip; an extension layer extending laterally from a boundary of the semiconductor chip; a redistribution layer disposed over at least one side of the extension layer and the semiconductor chip, wherein the redistribution layer electrically couples at least one contact of the semiconductor chip to at least one contact of an interface, wherein at least a part of the interface extends laterally beyond the boundary of the semiconductor chip.
The at least one contact of the interface may be disposed at least partially outside the boundary of the semiconductor chip.
The redistribution layer may include or may be composed of at least one electrically conductive material, for example at least one metal and/or metal alloy, such as e.g. aluminum, copper, an aluminum alloy, and/or a copper alloy.
The redistribution layer may include at least one metallization level. For example, the redistribution layer may have a single metallization level (single-level RDL). Alternatively, the redistribution layer may have a plurality of metallization levels (multi-level RDL).
The at least one contact of the semiconductor chip may include or may be at least one electrically conductive contact. The at least one contact of the semiconductor chip may include or may be at least one pad (also referred to as contact pad), for example a plurality of pads (contact pads).
The semiconductor chip may be a logic chip, e.g. a CPU (central processing unit) or the like.
The semiconductor chip may include or may be composed of any suitable semiconductor material, including compound semiconductors. For example, the semiconductor chip may include silicon or may be a silicon chip.
The interface may be a standardized interface, for example a standardized chip-to-chip interface. The standardized chip-to-chip interface may be a standardized logic-memory interface, for example a ‘wide I/O’ logic-memory-interface.
The standardized interface (e.g. standardized chip-to-chip interface) may have standardized geometric dimensions, for example a standardized length and/or width, and/or a standardized pad pitch. A pad pitch may, for example, refer to a distance between the respective centers of two adjacent pads. In the case of pads arranged in a rectangular array along two main axes (e.g. length axis and width axis), the pad pitch may be the same or may be different for the two axes.
At least one geometric dimension of the semiconductor chip may be smaller than a corresponding geometric dimension of the standardized chip-to-chip interface.
The semiconductor chip may have a smaller length than the standardized interface (e.g. standardized chip-to-chip interface). In other words, the semiconductor chip may be shorter than the standardized interface (e.g. standardized chip-to-chip interface).
The extension layer may be composed of a material (or materials) different from the semiconductor chip.
The extension layer may include or may be composed of an encapsulant material, e.g. chip encapsulant material.
The extension layer may include or may be composed of an insulating material.
The extension layer may include or be composed of a plastic material, e.g. a molding material (e.g. mold compound).
The redistribution layer may include at least one contact (e.g. electrically conductive contact) coupled to the at least one contact (e.g. electrically conductive contact) of the interface (e.g. standardized interface, e.g. standardized chip-top-chip interface) disposed at least partially outside the boundary of the semiconductor chip.
The redistribution layer may further include at least one contact (e.g. electrically conductive contact) coupled to at least one contact (e.g. electrically conductive contact) of the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface) disposed inside the boundary of the semiconductor chip. The at least one contact (e.g. electrically conductive contact) of the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface) disposed inside the boundary of the semiconductor chip may have a distance from the boundary that is greater than or equal to about 5 μm, for example greater than or equal to about 10 μm.
One or more contacts (e.g. electrically conductive contacts) of the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface) may be configured as a pad, e.g. metal pad.
One or more contacts (e.g. electrically conductive contacts) of the redistribution layer may be configured as a pad, e.g. metal pad.
The pad or pads of the redistribution layer may be disposed in a top metallization level of the redistribution layer.
The semiconductor chip may have a smaller pad pitch than the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface). In other words, pads of the semiconductor chip may be arranged at a smaller pitch (distance) than pads of the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface).
The redistribution layer may be disposed over a first side of the semiconductor chip and/or over a second side of the semiconductor chip opposite the first side. For example, a first portion of the redistribution layer may be disposed over the first side of the semiconductor chip and a second portion of the redistribution layer may be disposed over the second side of the semiconductor chip.
The first side may be a back side of the semiconductor chip and the second side may be a front side of the semiconductor chip. The front side of a chip (e.g. of the semiconductor chip) may be an active side (or a side proximate an active area) of the chip, while the back side of a chip (e.g. of the semiconductor chip) may be a side opposite the active side (or a side distal to the active area) of the chip (e.g. semiconductor chip).
The front side (e.g. active side) of the semiconductor chip may face away from the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface). Alternatively, the front side (e.g. active side) of the semiconductor chip may face towards the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface).
The semiconductor chip may include at least one through-via, e.g. a plurality of through-vias, e.g. one or more through-silicon vias (TSVs), extending from the first side (e.g. back side) to the second side (e.g. front side) of the semiconductor chip, which may be electrically coupled to the at least one contact (e.g. electrically conductive contact (e.g. pad)) of the semiconductor chip. The through-via(s), e.g. TSV(s), may, for example, have a diameter of less than or equal to about 10 μm, for example a diameter in the range from about 2 μm to about 10 μm, e.g. a diameter of less than or equal to about 5 μm, for example a diameter in the range from about 2 μm to about 5 μm, although other values may be possible.
The extension layer may be disposed over the first side (e.g. back side) of the semiconductor chip between the semiconductor chip and the redistribution layer.
The extension layer may include at least one through-via (e.g. through-encapsulant via (TEV), e.g. through-mold via (TMV)) electrically coupling at least one contact (e.g. electrically conductive contact) of the semiconductor chip with the redistribution layer (for example, with at least one pad of the redistribution layer), for example a plurality of through-vias (e.g. TEVs, e.g. TMVs) electrically coupling a plurality of contacts (e.g. electrically conductive contacts) of the semiconductor chip with the redistribution layer (for example, with a plurality of pads of the redistribution layer).
The through-via(s) may, for example, have a diameter in the range from about 50 μm to about 100 μm, e.g. a diameter of about 50 μm, although other values may be possible as well.
The redistribution layer may include a first portion disposed over a first side (e.g. back side) of the semiconductor chip and a second portion disposed over a second side (e.g. front side) of the semiconductor chip opposite the first side.
The first portion of the redistribution layer may include at least one contact (e.g. electrically conductive contact) to be coupled to the at least one contact (e.g. electrically conductive contact) of the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface) disposed at least partially outside the boundary of the semiconductor chip, and the extension layer may include at least one through-via (e.g. through-encapsulant via (TEV), e.g. through-mold via (TMV)) electrically coupling the first portion of the redistribution layer with the second portion of the redistribution layer.
The semiconductor chip may include at least one contact (e.g. electrically conductive contact) disposed over the second side (e.g. front side) of the semiconductor chip and electrically coupled with the second portion of the redistribution layer.
The second side (e.g. front side) of the semiconductor chip may face away from the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface).
The second side (e.g. front side) of the semiconductor chip and the interface (e.g. standardized interface, e.g. standardized chip-to-chip-interface) may be disposed at opposite sides of the semiconductor device.
The extension layer may extend from at least one lateral side of the semiconductor chip.
The extension layer may extend from at least four sides of the semiconductor chip, for example from at least all lateral sides of the semiconductor chip.
A part of the extension layer may be disposed over the first side (e.g. back side) of the semiconductor chip.
A part of the extension layer may be disposed over the second side (e.g. front side) of the semiconductor chip.
The extension layer may at least partially encapsulate the semiconductor chip.
For example, the extension layer may laterally enclose the semiconductor chip and may be disposed over the back side and/or over the front side of the semiconductor chip.
The semiconductor chip may be a first semiconductor chip and the semiconductor device may further include a second semiconductor chip having the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface) and electrically coupled to the first semiconductor chip via the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface).
The second semiconductor chip may include or may be composed of any suitable semiconductor material, including compound semiconductors. For example, the second semiconductor chip may include silicon or may be a silicon chip.
The second semiconductor chip may be disposed over the redistribution layer, wherein one or more contacts (e.g. electrically conductive contacts) of the second semiconductor chip arranged in accordance with the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface) may be electrically coupled to one or more contacts (e.g. electrically conductive contacts) of the redistribution layer arranged in accordance with the interface (e.g. standardized interface, e.g. standardized chip-to-chip interface).
The second semiconductor chip may be a memory chip, for example a DRAM (dynamic random access memory) chip, alternatively any other type of (volatile or non-volatile) memory chip. The first semiconductor chip may be a logic chip (e.g. a CPU, or the like) and the second semiconductor chip may be a memory chip (e.g. a DRAM chip, or any other type of memory chip).
The semiconductor device may further include at least one additional semiconductor chip disposed over a side of the second semiconductor chip facing away from the first semiconductor chip, and electrically coupled to the second semiconductor chip.
The at least one additional semiconductor chip may be a memory chip (e.g. a DRAM chip, or any other type of memory chip).
The semiconductor device may be configured as a three-dimensional (3D) chip stack including the first semiconductor chip, which may, for example be a logic chip (e.g. a CPU, or the like), and a plurality of chips (e.g. memory chips, e.g. DRAM chips, or other types of memory chips) stacked one over the other, disposed over the redistribution layer and electrically coupled to the first semiconductor chip (e.g. logic chip) via the standardized chip-to-chip interface (e.g. logic-to-memory interface).
The semiconductor device may further include an interposer disposed over a side of the first semiconductor chip facing away from the second semiconductor chip, and electrically coupled to the first semiconductor chip.
The interposer may be disposed over the second side (e.g. front side) of the first semiconductor chip.
The interposer may include an electrically insulating material.
The interposer may include or be composed of a laminate material or laminate.
The interposer may include or be composed of a printed circuit board (PCB).
The interposer may include at least one interconnect level.
The interposer may include a plurality of interconnect levels.
The interposer may be a silicon interposer.
The interposer may be a glass interposer.
The semiconductor device may further include at least one electrical connector disposed between the interposer and the first semiconductor chip and electrically coupling the interposer to the first semiconductor chip.
The at least one electrical connector may include a plurality of solder bumps.
The at least one electrical connector may include a plurality of metal pillars (e.g. copper pillars).
The semiconductor device may further include a ball grid array disposed over a side of the interposer facing away from the first semiconductor chip.
In accordance with one or more aspects, a semiconductor device may include: a first semiconductor chip having at least one contact (e.g. electrically conductive contact) to be electrically coupled to a second semiconductor chip having an interface (e.g. chip-to-chip interface) with standardized geometric dimensions, wherein a lateral dimension of the first semiconductor chip along at least one direction is smaller than a lateral dimension of the interface (e.g. chip-to-chip interface) along the at least one direction; an extension layer extending laterally from at least one side of the first semiconductor chip along the at least one direction, wherein a combined lateral dimension of the first semiconductor chip and the extension layer along the at least one direction is greater than or equal to the lateral dimension of the interface (e.g. chip-to-chip interface) along the at least one direction; a redistribution layer disposed over at least one side of the extension layer and the first semiconductor chip, the redistribution layer electrically coupling the at least one contact (e.g. electrically conductive contact) of the first semiconductor chip to at least one contact (e.g. electrically conductive contact) of the interface (e.g. chip-to-chip interface) disposed at least partially outside a boundary of the first semiconductor chip.
The semiconductor device may further include a second semiconductor chip having the interface (e.g. chip-to-chip interface) with standardized geometric dimensions, wherein the second semiconductor chip is electrically coupled to the first semiconductor chip via the interface (e.g. chip-to-chip interface).
The interface (e.g. chip-to-chip interface) may include a plurality of contacts (e.g. electrically conductive contacts), wherein at least one contact (e.g. electrically conductive contact) of the plurality of contacts (e.g. electrically conductive contacts) is disposed at least partially outside a boundary of the first semiconductor chip.
The first semiconductor chip may be a logic chip (e.g. a CPU, or the like) and the second semiconductor chip may be a memory chip (e.g. a DRAM chip, or any other type of memory chip).
In accordance with one or more aspects, a semiconductor device may include: a first semiconductor chip having a first plurality of contacts (e.g. electrically conductive contacts); an extension layer extending from a lateral boundary of the first semiconductor chip; a redistribution layer disposed over the extension layer and the first semiconductor chip and having a second plurality of contacts (e.g. electrically conductive contacts) electrically coupled to the first plurality of contacts (e.g. electrically conductive contacts), wherein at least one contact (e.g. electrically conductive contact) of the second plurality of contacts (e.g. electrically conductive contacts) is disposed at least partially outside the lateral boundary of the first semiconductor chip, wherein the second plurality of contacts (e.g. electrically conductive contacts) is arranged in accordance with a predetermined interface standard (e.g. chip-to-chip interface standard).
The semiconductor device may further include: a second semiconductor chip having a third plurality of contacts (e.g. electrically conductive contacts) arranged in accordance with the predetermined interface standard (e.g. chip-to-chip interface standard), wherein the third plurality of contacts (e.g. electrically conductive contacts) is in contact with the second plurality of contacts (e.g. electrically conductive contacts).
The first semiconductor chip may be a logic chip and the second semiconductor chip may be a memory chip, wherein the predetermined interface standard (e.g. chip-to-chip interface standard) is a logic-memory interface standard.
The extension layer may include at least one through-via electrically coupling at least one contact (e.g. electrically conductive contact) of the first plurality of contacts (e.g. electrically conductive contacts) to at least one contact (e.g. electrically conductive contact) of the second plurality of contacts (e.g. electrically conductive contacts).
In accordance with one or more aspects, a semiconductor device may include: a first semiconductor chip to be electrically coupled to a second semiconductor chip via a standardized chip-to-chip interface, wherein at least a part of the standardized chip-to-chip interface extends laterally beyond a boundary of the first semiconductor chip; an extension layer extending laterally from the boundary of the first semiconductor chip; a redistribution layer disposed over at least one side of the extension layer and the first semiconductor chip, the redistribution layer being configured to electrically couple at least one electrically conductive contact of the first semiconductor chip to at least one electrically conductive contact of the standardized chip-to-chip interface disposed at least partially outside the boundary of the first semiconductor chip.
In accordance with one or more aspects, a semiconductor device may include: a first semiconductor chip having at least one electrically conductive contact to be electrically coupled to a second semiconductor chip having a chip-to-chip interface with standardized geometric dimensions, wherein a lateral dimension of the first semiconductor chip along at least one direction is smaller than a lateral dimension of the chip-to-chip interface along the at least one direction; an extension layer extending laterally from at least one side of the first semiconductor chip along the at least one direction, wherein a combined lateral dimension of the first semiconductor chip and the extension layer along the at least one direction is greater than or equal to the lateral dimension of the chip-to-chip interface along the at least one direction; a redistribution layer disposed over at least one side of the extension layer and the first semiconductor chip, the redistribution layer being configured to reroute the at least one electrically conductive contact of the first semiconductor chip to at least one electrically conductive contact of the chip-to-chip interface disposed at least partially outside a boundary of the first semiconductor chip.
In accordance with one or more aspects, a semiconductor device may include: a first semiconductor chip having a first plurality of electrically conductive contacts; an extension layer extending from a lateral boundary of the first semiconductor chip; a redistribution layer disposed over the extension layer and the first semiconductor chip and having a second plurality of electrically conductive contacts electrically coupled to the first plurality of electrically conductive contacts, wherein at least one electrically conductive contact of the second plurality of electrically conductive contacts is disposed at least partially outside the lateral boundary of the first semiconductor chip, wherein the second plurality of electrically conductive contacts is arranged in accordance with a predetermined chip-to-chip interface standard.
While the invention has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
