Semiconductor package

Description

BACKGROUND OF THE INVENTION

Example embodiments of the inventive concepts relate to a semiconductor device, and in particular, to a semiconductor package.

There is a growing trend to fabricate lightweight, small-sized, high speed, multifunctional, high performance, and low-cost electronic systems. In response to such a trend, multi-chip stacked package techniques and/or system in package techniques have been proposed. In a multi-chip stacked package or a system in package, one or more functions of a plurality of semiconductor devices may be performed in a single semiconductor package. The multi-chip stacked package or the system in package may have a thickness larger than that of a single chip package, but may have a similar size to the single chip package in terms of a planar surface area or “footprint”. Thus, the multi-chip stacked package or the system in package may be used in smaller (e.g., mobile) devices with high performance requirements such as, for example, mobile phones, notebook computers, memory cards, portable camcorders, and the like.

SUMMARY

Example embodiments of the inventive concepts provide a semiconductor package with improved electric characteristics.

Other example embodiments of the inventive concepts provide a semiconductor package that can be fabricated with low cost.

According to example embodiments of the inventive concepts, a semiconductor package may include a package substrate including an opening provided at a central region thereof and a circuit pattern provided adjacent to the opening, a first semiconductor chip provided on the package substrate to include a first integrated circuit, a first center pad, which may be disposed at a central region thereof exposed by the opening and may be electrically connected to the circuit pattern by a first wire, and first bonding pads, each of which may be disposed at the central region thereof to be spaced apart from the first center pad and be electrically connected to the first integrated circuit, a pair of second semiconductor chips mounted between the package substrate and the first semiconductor chip and spaced apart from each other to include a second integrated circuit and second bonding pads, the second bonding pads being provided adjacent to opposite edge portions thereof to correspond to the first bonding pads and be electrically connected to the second integrated circuit, and a connection element electrically connecting the first bonding pads with the second bonding pads. The first semiconductor chip may have a memory capacity that may be two times that of each of the second semiconductor chips, and a total memory capacity of the package may be 2ⁿtimes a memory capacity of the first semiconductor chip.

In example embodiments, the first center pad may be electrically connected to the first bonding pads via the first integrated circuit.

In example embodiments, the first semiconductor chip may have a first surface facing the package substrate and a second surface opposite the first surface, and the first center pad and the first bonding pads may be disposed on the first surface, and each of the second semiconductor chips may have a third surface facing the first surface of the first semiconductor chip and a fourth surface opposite the third surface, and the second bonding pads may be disposed on the third surface.

In example embodiments, the second semiconductor chips may further include second center pads disposed at central regions thereof and connected to the second integrated circuit, and the second center pads may be electrically connected to the second bonding pads via a second redistributed layer.

In example embodiments, the second integrated circuit may be electrically connected to the second bonding pads, without the second center pads provide at the central region of thereof.

In example embodiments, the semiconductor package may further include a pair of third semiconductor chips provided between the package substrate and the second semiconductor chips and spaced apart from each other to include a third integrated circuit and third bonding pads, the third bonding pads being provided at opposite edge portions thereof and being electrically connected to the third integrated circuit, and a pair of fourth semiconductor chips provided between the package substrate and the third semiconductor chips and spaced apart from each other to include a fourth integrated circuit and fourth bonding pads, the fourth bonding pads being provided at opposite edge portions thereof and being electrically connected to the fourth integrated circuit. The second bonding pads, the third bonding pads, and the fourth bonding pads may be connected to each other in a side connection manner or a wire connection manner.

In example embodiments, each of the third semiconductor chips may have a fifth surface facing the second semiconductor chips and a sixth surface opposite the fifth surface, and the third bonding pads may be disposed on the fifth surface, and each of the fourth semiconductor chips may have a seventh surface facing the sixth surface of the third semiconductor chip and an eighth surface opposite the seventh surface, and the fourth bonding pads may be disposed on the seventh surface.

In example embodiments, the connection element may include first bumpers disposed between the first semiconductor chip and the second semiconductor chips.

In example embodiments, the first semiconductor chip may have a first surface facing the package substrate and a second surface opposite the first surface, and the first center pad and the first bonding pads may be disposed on the first surface, each of the second semiconductor chips may have a third surface facing the first surface of the first semiconductor chip and a fourth surface opposite the third surface, and the second bonding pads may be disposed on the fourth surface.

In example embodiments, the connection element may include a second wire, the second semiconductor chips may be shifted toward the opening of the package substrate to expose the second bonding pad of the second semiconductor chips, and the second semiconductor chips expose the first bonding pads.

In example embodiments, each of the third semiconductor chips may have a fifth surface facing the second semiconductor chips and a sixth surface opposite the fifth surface, and the third bonding pads and the third integrated circuit may be disposed on the sixth surface, and each of the fourth semiconductor chips may have a seventh surface facing the sixth surface of the third semiconductor chip and an eighth surface opposite the seventh surface, and the fourth bonding pads and the fourth integrated circuit may be disposed on the eighth surface.

In example embodiments, the third semiconductor chips may be shifted toward the opening of the package substrate to expose the third bonding pad of the third semiconductor chips, the fourth semiconductor chips may be shifted toward the opening of the package substrate to expose the fourth bonding pad of the fourth semiconductor chips, the second and third bonding pads may be connected to each other by a third wire, and the third and fourth bonding pads may be connected to each other by a fourth wire.

According to example embodiments of the inventive concepts, a semiconductor package may include a package substrate with a circuit pattern, a first semiconductor chip provided on the package substrate to include a first integrated circuit and a through-silicon via, the first semiconductor chip including a first surface facing the package substrate and a second surface opposite the first surface, the through-silicon via being provided at a central region thereof and electrically connected to the circuit pattern, and a pair of second semiconductor chips disposed on the first semiconductor chip to be spaced apart from each other and include a second integrated circuit, each of the second semiconductor chips having a third surface facing the first semiconductor chip and a fourth surface opposite the third surface.

In example embodiments, the second semiconductor chips have a memory capacity that may be two times that of the first semiconductor chip, and a total memory capacity of the package may be 2ⁿtimes a memory capacity of the first semiconductor chip.

In example embodiments, the semiconductor package may further include a first bumper provided between the first semiconductor chip and the package substrate to connect the through-silicon via electrically to the circuit pattern.

In example embodiments, the first semiconductor chip may further include first bonding pads disposed on the second surface and connected to the through-silicon via, and the second semiconductor chips may further include second bonding pads disposed on the fourth surface and electrically connected to the second integrated circuit.

In example embodiments, the semiconductor package may further include a pair of third semiconductor chips provided on the second semiconductor chips and spaced apart from each other to include a third integrated circuit and third bonding pads, the third bonding pads being provided at opposite edge portions thereof and being electrically connected to the third integrated circuit, and a pair of fourth semiconductor chips provided on the third semiconductor chips and spaced apart from each other to include a fourth integrated circuit and fourth bonding pads, the fourth bonding pads being provided at opposite edge portions thereof and being electrically connected to the fourth integrated circuit.

In example embodiments, each of the third semiconductor chips may have a fifth surface facing the second semiconductor chips and a sixth surface opposite the fifth surface, and the third bonding pads may be disposed on the sixth surface, and each of the fourth semiconductor chips may have a seventh surface facing the sixth surface of the third semiconductor chip and an eighth surface opposite the seventh surface, and the fourth bonding pads may be disposed on the eighth surface.

In example embodiments, the second semiconductor chips further include connection pads on the third surface, and the semiconductor package may further include second bumpers provided between the first and second semiconductor chips to connect the connection pads electrically to the first bonding pad.

In example embodiments, the connection pad, the second bonding pads, the third bonding pads, and the fourth bonding pads may be connected to each other in a side connection manner.

In example embodiments, the third semiconductor chips may be shifted toward an edge of the package substrate to expose the second bonding pads of the second semiconductor chips, and the fourth semiconductor chips may be shifted toward the edge of the package substrate to expose the third bonding pads of the third semiconductor chips.

In example embodiments, the second semiconductor chips further include connection pads on the third surface, the semiconductor package may further include second bumpers that may be provided between the first semiconductor chip and the second semiconductor chips to connect the connection pads to the first bonding pad, and the connection pads, the second bonding pads, the third bonding pads, and the fourth bonding pads may be connected to each other in a side connection manner.

In example embodiments, the first bonding pad, the second bonding pads, the third bonding pads, and the fourth bonding pads may be connected to each other in a wire bonding manner.

In example embodiments, the first bonding pad may be provided on the first surface.

In example embodiments, the first semiconductor chip may further include first bonding pads provided on the first surface and connected to the through-silicon via, and the second semiconductor chips further include second bonding pads provided on the third surface and electrically connected to the second integrated circuit.

In example embodiments, the second bonding pads, the third bonding pads, and the fourth bonding pads may be connected to each other in a side connection manner.

In example embodiments, the third semiconductor chips may be shifted toward the central region of the package substrate to expose the third bonding pads, and the fourth semiconductor chips may be shifted toward the central region of the package substrate to expose the fourth bonding pads.

In example embodiments, the second bonding pads, the third bonding pads, and the fourth bonding pads may be connected to each other in a wire bonding manner.

In example embodiments, the semiconductor package may further include a second bumper disposed between the first and second semiconductor chips to connect the second bonding pads to the through-silicon via.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.

FIG. 1 is a schematic diagram illustrating a semiconductor package according to example embodiments of the inventive concepts.

FIG. 2A is a sectional view of a semiconductor package according to a first embodiment of the inventive concepts.

FIGS. 2B and 2C are enlarged views illustrating portions A and B of FIG. 2A, respectively.

FIG. 2D is a schematic plan view illustrating a bottom surface of a first semiconductor chip.

FIG. 2E is a schematic plan view illustrating top surfaces of second semiconductor chips.

FIG. 3A is a sectional view of a semiconductor package according to a second embodiment of the inventive concepts.

FIGS. 3B and 3C are enlarged views illustrating portions A and B of FIG. 3A, respectively.

FIG. 3D is a schematic plan view illustrating a bottom surface of a first semiconductor chip 110.

FIG. 3E is a schematic plan view illustrating top surfaces of second semiconductor chips 120.

FIG. 4A is a sectional view of a semiconductor package according to a third embodiment of the inventive concepts.

FIG. 4B is an enlarged view of a portion A of FIG. 4A.

FIG. 5 is a sectional view of a semiconductor package according to a fourth embodiment of the inventive concepts.

FIG. 6A is a sectional view of a semiconductor package according to a fifth embodiment of the inventive concepts.

FIGS. 6B and 6C are enlarged views illustrating portions A and B of FIG. 6A, respectively.

FIG. 7 is a sectional view of a semiconductor package according to a sixth embodiment of the inventive concepts.

FIG. 8A is a sectional view of a semiconductor package according to a seventh embodiment of the inventive concepts.

FIG. 8B is an enlarged view of a portion A of FIG. 8A.

FIG. 9 is a sectional view of a semiconductor package according to a modification of the seventh embodiment of the inventive concepts.

FIG. 10 is a sectional view of a semiconductor package according to an eighth embodiment of the inventive concepts.

FIG. 11 is a sectional view of a semiconductor package according to a ninth embodiment of the inventive concepts.

FIG. 12 is a sectional view of a semiconductor package according to a tenth embodiment of the inventive concepts.

FIG. 13A is a sectional view of a semiconductor package according to an eleventh embodiment of the inventive concepts.

FIGS. 13B and 13C are enlarged views illustrating portions A and B of FIG. 13A, respectively.

FIG. 14 is a sectional view of a semiconductor package according to a twelfth embodiment of the inventive concepts.

FIG. 15 is a sectional view of a semiconductor package according to a thirteenth embodiment of the inventive concepts.

FIG. 16 is a block diagram illustrating an electronic system according to example embodiments of the inventive concepts.

It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.

DETAILED DESCRIPTION

Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments of the inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of example embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus redundant descriptions may be omitted.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements or layers should be interpreted using the same principles discussed above (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on”). As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concepts. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Example embodiments of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing variances. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the inventive concepts.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the inventive concepts belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1 is a schematic diagram illustrating a semiconductor package P, according to example embodiments of the inventive concepts, and an external controller C. The semiconductor package P may include a master chip 10 and at least one slave chip 20. The master chip 10 may be configured to receive control signals (e.g., address and command), voltage signals, and data from an external controller C, send them to the slave chip 20, and control the one or more slave chips 20.

A semiconductor package 1, according to a first embodiment of the inventive concepts, will be described with reference to FIGS. 2A through 2E. FIG. 2A is a schematic cross-sectional view of the semiconductor package 1 according to a first embodiment of the inventive concepts. FIGS. 2B and 2C are enlarged views of portions A and B, respectively, of the semiconductor package 1 of FIG. 2A. FIG. 2D is a schematic plan view illustrating a bottom surface of a first semiconductor chip 110, and FIG. 2E is a schematic plan view illustrating top surfaces of second semiconductor chips 120.

Referring to FIGS. 2A through 2E, the semiconductor package 1 may include a package substrate 100, a first semiconductor chip 110 on the package substrate 100, and a pair of second semiconductor chips 120 spaced apart from each other and mounted between the package substrate 100 and the first semiconductor chip 110.

The package substrate 100 may be a printed circuit board. In example embodiments, an opening 101 may be formed through a center of the package substrate 100. The package substrate 100 may include circuit patterns 102 provided on opposite sides of and adjacent to the opening 101. The circuit patterns 102 may be provided on a bottom surface of the package substrate 100 and be electrically connected to a respective external pad 104. To connect the semiconductor package 1 electrically to an external device, at least one external terminal 108 (e.g., a solder bump or a solder ball) may be provided on the external pad 104.

The first semiconductor chip 110 may have a first surface 110a and a second surface 110b opposite the first surface. In example embodiments, the first semiconductor chip 110 may be provided in such a way that the first surface 110a faces the package substrate 100. The first semiconductor chip 110 may include a pair of cell regions 112 and a central region 111 interposed between the cell regions 112. The first semiconductor chip 110 may include a first integrated circuit IC1, a first center pad 114, and first bonding pads 115.

As shown in FIGS. 2B and 2D, the first integrated circuit IC1 may be formed in the first semiconductor chip 110 adjacent to the first surface 110a. The first center pad 114 and the first bonding pads 115 may be disposed on the first surface 110a of the central region 111. The first center pad 114 may be exposed by the opening 101. The first bonding pads 115 may be provided spaced apart from the first center pad 114. The first bonding pads 115 may be electrically connected to the first integrated circuit IC1 via a first contact 117 and a first internal pad 118.

In example embodiments, the first bonding pads 115 may include a pair of first bonding pads 115 provided on opposite sides of each first center pad 114. The pair of the first bonding pads 115 may be connected to each other via a first redistributed line 116. The first center pad 114 may be separated from the first bonding pads 115 and the first redistributed line 116. The first center pad 114 and the first bonding pads 115 may be electrically connected to each other through the first integrated circuit IC1. A first lower insulating layer 119 may be provided on the first surface 110a of the first semiconductor chip 110 to cover the first surface 110a while exposing the first center pad 114 and the first bonding pads 115.

Referring back to FIG. 2A, the second semiconductor chips 120 may be attached to the package substrate 100 by an adhesive layer 210. The adhesive layer 210 may be an insulating film or tape, which may be formed of epoxy or silicone. The second semiconductor chips 120 may include edge portions 120e that are disposed on opposite sides of and adjacent to the opening 101 of the package substrate 100 to face each other. The second semiconductor chips 120 may have a third surface 120a facing the first surface 110a of the first semiconductor chip 110 and a fourth surface 120b opposite the third surface 120a.

As shown in FIGS. 2C and 2E, the second semiconductor chip 120 may include a second integrated circuit IC2, second center pads 124, and second bonding pads 125. The second integrated circuit IC2 may be formed in the second semiconductor chip 120 adjacent to the third surface 120a. The second center pads 124 and the second bonding pads 125 may be disposed on the third surface 120a of the second semiconductor chip 120. The second center pads 124 may be provided in a central region 121 of the second semiconductor chip 120. A pair of cell regions 122 may be provided on opposite sides of the second center pads 124. The second bonding pads 125 may be provided adjacent to edge portions 120e of the second semiconductor chips 120 that face each other across the opening 101. The second bonding pads 125 may be provided to correspond to the first bonding pads 115 and be electrically connected to the second center pads 124 via a second redistributed line 126. The second bonding pads 125 may be electrically connected to the second integrated circuit IC2 via the second center pads 124. A second insulating layer 129 may be provided on the third surface 120a of the second semiconductor chip 120 to cover the third surface 120a and expose the second bonding pads 125.

Referring back to FIG. 2A, the semiconductor package 1 may further include first bumpers 22 electrically connecting the first bonding pads 115 with the second bonding pads 125, and dummy bumpers 24 provided spaced apart from the first bumpers 22 to support the first and second semiconductor chips 110 and 120. The first bumpers 22 may be arranged below the first semiconductor chip 110 and adjacent opposite sides of the opening 101, while the dummy bumpers 24 may be provided below the first semiconductor chip 110 and away from the opening 101.

At least one main bonding wire 40 may be provided in the opening 101 to electrically connect the first center pad 114 of the first semiconductor chip 110 with the circuit pattern 102 of the package substrate 100.

A molding layer 200 may be formed to cover the first and second semiconductor chips 110 and 120. The molding layer 200 may include a protruding portion 201, which protrudes from the opening 101 away from a bottom of the package substrate 100.

At least one of the first and second semiconductor chips 110 and 120 may be a memory chip, such as DRAM or FLASH memory. The first semiconductor chip 110 may be a master chip, and the first integrated circuit IC1 may include memory cells for storing data and a control circuit and/or a power circuit for controlling operations of the memory cells. One or more of the second semiconductor chips 120 may be a slave chip, and the second integrated circuit IC2 may include memory cells for storing data. The second semiconductor chips 120 may be configured without a control circuit and/or a power circuit.

The first semiconductor chip 110 may be configured to communicate with an external controller C (see FIG. 1) through the main bonding wire 40 and to control the second semiconductor chips 120 through the first bumpers 22. Control signals (e.g., address and command signals), voltage signals, and data to be transmitted from the controller C may be provided to the first semiconductor chip 110 through the main bonding wire 40, and data to be read out from the memory cells of the first or second semiconductor chips 110 or 120 may also be transmitted to the controller C through the main bonding wire 40.

Since the second semiconductor chips 120 communicate with the external controller C through the main bonding wire 40 and the first semiconductor chip 110, it is possible to reduce a parasitic capacitance in the communication. Further, since a bonding wire, rather than a through-silicon via, is used to connect the first and second semiconductor chips 110 and 120 to the outside, it is possible to reduce fabrication costs of the semiconductor package.

In the case where the first and second semiconductor chips 110 and 120 are memory chips, a memory capacity of the first semiconductor chip 110 may, for example, be twice that of each of the second semiconductor chips 120. A total memory capacity of the semiconductor package 1 may be 2ⁿtimes that of the first semiconductor chip 110, where n is an integer.

A semiconductor package 2 according to a second embodiment of the inventive concepts will now be described with reference to FIGS. 3A through 3E. FIG. 3A is a schematic cross-sectional view of a semiconductor package 2 according to a second embodiment of the inventive concepts. FIGS. 3B and 3C are enlarged views illustrating portions A and B, respectively, of the semiconductor package 2 of FIG. 3A. FIG. 3D is a schematic plan view illustrating a bottom surface of a first semiconductor chip 110, and FIG. 3E is a schematic plan view illustrating top surfaces of second semiconductor chips 120. In the description that follows, discussion of features identical to those of FIGS. 2A through 2E will be minimized in order to avoid redundancy.

Referring to FIGS. 3A through 3E, in the semiconductor package 2, the second integrated circuit IC2 of the second semiconductor chips 120 may be electrically connected to the second bonding pads 125, without the second center pads 124 of the previous embodiment. In other words, the semiconductor package 2 of this embodiment may differ from the semiconductor package 1 of the previous embodiment in that the second integrated circuit IC2 may be directly connected to edge pads (e.g., the second bonding pads 125), which may be provided adjacent to edge portions 120e of the second semiconductor chips 120.

A semiconductor package 3 according to a third embodiment of the inventive concepts will now be described with reference to FIGS. 4A and 4B. FIG. 4A provides a schematic cross-sectional view of a semiconductor package 3 according to a third embodiment, and FIG. 4B is an enlarged view of portion A of FIG. 4A. Discussion of features identical to those of FIGS. 2A through 2E will be minimized in order to avoid redundancy.

Referring to FIGS. 4A and 4B, the semiconductor package 3 may include a package substrate 100, a first semiconductor chip 110 on the package substrate 100, and a pair of second semiconductor chips 120 spaced apart from each other across the opening 101 and disposed between the package substrate 100 and the first semiconductor chip 110. In addition, however, a pair of third semiconductor chips 130 may be spaced apart from each other across the opening 101 and disposed between the package substrate 100 and the second semiconductor chips 120, and a pair of fourth semiconductor chips 140 may be spaced apart from each other across the opening 101 and disposed between the package substrate 100 and the third semiconductor chips 130.

Each of the third semiconductor chips 130 may include a fifth surface 130a facing the second semiconductor chip 120 and a sixth surface 130b opposite the fifth surface. One or more of the third semiconductor chips 130 may include a third integrated circuit, third center pads 134 and third bonding pads 135. A third insulating layer 139 may be formed on the sixth surface 130b of the third semiconductor chips 130.

Similar to the second integrated circuit IC2 shown in FIG. 2C, the third integrated circuit may be provided in the third semiconductor chips 130 adjacent to the fifth surface 130a. The third center pads 134 and the third bonding pads 135 may be provided on the fifth surface 130a of the third semiconductor chip 130. The third center pads 134 may be provided in a central region of the third semiconductor chip 130. The third bonding pads 135 may be disposed adjacent to edge portions 130e of the third semiconductor chips 130. The third bonding pads 135 may be provided to correspond to the second bonding pads 125 and be electrically connected to the third center pads 134 via a third redistributed line 136. Accordingly, the third bonding pads 135 may be electrically connected to the third integrated circuit via the third center pads 134.

Each of the fourth semiconductor chips 140 may include a seventh surface 140a facing the corresponding third semiconductor chip 130 and an eighth surface 140b opposite the seventh surface 140a. One or more of the fourth semiconductor chips 140 may include a fourth integrated circuit, fourth center pads 144, and fourth bonding pads 145.

Similar to the second integrated circuit IC2 shown in FIG. 2C, the fourth integrated circuit may be provided in the fourth semiconductor chip 140 adjacent to the seventh surface 140a. The fourth center pads 144 and the fourth bonding pads 145 may be disposed on the seventh surface 140a of the fourth semiconductor chip 140. The fourth center pads 144 may be provided in a central region of the fourth semiconductor chip 140. The fourth bonding pads 145 may be disposed adjacent to edge portions 140e of the fourth semiconductor chips 140. The fourth bonding pads 145 may be provided to correspond to the third bonding pads 135 and be electrically connected to the fourth center pads 144 via a fourth redistributed line 146. Accordingly, the fourth bonding pads 145 may be electrically connected to the fourth integrated circuit via the fourth center pads 144.

The second semiconductor chips 120, the third semiconductor chips 130, the fourth semiconductor chips 140, and the package substrate 100 may be attached to each other by adhesive layers 210.

The second bonding pads 125, the third bonding pads 135, and the fourth bonding pads 145 may be connected to each other in a side connection manner. For example, as shown in FIG. 4B, a sidewall insulating layer 32 may be formed on a sidewall of the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140, and a metal pattern 30 may be formed on the sidewall insulating layer 32. The metal pattern 30 extend laterally and be electrically connected to the second 125, third 135 and fourth bonding pads 145. For example, the metal pattern 30 may extend laterally between the second, third, and fourth semiconductor chips 120, 130, and 140. The metal pattern 30 may, for example, include copper (Cu).

A semiconductor package 4 according to a fourth embodiment of the inventive concepts will now be described with reference to FIG. 5. FIG. 5 is a schematic cross-sectional view of a semiconductor package 4 according to a fourth embodiment. In the description that follows, discussion of features identical to those of FIG. 4A will be minimized in order to avoid redundancy.

Referring to FIG. 5, unlike the previous embodiment, the third semiconductor chips 130 of this embodiment may be shifted toward an outer edge of the package substrate 100 to expose the fourth bonding pads 145 of the fourth semiconductor chips 140. Similarly, the second semiconductor chips 120 may be shifted toward the outer edge of the package substrate 100 to expose the third bonding pads 135 of the third semiconductor chips 130.

A first subwire 42 may be provided in the opening 101 to electrically connect the second bonding pads 125 with the third bonding pads 135. A second subwire 44 may be provided in the opening 101 to electrically connect the third bonding pads 135 with the fourth bonding pads 145.

A semiconductor package 5 according to a fifth embodiment of the inventive concepts will now be described with reference to FIGS. 6A through 6C. FIG. 6A is a schematic cross-sectional view of a semiconductor package 5 according to a fifth embodiment of the inventive concepts, and FIGS. 6B and 6C are enlarged views of portions A and B, respectively, of FIG. 6A, respectively. In the description that follows, discussion of features identical to those of FIGS. 2A through 2E will be minimized in order to avoid redundancy.

Referring to FIGS. 6A through 6C, unlike the first embodiment, second integrated circuits IC2 of second semiconductor chips 120 in this embodiment may be formed in the second semiconductor chips 120 adjacent to the fourth surfaces 120b. The second center pads 124 and the second bonding pads 125 may be provided on the fourth surface 120b of the second semiconductor chip 120. The second center pads 124 may be provided in the central region of the second semiconductor chip 120. The second bonding pads 125 may be disposed adjacent to edge portions 120e of the second semiconductor chips 120. The second bonding pads 125 may be provided to correspond to the first bonding pads 115 and be electrically connected to the second center pads 124 via a second redistributed line 126. The second center pads 124 may be electrically connected to the second integrated circuit IC2 via a second contact 127. The second insulating layer 129 may be provided on the fourth surface 120b of the second semiconductor chip 120 to cover the fourth surface 120b and expose the second bonding pads 125.

The package substrate 100 and the first and second semiconductor chips 110 and 120 may be attached to each other by adhesive layers 210. The adhesive layers 210 may be an insulating film or tape, which may be formed of epoxy or silicone.

The second semiconductor chips 120 may be shifted toward the opening 101 to expose the second bonding pads 125 of second semiconductor chips. The second semiconductor chips 120 may be arranged to expose the first bonding pads 115. A first subwire 42 may be provided in the opening 101 to electrically connect the first bonding pads 115 with the second bonding pads 125.

A semiconductor package 6 according to a sixth embodiment of the inventive concepts will now be described with reference to FIG. 7. FIG. 7 is a schematic cross-sectional view of a semiconductor package 6 according to a sixth embodiment. In the description that follows, discussion of features identical to those of FIGS. 6A through 6C will be minimized in order to avoid redundancy.

Referring to FIG. 7, a semiconductor package 6 may include a pair of third semiconductor chips 130 spaced apart from each other and disposed between the package substrate 100 and the second semiconductor chips 120, along with a pair of fourth semiconductor chips 140 spaced apart from each other and disposed between the package substrate 100 and the third semiconductor chips 130.

One or more of the third semiconductor chips 130 may include a third integrated circuit, a third center pad 134, and a third bonding pad 135. Each of the third semiconductor chips 130 may include a fifth surface 130a facing the second semiconductor chips 120 and a sixth surface 130b opposite the fifth surface 130a.

Similar to the second integrated circuit IC2 shown in FIG. 6C, the third integrated circuit may be provided in the third semiconductor chip 130 adjacent to the sixth surface 130b. The third center pad 134 and the third bonding pad 135 may be provided on the sixth surface 130b of the third semiconductor chip 130. The third center pads 134 may be provided in the central region of the corresponding third semiconductor chip 130. The third bonding pads 135 may be disposed adjacent to edge portions 130e of the third semiconductor chips 130. The third bonding pads 135 may be provided to correspond to the second bonding pads 125 and be electrically connected to the third center pads 134 via a third redistributed line 136. Accordingly, the third bonding pads 135 may be electrically connected to the third integrated circuit via the third center pads 134.

One or more of the fourth semiconductor chips 140 may include a fourth integrated circuit, a third center pad 144, and a fourth bonding pad 145. Each of the fourth semiconductor chips 140 may include a seventh surface 140a facing the third semiconductor chips 130 and an eighth surface 140b opposite the seventh surface 140a.

Similar to the second integrated circuit IC2 shown in FIG. 6C, the fourth integrated circuit may be provided in the fourth semiconductor chip 140 adjacent to the eighth surface 140b. The fourth center pad 144 and the fourth bonding pad 145 may be provided on the eighth surface 140b of the fourth semiconductor chip 140. The fourth center pad 144 may be provided in a central region of the fourth semiconductor chip 140. The fourth bonding pads 145 may be disposed adjacent to edge portions 140e of the fourth semiconductor chips 140. The fourth bonding pads 145 may be provided to correspond to the third bonding pads 135 and be electrically connected to the fourth center pads 144 via a fourth redistributed line 146. Accordingly, the fourth bonding pads 145 may be electrically connected to the fourth integrated circuits via the fourth center pads 144.

The third semiconductor chips 130 may be shifted toward the opening 101 to expose the third bonding pads 135 of the third semiconductor chips. The fourth semiconductor chips 140 may be shifted toward the opening 101 to expose the fourth bonding pads 145 of the fourth semiconductor chips.

A second subwire 44 may be provided in the opening 101 to electrically connect the second bonding pad 125 with a corresponding third bonding pad 135. A third subwire 46 may be provided in the opening 101 to electrically connect a third bonding pad 135 with a corresponding fourth bonding pad 145.

A semiconductor package 7A according to a seventh embodiment of the inventive concepts will now be described with reference to FIGS. 8A and 8B. FIG. 8A is a schematic cross-sectional view of a semiconductor package 7A according to a seventh embodiment of the inventive concepts, and FIG. 8B is an enlarged view of a portion A of FIG. 8A.

Referring to FIGS. 8A and 8B, the semiconductor package 7A may include a package substrate 100 with a circuit pattern, a first semiconductor chip 110 on the package substrate, and a pair of second semiconductor chips 120 provided spaced apart from each other on the first semiconductor chip 110.

The package substrate 100 may be a printed circuit board. The package substrate 100 may include the circuit pattern 102. The circuit pattern 102 may be electrically connected to an external pad 104, which may be disposed on the bottom surface of the package substrate 100. To electrically connect the semiconductor package 6 to an external device, at least one external terminal 108 (e.g., a solder bump or a solder ball) may be provided on the external pad 104.

The first semiconductor chip 110 may include a first surface 110a facing the package substrate 100 and a second surface 110b opposite the first surface. Each first semiconductor chip 110 may include a first integrated circuit IC1, through-silicon vias TSV, and a first bonding pad 115. The first integrated circuit IC1 may be formed in the first semiconductor chip 110 adjacent to the second surface 110b.

The through-silicon vias TSV may be provided in the central region of the first semiconductor chip 110. The through-silicon vias TSV may be formed to penetrate the first semiconductor chip 110 or a substrate thereof. The first semiconductor chip 110 may include a lower pad 111a and an upper pad 111b that are provided on the first and second surfaces 110a and 110b, respectively, and are connected to each other by the through-silicon vias TSV.

The first bonding pads 115 may be provided in a central region of the first semiconductor chip 110, but spaced apart from the through-silicon vias TSV. In example embodiments, the first bonding pads 115 may be provided on the second surface 110b of the first semiconductor chip 110. The first bonding pads 115 may be electrically connected to the first integrated circuit IC1 via the first contact 117 and the first internal pad 118. In example embodiments, a pair of first bonding pads 115 may be provided with the through-silicon vias TSV interposed therebetween. The first bonding pads 115 may be electrically connected to the through-silicon via TSV via the first redistributed line 116. The first insulating layer 119 may be provided on the second surface 110b of the first semiconductor chip 110 to expose the first bonding pads 115.

First bumpers 22 may be provided between the first semiconductor chip 110 and the package substrate 100 to electrically connect the through-silicon via TSV to the circuit pattern 102. The semiconductor package 6 may further include first dummy bumpers 24 that are spaced apart from the first bumpers 22 to support the first semiconductor chip 110 and the package substrate 100.

A pair of second semiconductor chips 120 may be provided spaced apart from each other to expose the central region of the first semiconductor chip 110. Opposite edge portions 120e of the second semiconductor chips 120 may be disposed adjacent to the central region of the first semiconductor chip 110. Each of the second semiconductor chips 120 may include a third surface 120a facing the first semiconductor chip 110 and a fourth surface 120b opposite the third surface. Each second semiconductor chip 120 may include a second integrated circuit, a second center pad 124, and a second bonding pad 125.

Each second integrated circuit may be formed in a corresponding second semiconductor chip 120 adjacent to the fourth surface 120b, as shown in FIG. 2C. The second center pads 124 may be disposed in the central region of the respective second semiconductor chip 120. The second bonding pads 125 may be disposed adjacent to edge portions 120e of the second semiconductor chips 120. The second center pads 124 and the second bonding pads 125 may be disposed on the fourth surfaces 120b of the second semiconductor chips 120. The second bonding pads 125 may be electrically connected to the second center pads 124 via the second redistributed lines 126. The second center pads 124 may be electrically connected to the second integrated circuits IC2. Accordingly, the second bonding pads 125 may be electrically connected to the second integrated circuits IC2 via the second center pads 124.

Connection pads 127 may be provided on the third surfaces 120a of the second semiconductor chips 120. The connection pads 127 may be provided to correspond to the second bonding pads 125. A second insulating layer 129 may be provided on the third surface 120a of the second semiconductor chip 120 to cover the third surface and expose the connection pad 127.

The second bonding pads 125 and the connection pads 127 may be connected to each other in a side connection manner. For example, as illustrated in FIG. 8B, a sidewall insulating layer 32 may be formed on a sidewall of each second semiconductor chip 120, and a metal pattern 30 may be formed on the sidewall insulating layer 32. The metal pattern 30 may extend toward the third surface 120a and the fourth surface 120b of the second semiconductor chip 120 and be electrically connected to the second bonding pad 125 and the connection pad 127. The metal pattern 30 may, for example, include copper (Cu).

Second bumpers 26 may be provided between the first semiconductor chip 110 and the second semiconductor chips 120 to connect the connection pads 127 with the first bonding pads 115. The semiconductor package 6 may further include second dummy bumpers 28 that are provided spaced apart from the second bumpers 26 to support the first semiconductor chip 110 and the second semiconductor chips 120.

A semiconductor package 7B, according to a modification of the seventh embodiment of the inventive concepts, will now be described with reference to FIG. 9. Discussion of features identical to those of FIGS. 8A and 8B will be minimized in order to avoid redundancy.

Referring to FIG. 9, unlike the semiconductor package 7A, the semiconductor package 7B may be configured to include first bonding pads 115 electrically connected to the through-silicon via TSV by a bonding wire 40, rather than by the first redistributed line 116.

A semiconductor package 8, according to an eighth embodiment of the inventive concepts, will now be described with reference to FIG. 10. Discussion of features identical to those of FIGS. 8A and 8B will again be minimized in order to avoid redundancy.

Referring to FIG. 10, a semiconductor package 8 may include a package substrate 100, a first semiconductor chip 110 arranged on the package substrate 100, a pair of second semiconductor chips 120 spaced apart from each other and disposed between the package substrate 100 and the first semiconductor chip 110, a pair of third semiconductor chips 130 spaced apart from each other and disposed on the second semiconductor chips 120, and a pair of fourth semiconductor chips 140 spaced apart from each other and disposed on the third semiconductor chips 130.

Similar to the second integrated circuit IC2 shown in FIG. 2C, the third integrated circuit may be provided in the third semiconductor chips 130 adjacent to the sixth surface 130b. The third center pads 134 and the third bonding pads 135 may be provided on the sixth surfaces 130b of the third semiconductor chips 130. The third center pads 134 may be provided in a central region of the third semiconductor chips 130. The third bonding pads 135 may be disposed adjacent to edge portions 130e of the third semiconductor chips 130. The third bonding pads 135 may be provided to correspond to the second bonding pads 125 and be electrically connected to the third center pads 134 via the third redistributed lines 136. Accordingly, the third bonding pads 135 may be electrically connected to the third integrated circuits via the third center pads 134.

One or more of the fourth semiconductor chips 140 may include a fourth integrated circuit, a fourth center pad 144, and a fourth bonding pad 145. Each of the fourth semiconductor chips 140 may include a seventh surface 140a facing a corresponding one of the third semiconductor chips 130 and an eighth surface 140b opposite the seventh surface 140a.

Similar to the second integrated circuit IC2 shown in FIG. 2C, the fourth integrated circuit may be provided in the fourth semiconductor chip 140 adjacent to the eighth surface 140b. The fourth center pads 144 and the fourth bonding pads 145 may be provided on the eighth surfaces 140b of the fourth semiconductor chips 140. The fourth center pads 144 may be provided in central regions of the fourth semiconductor chips 140. The fourth bonding pads 145 may be disposed adjacent to edge portions 140e of the fourth semiconductor chips 140. The fourth bonding pads 145 may be provided to correspond to the third bonding pads 135 and be electrically connected to the fourth center pads 144 via the fourth redistributed lines 146. Accordingly, the fourth bonding pads 145 may be electrically connected to the fourth integrated circuits via the fourth center pads 144.

The second semiconductor chips 120, the third semiconductor chips 130, and the fourth semiconductor chips 140 may be attached to each other by the adhesive layers 210.

The connection pads 127, the second bonding pads 125, the third bonding pads 135, and the fourth bonding pads 145 may be connected to each other in a side connection manner. For example, similar to that shown in FIG. 8B, a sidewall insulating layer 32 may be formed on sidewalls of the second, third, and fourth semiconductor chips 120, 130, and 140, and a metal pattern 30 may be formed on the sidewall insulating layer 32. The metal pattern 30 may be connected to the connection pads 127, the second bonding pads 125, the third bonding pads 135, and the fourth bonding pads 145. The metal pattern 30 may, for example, include copper (Cu).

A semiconductor package 9 according to a ninth embodiment of the inventive concepts will be described with reference to FIG. 11. In the description that follows, discussion of features identical to those of FIG. 10 will be minimized in order to avoid redundancy.

Referring to FIG. 11, unlike the embodiment of FIG. 10, the third semiconductor chips 130 may be shifted toward an outer edge of the package substrate 100, as compared to the second semiconductor chips 120, to expose the second bonding pads 125 of the second semiconductor chips 120. Similarly, the fourth semiconductor chips 140 may be shifted toward the outer edge of the package substrate 100 to expose the third bonding pads 135 of the third semiconductor chips 130.

A semiconductor package 10 according to a tenth embodiment of the inventive concepts will now be described with reference to FIG. 12. Discussion of features identical to those of FIG. 11 will be minimized in order to avoid redundancy.

Referring to FIG. 12, unlike the embodiment of FIG. 11, the second semiconductor chips 120 may be attached to the first semiconductor package 110 by an adhesive layer 210. The third semiconductor chips 130 may again be shifted toward the outer edge of the package substrate 100 to expose the second bonding pads 125 of the second semiconductor chips 120, and the fourth semiconductor chips 140 may be shifted toward the outer edge of the package substrate 100 to expose the third bonding pads 135 of the third semiconductor chips 130.

The first and second bonding pads 115 and 125, respectively, may be electrically connected to each other via first subwires 42, the second and third bonding pads 125 and 135, respectively, may be electrically connected to each other via second subwires 44, and the third and fourth bonding pads 135 and 145, respectively, may be connected to each other via third subwires 46.

In addition, the seventh, eighth, and ninth embodiments described above may further be modified in such a way that the first bonding pads 115 are connected to the through-silicon via TSV by a main bonding wire 40, rather than by the first redistributed line, as described with reference to FIG. 9.

A semiconductor package 11 according to an eleventh embodiment of the inventive concepts will now be described with reference to FIGS. 13A through 13C. FIG. 13A is a schematic cross-sectional view of a semiconductor package 11 according to an eleventh embodiment of the inventive concepts, and FIGS. 13B and 13C are enlarged views illustrating portions A and B, respectively, of FIG. 13A.

Referring to FIGS. 13A through 13C, the semiconductor package 11 may include a package substrate 100 with a circuit pattern 102, a first semiconductor chip 110 provided on the package substrate, and a pair of second semiconductor chips 120 provided on the first semiconductor chip and spaced apart from each other.

The package substrate 100 may be a printed circuit board. The package substrate 100 may include the circuit pattern 102. The circuit pattern 102 may be electrically connected to an external pad 104, which may be provided on a bottom surface 100a of the package substrate 100. To electrically connect the semiconductor package 6 to an external device, at least one external terminal 108 (e.g., a solder bump or a solder ball) may be provided on the external pad 104.

The first semiconductor chip 110 may include a first surface 110a facing the package substrate 100 and a second surface 110b opposite the first surface 110a. The first semiconductor chip 110 may include a first integrated circuit IC1, through-silicon vias TSV, and a first bonding pad 115. The first integrated circuit IC1 may be formed in the first semiconductor chip 110 adjacent to the first surface 110a.

The through-silicon vias TSV may be disposed in a central region of the first semiconductor chip 110. The through-silicon vias TSV may be formed to penetrate the first semiconductor chip 110 or a substrate thereof. The first semiconductor chip 110 may include a lower pad 111a and an upper pad 111b, which are provided on the first and second surfaces 110a and 110b, respectively, and are connected to each other by the through-silicon vias TSV.

The first bonding pads 115 may be provided in the central region of the first semiconductor chip 110 but spaced apart from the through-silicon vias TSV. The first bonding pads 115 may be disposed on the first surface 110a of the first semiconductor chip 110. Each first bonding pad 115 may be electrically connected to the first integrated circuit IC1 via a first contact 117 and a first internal pad 118. The first bonding pads 115 may be disposed adjacent to the through-silicon vias TSV. Each first bonding pad 115 may be electrically connected to a corresponding one of the through-silicon vias TSV via a first redistributed line 116.

First bumpers 22 may be provided between the first semiconductor chip 110 and the package substrate 100 to electrically connect the first bonding pads 115 to the circuit pattern 102. First dummy bumpers 24 may additionally be provided between the first semiconductor chip 110 and the package substrate 100 and spaced apart from the first bumpers 22.

A first insulating layer 119 may be provided on the first surface 110a of the first semiconductor chip 110 to cover the first surface 110a and expose the first bonding pads 115.

A pair of second semiconductor chips 120 may be provided spaced apart from each other to expose the central region of the first semiconductor chip 110. Opposite edge portions 120e of the second semiconductor chips 120 may be disposed adjacent to the central region of the first semiconductor chip 110. Each of the second semiconductor chips 120 may include a third surface 120a facing the first semiconductor chip 110 and a fourth surface 120b opposite the third surface 120a. Each second semiconductor chip 120 may include a second integrated circuit IC2, a second center pad 124, and a second bonding pad 125.

The second integrated circuits IC2 may be formed in the second semiconductor chips 120 adjacent to the third surfaces 120a. The second center pads 124 may be provided in the central regions of the second semiconductor chips 120.

The second bonding pads 125 may be disposed adjacent to edge portions 120e of the second semiconductor chips 120. The second center pads 124 and the second bonding pads 125 may be provided on the third surfaces 120a of the second semiconductor chips 120. The second bonding pads 125 may be electrically connected to the second center pads 124 via second redistributed lines 126. The second center pads 124 may be electrically connected to the second integrated circuits IC2 via second contacts 127. Second insulating layers 129 may be provided on the third surfaces 120a of the second semiconductor chips 120 to cover the third surfaces 120a and expose the second bonding pads 125.

Second bumpers 26 may be provided between the first semiconductor chip 110 and the second semiconductor chips 120 to connect the second bonding pads 125 to the upper pad 111b. Second dummy bumpers 28 may additionally be provided between the first semiconductor chip 110 and the second semiconductor chips 120, spaced apart from the second bumpers 26.

A semiconductor package 12 according to a twelfth embodiment of the inventive concepts will now be described with reference to FIG. 14. Discussion of features identical to those of FIGS. 13A through 13C will be minimized to avoid redundancy.

Referring to FIG. 14, a semiconductor package 12 according to this embodiment may include a package substrate 100, a first semiconductor chip 110 on the package substrate 100, a pair of second semiconductor chips 120 spaced apart from each other and disposed between the package substrate 100 and the first semiconductor chip 110. In addition, the semiconductor package 12 may include a pair of third semiconductor chips 130 spaced apart from each other and disposed on the second semiconductor chips 120, and a pair of fourth semiconductor chips 140 spaced apart from each other and disposed on the third semiconductor chips 130.

One or more of the third semiconductor chips 130 may include a third integrated circuit, a third center pad 134, and a third bonding pad 135. The third bonding pads 135 may be electrically connected to the third integrated circuits. The third semiconductor chips 130 may each include a fifth surface 130a facing a corresponding second semiconductor chip 120 and a sixth surface 130b opposite the fifth surface 130a.

Similar to the second integrated circuit IC2 shown in FIG. 13C, the third integrated circuit may be provided in the third semiconductor chip 130 adjacent to the fifth surface 130a. The third center pads 134 and the third bonding pads 135 may be provided on the fifth surfaces 130a of the third semiconductor chips 130. The third center pads 134 may be provided in central regions of the third semiconductor chips 130. The third bonding pads 135 may be disposed adjacent to edge portions 130e of the third semiconductor chips 130. The third bonding pads 135 may be provided to correspond to the second bonding pads 125 and be electrically connected to the third center pads 134 via third redistributed lines 136. Accordingly, the third bonding pads 135 may be electrically connected to the third integrated circuits via the third center pads 134.

One or more of the fourth semiconductor chips 140 may include a fourth integrated circuit, a fourth center pad 144, and a fourth bonding pad 145. In example embodiments, the fourth bonding pads 145 may be provided at edge portions 140e of the fourth semiconductor chips 140 to be arranged adjacent to each other. The fourth semiconductor chips 140 may each include a seventh surface 140a facing a corresponding third semiconductor chip 130 and an eighth surface 140b opposite the seventh surface 140a.

Similar to the second integrated circuit IC2 shown in FIG. 13C, the fourth integrated circuit may be provided in the fourth semiconductor chip 140 adjacent to the seventh surface 140a. The fourth center pads 144 and the fourth bonding pads 145 may be provided on the seventh surfaces 140a of the fourth semiconductor chips 140. The fourth center pads 144 may be provided in central regions of the fourth semiconductor chips 140. The fourth bonding pads 145 may be disposed adjacent to edge portions 140e of the fourth semiconductor chips 140. The fourth bonding pads 145 may be provided to correspond to the third bonding pads 135 and be electrically connected to the fourth center pads 144 via the fourth redistributed lines 146. Accordingly, the fourth bonding pads 145 may be electrically connected to the fourth integrated circuits via the fourth center pads 144.

The second semiconductor chips 120, third semiconductor chips 130, and fourth semiconductor chips 140 may be attached to each other by adhesive layers 210.

The second bonding pads 125, the third bonding pads 135, and the fourth bonding pads 145 may be connected to each other in a side connection manner, as described previously with respect to FIG. 10.

A semiconductor package 13 according to a thirteenth embodiment of the inventive concepts will now be described with reference to FIG. 15. Discussion of features identical to those of FIG. 14 will be minimized to avoid redundancy.

Referring to FIG. 15, unlike the embodiment shown in FIG. 14, the third semiconductor chips 130 of this embodiment may be shifted toward the center of the package substrate 100 to expose the third bonding pads 135 of the third semiconductor chips 130, and the fourth semiconductor chips 140 may be shifted toward the center of the package substrate 100 to expose the fourth bonding pads 145 of the fourth semiconductor chips 140.

The second and third bonding pads 125 and 135, respectively, may be connected to each other by first subwires 42, and the third and fourth bonding pads 135 and 145, respectively, may be connected to each other by second subwires 44.

According to the eleventh, twelfth, and thirteenth embodiments described above, the first integrated circuit IC1 of the first semiconductor chip 110 may be formed in the first semiconductor chip 110 adjacent to the first surface 110a, and the first bonding pads 115 may be provided on the first surface 110a of the first semiconductor chip 110. However, the inventive concepts are not limited to this configuration. For example, these embodiments may be modified in such a way that the first integrated circuit IC1 of the first semiconductor chip 110 is formed in the first semiconductor chip 110 adjacent to the second surface 110b and the first bonding pads 115 are provided on the second surface 110b of the first semiconductor chip 110, similar to the embodiment described with reference to FIGS. 8A and 8B.

According to the third through thirteenth embodiments described above, the bonding pads may be connected to the center pads, but the inventive concepts are not limited thereto. For example, these embodiments may be modified in such a way that the integrated circuit is directly connected to the edge pads (i.e., bonding pads) that are disposed adjacent to an edge portion of the semiconductor chip, without the center pads or without the use of the center pads, as described with respect to the second embodiment described shown in FIGS. 3A through 3E.

According to the fourth, fifth, sixth, tenth, and thirteenth embodiments described above, bonding pads may be connected by bonding wires including subwires, but the inventive concepts are not limited thereto. For example, these embodiments may be modified in such a way that the bonding pads may be connected by a side connection manner, as described, for example, with reference to FIG. 11.

FIG. 16 is a block diagram illustrating an electronic system 1000 according to example embodiments of the inventive concepts. Referring to FIG. 16, the electronic system 1000 may include at least one of the semiconductor packages according to the embodiments mentioned above. The electronic system 1000 may include a mobile device or a computer. As an illustration, the electronic system 1000 may include a memory system 1120, a processor 1130, a random access memory (RAM) 1140, and a user interface 1150 that that are electrically connected to a bus 1110. The processor 1130 may be configured to execute programs and control the electronic system 1000. The RAM 1140 may be used as an operating memory of the processor 1130. For example, all or each of the memory system 1120, the processor 1130, and the RAM 1140 may include the semiconductor package according to example embodiments of the inventive concepts. Alternatively, the processor 1130 and the RAM 1140 may be provided as components of a semiconductor package. The user interface 1150 may be used to input/output data to/from the electronic system 1000. The memory system 1120 may be configured to store code for operating the processor 1130, data processed by the processor 1130 or data inputted from the outside.

The electronic system 1000 of FIG. 16 may be applied to various electronic devices or systems. For example, the electronic system 1000 of FIG. 16 may be applied to a mobile system (e.g., a smartphone), a portable notebook, a MP3 player, a navigation system, a solid state disk (SSD), a server system, a vehicle, or household appliances.

According to example embodiments of the inventive concepts, semiconductor chips may be connected to each other via bonding wires that are provided through central regions thereof, and thus, the semiconductor package can be fabricated with low cost. Slave chips may be connected to the outside through a master chip, and this makes it possible to improve electric characteristics of the package.

While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.

Claims

1. A semiconductor package, comprising: a package substrate having a circuit pattern;a first semiconductor chip arranged on the package substrate, the first semiconductor chip comprising: a first surface facing the package substrate and a second surface opposite the first surface;a first integrated circuit; anda through-silicon via, wherein the through-silicon via is arranged in a central region of the first semiconductor chip and is electrically connected to the circuit pattern; anda pair of second semiconductor chips spaced apart from each other and disposed on the first semiconductor chip, each second semiconductor chip comprising: a second integrated circuit;a third surface facing the first semiconductor chip; anda fourth surface opposite the third surface,wherein the first semiconductor chip further comprises first bonding pads disposed on the second surface and connected to the through-silicon via, andwherein each of the second semiconductor chips further comprises a second bonding pad disposed on the fourth surface and electrically connected to the second integrated circuit.
2. The semiconductor package of claim 1, wherein the first semiconductor chips have a memory capacity that is two times that of each of the second semiconductor chips, and wherein a total memory capacity of the package is 2n times a memory capacity of the first semiconductor chip, where n is an integer.
3. The semiconductor package of claim 1, further comprising a first bumper arranged between the first semiconductor chip and the package substrate to electrically connect the through-silicon via to the circuit pattern.
4. The semiconductor package of claim 1, further comprising: a pair of third semiconductor chips spaced apart from each other and arranged on the second semiconductor chips, each of the third semiconductor chips comprising: a third integrated circuit; anda third bonding pad, wherein the third bonding pad is located near an edge portion of each of the third semiconductor chips, and wherein the third bonding pad is electrically connected to the third integrated circuit; anda pair of fourth semiconductor chips spaced apart from each other and arranged on the third semiconductor chips, each of the fourth semiconductor chips comprising: a fourth integrated circuit; anda fourth bonding pad, wherein the fourth bonding pad is located near an edge portion of each of the fourth semiconductor chips, and wherein the fourth bonding pad is electrically connected to the fourth integrated circuit.
5. The semiconductor package of claim 4, wherein each of the third semiconductor chips has a fifth surface facing the second semiconductor chips and a sixth surface opposite the fifth surface, and wherein the third bonding pads are disposed on the sixth surfaces, and wherein each of the fourth semiconductor chips has a seventh surface facing the sixth surface of a corresponding each of the third semiconductor chips and an eighth surface opposite the seventh surface, and wherein the fourth bonding pads are disposed on the eighth surfaces.
6. The semiconductor package of claim 5, wherein each of the second semiconductor chips further comprises a connection pad on the third surface, and wherein the semiconductor package further comprises second bumpers disposed between the first and second semiconductor chips to electrically connect the connection pads to the first bonding pads.
7. The semiconductor package of claim 6, wherein corresponding ones of the connection pads, the second bonding pads, the third bonding pads, and the fourth bonding pads are connected to each other in a side connection manner.
8. The semiconductor package of claim 5, wherein the third semiconductor chips are shifted toward an edge of the package substrate to expose the second bonding pads of the second semiconductor chips, and wherein the fourth semiconductor chips are shifted toward the edge of the package substrate to expose the third bonding pads of the third semiconductor chips.
9. The semiconductor package of claim 8, wherein the second semiconductor chips further comprise connection pads arranged on the third surfaces, wherein the semiconductor package further comprises second bumpers disposed between the first semiconductor chip and the second semiconductor chips to connect the connection pads to corresponding ones of the first bonding pads, andwherein corresponding ones of the connection pads, the second bonding pads, the third bonding pads, and the fourth bonding pads are connected to each other in a side connection manner.
10. The semiconductor package of claim 1, wherein the first bonding pads are also provided on the first surface.
11. The semiconductor package of claim 1, wherein the first semiconductor chip further comprises first bonding pads provided on the first surface and connected to the through-silicon via, and wherein each of the second semiconductor chips further comprises a second bonding pad arranged on the third surface and electrically connected to the second integrated circuit.
12. A semiconductor package, comprising: a package substrate having a circuit pattern;a first semiconductor chip arranged on the package substrate, the first semiconductor chip comprising: a first surface facing the package substrate and a second surface opposite the first surface;a first integrated circuit;a through-silicon via, wherein the through-silicon via is arranged in a central region of the first semiconductor chip and is electrically connected to the circuit pattern; andfirst bonding pads provided on the first surface and connected to the through-silicon via;a pair of second semiconductor chips spaced apart from each other and disposed on the first semiconductor chip, each second semiconductor chip comprising: a second integrated circuit;a third surface facing the first semiconductor chip;a fourth surface opposite the third surface; anda second bonding pad arranged on the third surface and electrically connected to the second integrated circuit;a third semiconductor chip disposed on each of the second semiconductor chips, each of the third semiconductor chip comprising: a third integrated circuit; anda third bonding pad, wherein the third bonding pad is located near an edge portion of each of the third semiconductor chips and is electrically connected to the third integrated circuit; anda fourth semiconductor chip disposed on each of the third semiconductor chips, wherein each of the fourth semiconductor chips comprising: a fourth integrated circuit; anda fourth bonding pad, wherein the fourth bonding pad is located near an edge portion of each of the fourth semiconductor chips and is electrically connected to the fourth integrated circuit.
13. The semiconductor package of claim 12, wherein each of the third semiconductor chips has a fifth surface facing a corresponding second semiconductor chip and a sixth surface opposite the fifth surface, and wherein the third bonding pad is disposed on the fifth surface, and wherein each of the fourth semiconductor chips has a seventh surface facing the sixth surface of a corresponding third semiconductor chip and an eighth surface opposite the seventh surface, and wherein the fourth bonding pad is disposed on the seventh surface.
14. The semiconductor package of claim 13, wherein corresponding ones of the second bonding pads, the third bonding pads, and the fourth bonding pads are connected to each other in a side connection manner.
15. The semiconductor package of claim 13, wherein the third semiconductor chip is shifted toward a central region of the package substrate to expose the third bonding pads, and wherein the fourth semiconductor chip is shifted toward the central region of the package substrate to expose the fourth bonding pads.
16. The semiconductor package of claim 12, further comprising a second bumper disposed between the first and second semiconductor chips to connect one of the second bonding pads to the through-silicon via.
17. A semiconductor package, comprising: a package substrate having a circuit pattern;a first semiconductor chip arranged on the package substrate, the first semiconductor chip comprising: a first surface facing the package substrate and a second surface opposite the first surface, wherein the first surface is spaced apart from the package substrate;a first integrated circuit; anda through-silicon via, wherein the through-silicon via is arranged in a central region of the first semiconductor chip and is electrically connected to the circuit pattern;a pair of second semiconductor chips spaced apart from each other and disposed on the first semiconductor chip, each second semiconductor chip comprising: a second integrated circuit;a third surface facing the first semiconductor chip; anda fourth surface opposite the third surface;a first bumper arranged between the first semiconductor chip and the package substrate to electrically connect the through-silicon via to the circuit pattern;a second bumper arranged between the first semiconductor chip and one of the second semiconductor chips; anda third semiconductor chip disposed on the one of the second semiconductor chips and electrically connected to the through-silicon via through the second bumper;wherein the third semiconductor chip is electrically connected to the first bumper through a conductive structure extending around the one of the second semiconductor chips.
18. The semiconductor package of claim 17, further comprising first bonding pads disposed on the second surface and connected to the through-silicon via, wherein the first bonding pads are spaced apart from the package substrate.

Priority Claims (1)

Number	Date	Country	Kind
10-2012-0149602	Dec 2012	KR	national

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application is a divisional of U.S. patent application Ser. No. 14/064,110, filed Oct. 25, 2013 which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0149602, filed on Dec. 20, 2012, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

US Referenced Citations (239)

Number	Name	Date	Kind
5177594	Chance et al.	Jan 1993	A
5200806	Sawaya	Apr 1993	A
5343366	Cipolla et al.	Aug 1994	A
5818107	Pierson et al.	Oct 1998	A
5838061	Kim	Nov 1998	A
6037666	Tajima	Mar 2000	A
6133637	Hikita et al.	Oct 2000	A
6175157	Morifuji	Jan 2001	B1
6232668	Hikita et al.	May 2001	B1
6238949	Nguyen et al.	May 2001	B1
6245595	Nguyen et al.	Jun 2001	B1
6285084	Hikita et al.	Sep 2001	B1
6337579	Mochida	Jan 2002	B1
6355977	Nakamura	Mar 2002	B1
6369407	Hikita et al.	Apr 2002	B1
6376915	Hikita et al.	Apr 2002	B1
6396154	Hikita et al.	May 2002	B1
6399419	Shibata et al.	Jun 2002	B1
6404060	Hikita et al.	Jun 2002	B1
6424049	Sameshima	Jul 2002	B1
6458609	Hikita et al.	Oct 2002	B1
6459157	Oikawa	Oct 2002	B1
6462420	Hikita et al.	Oct 2002	B2
6476499	Hikita et al.	Nov 2002	B1
6507117	Hikita et al.	Jan 2003	B1
6534847	Hikita et al.	Mar 2003	B2
6555919	Tsai et al.	Apr 2003	B1
6580169	Sakuyama et al.	Jun 2003	B2
6602735	Shyu	Aug 2003	B2
6617693	Hikita et al.	Sep 2003	B2
6627979	Park	Sep 2003	B2
6635969	Nakamura	Oct 2003	B1
6635970	Lasky et al.	Oct 2003	B2
6657309	Hikita et al.	Dec 2003	B1
6661100	Anderson et al.	Dec 2003	B1
6674173	Wang	Jan 2004	B1
6689637	Park	Feb 2004	B2
6703713	Tseng et al.	Mar 2004	B1
6707140	Nguyen et al.	Mar 2004	B1
6717244	Hikita et al.	Apr 2004	B1
6720662	Den	Apr 2004	B1
6780670	Park	Aug 2004	B2
6835593	Shibata	Dec 2004	B2
6838312	Hikita et al.	Jan 2005	B2
6841870	Misumi	Jan 2005	B2
6869829	Hikita et al.	Mar 2005	B2
6870248	Shibata	Mar 2005	B1
6886076	Isodono et al.	Apr 2005	B1
6936929	Mostafazadeh et al.	Aug 2005	B1
7045386	Hikita et al.	May 2006	B2
7075177	Oka et al.	Jul 2006	B2
7091061	King et al.	Aug 2006	B2
7098070	Chen et al.	Aug 2006	B2
7126226	Hikita et al.	Oct 2006	B2
7144800	Mostafazadeh et al.	Dec 2006	B2
7157372	Trezza	Jan 2007	B1
7211885	Nordal et	May 2007	B2
7215032	Trezza	May 2007	B2
7224042	McCollum	May 2007	B1
7245021	Vindasius et al.	Jul 2007	B2
7269897	Frezza	Sep 2007	B2
7358601	Plants et al.	Apr 2008	B1
7443036	Iwasaki et al.	Oct 2008	B2
7482272	Trezza	Jan 2009	B2
7489025	Chen et al.	Feb 2009	B2
7521806	Trezza	Apr 2009	B2
7534722	Trezza	May 2009	B2
7538033	Trezza	May 2009	B2
7560813	Trezza	Jul 2009	B2
7633143	Fan	Dec 2009	B1
7652368	Hayashi et al.	Jan 2010	B2
7659202	Trezza	Feb 2010	B2
7736949	Chen et al.	Jun 2010	B2
7745258	Iwasaki et al.	Jun 2010	B2
7767493	Trezza et al.	Aug 2010	B2
7781886	Trezza et al.	Aug 2010	B2
7785931	Trezza	Aug 2010	B2
7785987	Trezza	Aug 2010	B2
7786592	Trezza	Aug 2010	B2
7808111	Trezza	Oct 2010	B2
7838997	Trezza	Nov 2010	B2
7843046	Andrews, Jr. et al.	Nov 2010	B2
7847412	Trezza	Dec 2010	B2
7851348	Misra et al.	Dec 2010	B2
7859118	Tsai	Dec 2010	B2
7863092	Chaware et al.	Jan 2011	B1
7884483	Trezza et al.	Feb 2011	B2
7919870	Trezza	Apr 2011	B2
7927919	Fan et al.	Apr 2011	B1
7932584	Trezza	Apr 2011	B2
7951699	Iwasaki et al.	May 2011	B2
7969015	Trezza	Jun 2011	B2
7986044	Mcconnell	Jul 2011	B2
7989958	Trezza et al.	Aug 2011	B2
7989959	Rahman	Aug 2011	B1
8053903	Trezza	Nov 2011	B2
8067312	Trezza	Nov 2011	B2
8084867	Tang et al.	Dec 2011	B2
8093729	Trezza	Jan 2012	B2
8143712	Chen	Mar 2012	B2
8154131	Trezza et al.	Apr 2012	B2
8354742	Camacho et al.	Jan 2013	B2
8482133	Ko et al.	Jul 2013	B2
20010008310	Sakuyama et al.	Jul 2001	A1
20010035568	Shyu	Nov 2001	A1
20020017718	Hikita et al.	Feb 2002	A1
20020020904	Hikita et al.	Feb 2002	A1
20020056899	Hikita et al.	May 2002	A1
20020058357	Chang	May 2002	A1
20020105067	Oka et al.	Aug 2002	A1
20020127773	Shibata et al.	Sep 2002	A1
20020130404	Ushijima et al.	Sep 2002	A1
20020190354	Park	Dec 2002	A1
20020190369	Hikita et al.	Dec 2002	A1
20020192866	Hikita et al.	Dec 2002	A1
20020192869	Park	Dec 2002	A1
20030062620	Shibata	Apr 2003	A1
20030082897	Sakuyama et al.	May 2003	A1
20030122248	Hikita et al.	Jul 2003	A1
20030146517	Lasky et al.	Aug 2003	A1
20030218191	Nordal et al.	Nov 2003	A1
20040007775	Park	Jan 2004	A1
20040016999	Misumi	Jan 2004	A1
20040026790	Hikita et al.	Feb 2004	A1
20040137708	Shibata	Jul 2004	A1
20040163240	Frezza	Aug 2004	A1
20040245651	Nishisako et al.	Dec 2004	A1
20040259288	Mostafazadeh et al.	Dec 2004	A1
20050012116	Lim et al.	Jan 2005	A1
20050040541	Kurita et al.	Feb 2005	A1
20050170558	King et al.	Aug 2005	A1
20050205983	Origasa et al.	Sep 2005	A1
20050242426	Kwon et al.	Nov 2005	A1
20050258530	Vindasius et al.	Nov 2005	A1
20060012038	Miyazaki et al.	Jan 2006	A1
20060105496	Chen et al.	May 2006	A1
20060113598	Chen	Jun 2006	A1
20060134832	Iwasaki et al.	Jun 2006	A1
20060211380	Mcconnell	Sep 2006	A1
20060237705	Kuo et al.	Oct 2006	A1
20060237828	Robinson et al.	Oct 2006	A1
20060270104	Trovarelli et al.	Nov 2006	A1
20060278966	Trezza et al.	Dec 2006	A1
20060278980	Trezza et al.	Dec 2006	A1
20060278981	Trezza et al.	Dec 2006	A1
20060278986	Trezza	Dec 2006	A1
20060278988	Trezza et al.	Dec 2006	A1
20060278989	Trezza	Dec 2006	A1
20060278992	Trezza et al.	Dec 2006	A1
20060278993	Trezza et al.	Dec 2006	A1
20060278994	Trezza	Dec 2006	A1
20060278995	Trezza	Dec 2006	A1
20060278996	Trezza et al.	Dec 2006	A1
20060281219	Trezza	Dec 2006	A1
20060281243	Trezza	Dec 2006	A1
20060281292	Trezza et al.	Dec 2006	A1
20060281296	Misra et al.	Dec 2006	A1
20060281303	Trezza et al.	Dec 2006	A1
20060281307	Trezza	Dec 2006	A1
20060281363	Trezza	Dec 2006	A1
20070013038	Yang	Jan 2007	A1
20070018303	Lee	Jan 2007	A1
20070037320	Mostafazadeh et al.	Feb 2007	A1
20070120241	Trezza et al.	May 2007	A1
20070138562	Trezza	Jun 2007	A1
20070141750	Iwasaki et al.	Jun 2007	A1
20070158839	Trezza	Jul 2007	A1
20070161235	Trezza	Jul 2007	A1
20070167004	Trezza	Jul 2007	A1
20070172987	Dugas et al.	Jul 2007	A1
20070182020	Trezza et al.	Aug 2007	A1
20070196948	Trezza	Aug 2007	A1
20070197013	Trezza	Aug 2007	A1
20070228576	Trezza	Oct 2007	A1
20080001241	Tuckerman et al.	Jan 2008	A1
20080002460	Tuckerman et al.	Jan 2008	A1
20080029879	Tuckerman et al.	Feb 2008	A1
20080083978	Hayashi et al.	Apr 2008	A1
20080128888	Park et al.	Jun 2008	A1
20080171174	Trezza	Jul 2008	A1
20080191363	Plants et al.	Aug 2008	A1
20080224279	Caskey et al.	Sep 2008	A1
20080274590	Iwasaki et al.	Nov 2008	A1
20080303131	Mcelrea et al.	Dec 2008	A1
20080318360	Chen et al.	Dec 2008	A1
20090045527	Tsai	Feb 2009	A1
20090068790	Caskey et al.	Mar 2009	A1
20090137116	Trezza	May 2009	A1
20090206458	Andrews, Jr. et al.	Aug 2009	A1
20090209064	Nonahasitthichai et al.	Aug 2009	A1
20090243064	Camacho	Oct 2009	A1
20090269888	Trezza	Oct 2009	A1
20100090326	Baek et al.	Apr 2010	A1
20100117242	Miller et al.	May 2010	A1
20100127768	Nonoyama et al.	May 2010	A1
20100140776	Trezza	Jun 2010	A1
20100140811	Leal et al.	Jun 2010	A1
20100197134	Trezza	Aug 2010	A1
20100219503	Trezza	Sep 2010	A1
20100244268	Tang et al.	Sep 2010	A1
20100304565	Trezza	Dec 2010	A1
20100327461	Co et al.	Dec 2010	A1
20110037159	Mcelrea et al.	Feb 2011	A1
20110084365	Law et al.	Apr 2011	A1
20110089522	Narazaki	Apr 2011	A1
20110089554	Lee et al.	Apr 2011	A1
20110090004	Schuetz	Apr 2011	A1
20110109382	Jin et al.	May 2011	A1
20110133324	Fan et al.	Jun 2011	A1
20110147931	Nondhasitthichai et al.	Jun 2011	A1
20110147932	Trezza et al.	Jun 2011	A1
20110156232	Youn et al.	Jun 2011	A1
20110161583	Youn	Jun 2011	A1
20110198752	Nondhasitthichai et al.	Aug 2011	A1
20110212573	Trezza et al.	Sep 2011	A1
20110223717	Trezza et al.	Sep 2011	A1
20110250722	Trezza	Oct 2011	A1
20110263119	Li et al.	Oct 2011	A1
20110272788	Kim et al.	Nov 2011	A1
20110275178	Trezza et al.	Nov 2011	A1
20110291229	Byeon et al.	Dec 2011	A1
20110291288	Wu	Dec 2011	A1
20110291289	Yoon et al.	Dec 2011	A1
20120013018	Chen	Jan 2012	A1
20120034739	Trezza	Feb 2012	A1
20120043664	Coteus et al.	Feb 2012	A1
20120049361	Park et al.	Mar 2012	A1
20120049365	Ko et al.	Mar 2012	A1
20120051113	Choi et al.	Mar 2012	A1
20120068360	Best	Mar 2012	A1
20120069530	Inoue et al.	Mar 2012	A1
20120086125	Kang et al.	Apr 2012	A1
20120108009	Trezza	May 2012	A1
20120146209	Hu	Jun 2012	A1
20120168960	Kim et al.	Jul 2012	A1
20130175706	Choi	Jul 2013	A1
20140151877	Lim et al.	Jun 2014	A1
20140199811	Haba et al.	Jul 2014	A1
20150221603	Ooi	Aug 2015	A1

Foreign Referenced Citations (104)

Number	Date	Country
H06232196	Aug 1994	JP
H09186289	Jul 1997	JP
H10144862	May 1998	JP
H10209370	Aug 1998	JP
H10256472	Sep 1998	JP
H10270636	Oct 1998	JP
H11040601	Feb 1999	JP
H11163051	Jun 1999	JP
H11163256	Jun 1999	JP
2000216328	Aug 2000	JP
2000223655	Aug 2000	JP
2000227457	Aug 2000	JP
2000228484	Aug 2000	JP
2000228485	Aug 2000	JP
2000228487	Aug 2000	JP
2000230964	Aug 2000	JP
2000232200	Aug 2000	JP
2000243896	Sep 2000	JP
2000243902	Sep 2000	JP
2000243903	Sep 2000	JP
2000243904	Sep 2000	JP
2000252409	Sep 2000	JP
2000260961	Sep 2000	JP
2001015680	Jan 2001	JP
2001085609	Mar 2001	JP
2001094037	Apr 2001	JP
2001094038	Apr 2001	JP
2001094042	Apr 2001	JP
2001110983	Apr 2001	JP
2001156249	Jun 2001	JP
2001168270	Jun 2001	JP
2001196528	Jul 2001	JP
2001267358	Sep 2001	JP
2001320012	Nov 2001	JP
2002026238	Jan 2002	JP
2002110851	Apr 2002	JP
2002110894	Apr 2002	JP
3286196	May 2002	JP
2003060155	Feb 2003	JP
2003060156	Feb 2003	JP
2003110084	Apr 2003	JP
2003110085	Apr 2003	JP
2003142647	May 2003	JP
2003142649	May 2003	JP
3423930	Jul 2003	JP
2003249515	Sep 2003	JP
2003282820	Oct 2003	JP
2004006941	Jan 2004	JP
2004071648	Mar 2004	JP
2004079685	Mar 2004	JP
3543253	Jul 2004	JP
3543254	Jul 2004	JP
3615672	Feb 2005	JP
2005064362	Mar 2005	JP
2005184023	Jul 2005	JP
2006024752	Jan 2006	JP
2006179570	Jul 2006	JP
2007059547	Mar 2007	JP
2007059548	Mar 2007	JP
2007165631	Jun 2007	JP
2007165671	Jun 2007	JP
2008219039	Sep 2008	JP
2009021329	Jan 2009	JP
19990037241	May 1999	KR
100206893	Jul 1999	KR
20010067308	Jul 2001	KR
20020008586	Jan 2002	KR
100363057	Nov 2002	KR
20030012192	Feb 2003	KR
100378285	Mar 2003	KR
100393101	Jul 2003	KR
100434201	Jun 2004	KR
100467946	Jan 2005	KR
100488256	May 2005	KR
100522223	Dec 2005	KR
20060036126	Apr 2006	KR
100604848	Jul 2006	KR
100631934	Oct 2006	KR
20080016124	Feb 2008	KR
20080018895	Feb 2008	KR
20080018896	Feb 2008	KR
100817078	Mar 2008	KR
20090091453	Aug 2009	KR
20100011613	Feb 2010	KR
20110012645	Feb 2011	KR
20110042393	Apr 2011	KR
10-2011-0048733	May 2011	KR
20110052133	May 2011	KR
20110078188	Jul 2011	KR
20110078189	Jul 2011	KR
101070167	Oct 2011	KR
101088546	Dec 2011	KR
101090616	Dec 2011	KR
20110130113	Dec 2011	KR
20110131578	Dec 2011	KR
20110131683	Dec 2011	KR
20110137059	Dec 2011	KR
20120019882	Mar 2012	KR
101137688	Apr 2012	KR
20120035725	Apr 2012	KR
101137934	May 2012	KR
101168786	Jul 2012	KR
101191523	Oct 2012	KR
101224299	Jan 2013	KR

Related Publications (1)

	Number	Date	Country
	20150155266 A1	Jun 2015	US

Divisions (1)

	Number	Date	Country
Parent	14064110	Oct 2013	US
Child	14613357		US

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