BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view of a semiconductor device in accordance with a first embodiment of the present invention;
FIG. 1
a is a sectional view taken along line 1a-1a in FIG. 1;
FIG. 1
b is a sectional view taken along line 1b-1b in FIG. 1;
FIG. 2 is a plan view of a semiconductor device in accordance with a second embodiment of the present invention;
FIG. 2
a is sectional view taken along line 2a-2a in FIG. 2;
FIG. 3 is a plan view of a semiconductor device in accordance with a third embodiment of the present invention;
FIG. 3
a is a sectional view taken along line 3a-3a in FIG. 3; and
FIG. 3
b is a sectional view taken along line 3b-3b in FIG. 3.