BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B are drawings (FIG. 1A is a schematic plan view and FIG. 1B is a schematic cross-sectional view which goes along a′-a′ line of FIG. 1A) showing the internal structure of the semiconductor device which is Example 1 of the present invention;
FIG. 2 is the schematic cross-sectional view which expanded a part of FIG. 1B;
FIG. 3 is the schematic cross-sectional view which expanded the portion of the electrode pad for wire connection of FIG. 2;
FIG. 4 is the schematic cross-sectional view which expanded the portion of the electrode pad for bump connection of FIG. 2;
FIG. 5 is a schematic plan view of the multi-wiring substrate used for manufacture of the semiconductor device which is Example 1 of the present invention;
FIG. 6 is a schematic cross-sectional view expanding and showing a part of multi-wiring substrate of FIG. 5;
FIG. 7 is the schematic cross-sectional view which expanded a part of FIG. 6;
FIG. 8 is the schematic cross-sectional view which expanded the electrode pad portion for wire connection of FIG. 7;
FIG. 9 is the schematic cross-sectional view which expanded the electrode pad portion for bump connection of FIG. 7;
FIG. 10 is a flow chart which shows the manufacturing process of the semiconductor device which is Example 1 of the present invention;
FIGS. 11 to 15 are schematic cross-sectional views showing the manufacturing process of the semiconductor device which is Example 1 of the present invention;
FIGS. 16A to 16C are drawings (FIGS. 16A to 16C are schematic cross-sectional views in each step) for explaining the first bump forming step in manufacture of the semiconductor device which is Example 1 of the present invention;
FIGS. 17A and 17B are drawings (FIGS. 17A and 17B are schematic cross-sectional views in each step) for explaining the second bump forming step in manufacture of the semiconductor device which is Example 1 of the present invention;
FIG. 18 is a schematic plan view showing the outline structure of the module (electronic device) incorporating the semiconductor device which is Example 1 of the present invention;
FIG. 19 is a schematic cross-sectional view which goes along b′-b′ line of FIG. 18;
FIG. 20 is the schematic cross-sectional view which expanded a part of FIG. 19;
FIG. 21 is the schematic cross-sectional view which expanded a part of FIG. 20;
FIG. 22 is a schematic plan view showing the outline structure of the cellular phone (portable electronic apparatus) incorporating the module of FIG. 18;
FIG. 23 is a drawing for explaining the electrolytic plating method;
FIG. 24 is a profile which shows the impurity concentration profile in Ni film;
FIG. 25 is a drawing showing the thickness of Ni film when fixing plating time in 30 minutes and forming Ni film on conditions of 1-3;
FIG. 26 is the drawing which made the table conditions 1-3 of FIG. 25;
FIGS. 27 and 28 are drawings for explaining the valuation method of impact strength;
FIG. 29 is a drawing showing the relation between the chlorine (Cl) concentration in Ni film, and a substrate warp (impact strength: ppm);
FIG. 30 is a drawing showing the relation between the current density at the time of Ni film formation (A/dm2), and impact strength (ppm);
FIG. 31 is a drawing showing the relation between the current density at the time of Ni film formation (A/dm2), and the chlorine (Cl) concentration in Ni film;
FIG. 32 is a drawing showing the relation between the current density at the time of Ni film formation (A/dm2), and the carbon (C) concentration in Ni film;
FIG. 33 is a drawing showing the relation between the plating time (minute) of Ni film, and the thickness (μm) of Ni film;
FIG. 34 is a drawing showing the relation between the plating time (minute) of Ni film, and current density (A/dm2);
FIG. 35 is a drawing showing the relation between average current density (A/dm2), and the thickness of Ni film (μm);
FIGS. 36A and 36B are drawings (FIG. 36A is a schematic cross-sectional view showing the whole structure, and FIG. 36B is the schematic cross-sectional view which expanded a part of FIG. 36A) showing the internal structure of the semiconductor device which is Example 2 of the present invention;
FIG. 37 is a schematic cross-sectional view showing the outline structure of the BGA type semiconductor device which is Example 3 of the present invention;
FIG. 38 is the schematic cross-sectional view which expanded a part of FIG. 37;
FIG. 39 is a cross-sectional view showing the outline structure of the semiconductor device which is Example 4 of the present invention;
FIG. 40 is the principal part cross-sectional view which expanded a part of FIG. 39;
FIG. 41 is a schematic cross-sectional view showing the outline structure of the SiP type semiconductor device which is Example 5 of the present invention; and
FIG. 42 is the schematic cross-sectional view which expanded a part of FIG. 41.