Controlling Flip-Chip Techniques for Concurrent Ball Bonds in Semiconductor Devices

Abstract

A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere (105) is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate (110) with a chip attachment location and a third set of contact pads (112) near the location. Low profile bond wires (130) span between the pads of the third set and the second set. A second semiconductor chip (140) of a size has a fourth set of contact pads (141) at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal (142) bonds the spacers to the second chip, while the spacers space the first and second chips by a gap (105a) wide enough for placing the wire spans to the second set pads.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic cross section of a device with a first semiconductor chip having one set of contact pads for wire bonding to a substrate, and another set of contact pads with spacers allowing the flip-assembly of an about equally-sized second chip while controlling the spacing gap between the chips.

FIG. 2 is a schematic cross section of an electronic system, which includes the semiconductor device of FIG. 1 in combination with another device flip-assembled on the semiconductor device.

FIG. 3 shows a schematic block diagram of certain process flow steps for fabricating a device with stacked chips as illustrated in FIG. 1; the process flow combines wire bond and flip assembly techniques by means of controlling the gap between the assembled chips.

FIGS. 4 to 7 illustrate schematically the significant steps of the fabrication process of the spacer and the device assembly.

FIG. 4 shows schematically the squeezed sphere of a free air ball attached to a chip contact pad.

FIG. 5 shows schematically the formation of a column-shaped spacer fabricated by two squeezed free air balls on a chip contact pad.

FIG. 6 shows schematically the alignment of two chips; one chip has a contact pad used for wire bonding and another contact pad used for a column-shaped spacer.

FIG. 7 shows schematically the stacked device after the process step of reflowing the solder on the second chip to bond to the spacers of the first chip, while keeping the two chips spaced by the height of the spacers wide enough for accommodating the wire spans of the wire-bonded contact pads.

Claims

1. A semiconductor device comprising: a first semiconductor chip having a size and an active and a passive surface, the active surface including an interior first set and a peripheral second set of contact pads at pad locations;a deformed sphere of non-reflow metal placed on the contact pads of the first and second sets;at least one additional deformed sphere placed on the spheres of the first set pads, forming column-shaped spacers having a height;a substrate having a first surface with an attachment location and a third set of contact pads near the location;the passive surface of the first chip attached to the substrate attachment location;low-profile bond wire spans between the pads of the third set and the second set to electrically connect the substrate and the first chip, the profile being lower than the height of the spacers;a second semiconductor chip having a second size and a fourth set of contact pads at locations matching the first set;the second chip placed over the first chip and the fourth set pads aligned with the spacers on the matching first set pads; anda reflow metal on the fourth set pads bonding to the spacers, connecting the second and first chips, at least one edge of the second chip overhanging the sphere on at least one pad of the second set.

2. The device according to claim 1 wherein the deformed spheres have about equal size.

3. The device according to claim 1 wherein the non-reflow metal includes gold.

4. The device according to claim 1 wherein the second chip has a size approximately equal to the first chip size.

5. The device according to claim 1 further including a polymer material to fill the gap between the first and second chips.

6. The device according to claim 5 wherein the polymer material includes a precursor based on an epoxy and polyimide compound.

7. The device according to claim 1 wherein the substrate is a third semiconductor chip.

8. The device according to claim 7 further including reflow bodies attached to the substrate surface opposite to its first surface to provide connection to external parts.

9. The device according to claim 1 further including an encapsulation of the third set pads and the connecting bond wires in protective material.

10. A method for fabricating a semiconductor device comprising the steps of: providing a first chip having a size, an active and a passive surface, the active surface including devices having an interior first set and a peripheral second set of contact pads;providing a substrate having a first surface with an attachment location and a third set of contact pads near the location;attaching the passive surface of the first chip onto the attachment location of the substrate;placing and squeezing squeezed a gold ball on each contact pad of the first and second sets;repeating the ball placing and squeezing for the pads of the first set to create column-shaped spacers of a height;spanning low profile wire bonds between the pads of the second and the third sets to electrically connect the first chip and the substrate, the profile being lower than the height of the spacers;providing a second semiconductor chip having a second size and devices with a fourth set of contact pads at locations matching the first pad set;applying reflow metal to the pads of the fourth set, or to the spacers, or to both;placing the second chip over the first chip and aligning the fourth set pads with the spacers on the matching first set pads so that at least one edge of the second chip overhangs the ball on at least one pad of the second set; andapplying thermal energy to reflow the metal for bonding the fourth set pads to the spacers on the first set pads, electrically connecting the first and the second chip.

11. The method according to claim 10 further including, after the step of spanning the wire bonds, the step of depositing a polymer precursor material over the active surface of the first chip in a height about equal to the spacer height, protecting the bonds on the second set pads.

12. The method according to claim 10 further including the step of encapsulating the wire bonds and at least a portion of the substrate in a protective material.

13. The method according to claim 10 wherein the substrate is a third semiconductor chip.

14. The method according to claim 10 wherein the substrate has an insulating body integral with conductive lines and vias.

15. The method according to claim 10 wherein the squeezed gold ball is a free air ball in gold wire bonding.

16. The method according to claim 15 wherein the repeated gold ball placings are produced from free air balls in gold wire bonding so that the squeezed balls have about equal size and are bonded together to form a column-shaped spacer.

17. The method according to claim 16 wherein the repeated placings produce spacers of about the same height so that the first and the second chip are spaced by substantially uniform distance.

18. The method according to claim 10 wherein the wires between the pads of the second and the third set are placed so that the ball is attached to the pad of the third set and the stitch is attached to the previously placed squeezed ball on the pad of the second set.

19. The method according to claim 10 further including the step of attaching reflow bodies to the substrate surface opposite its first surface to provide connection to external parts, the melting temperature of the reflow bodies lower than the melting temperature of the reflow metal employed on the fourth set pads.