Patent Application
20120126396
1. Field
The present invention generally relates to IC devices and IC device packages.
2. Background
Integrated circuit (IC) devices can be formed by mounting an IC die in or on a package that facilitates attachment to a printed circuit board (PCB). One such type of IC package is a ball grid array (BGA) package. BGA packages provide for relatively small footprints.
Existing BGA devices are subject to high thermal stresses that result from the heat given off during operation of the mounted IC die. The thermal stresses are often imposed on the IC device due to the heat generated by the IC die.
Methods and apparatuses for a die down device with a thermal connector are provided. In one embodiment, an integrated circuit (IC) device includes an IC die having opposing first and second surfaces, a thermal connector coupled to the first surface of the IC die, and a substrate. The second surface of the IC die is coupled to the substrate. The thermal connector is configured to be coupled to a circuit board.
In another embodiment, a method of assembling an integrated circuit device includes coupling a thermal connector to a first surface of an IC die and coupling a second surface of the IC die to a substrate. The thermal connector is configured to be coupled to a circuit board.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings.
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.
The present invention will be described with reference to the accompanying drawings. Generally, the drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.
The present invention has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The foregoing description of the specific embodiments will fully reveal the general nature of the invention so that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Furthermore, it should be understood that spatial descriptions (e.g., “above”, “below”, “left,” “right,” “up”, “down”, “top”, “bottom”, etc.) used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner.
Overview
A ball grid array (BGA) package is used to package and interface an IC die with a printed circuit board (PCB). BGA packages may be used with any type of IC die, and are particularly useful for high speed ICs. In a BGA package, solder pads do not just surround the package periphery, as in chip carrier type packages, but cover the entire bottom package surface in an array configuration. BGA packages are also referred to as pad array carrier (PAC), pad array, land grid array, and pad-grid array packages.
Die-up and die-down BGA package configurations exist. In die-down flip-chip packages, the active surface of the IC die faces in a direction away from the PCB and solder bumps can be used to couple contact pads on a surface of the IC die to the substrate. In die-up flip-chip BGA packages, the IC die is mounted on a top surface of the substrate or interposer and the active surface of the IC die faces in a direction away from the PCB.
Substrate 104 is generally made from one or more conductive layers bonded with a dielectric material. For instance, the dielectric material may be made from various substances, such as polyimide tape. The conductive layers are typically made from a metal, or combination of metals, such as copper and aluminum. Trace or routing patterns are made in the conductive layer material. In one embodiment, substrate 104 can be a single-layer, a two-layer, or additional layer substrate type. In a two-layer embodiment, the metal layers sandwich the dielectric layer, such as in a copper-Upilex-copper arrangement.
IC die 102 is attached to substrate 104, for example, by an epoxy. IC die 102 can be any type of semiconductor IC. One or more wire bonds 108 couple corresponding bond pads 118 on IC die 102 to contact points 120 on substrate 104. An encapsulate, mold compound, or epoxy 116 covers IC die 102 and wire bonds 108 for mechanical and environmental protection. Heat generated by IC die 102 can damage IC device 100. For example, the generated heat can lead to cracks in IC device 100.
As shown in
Stiffener 202 serves to provide stiffening for IC package 200, especially in the embodiment in which substrate 104 is a flexible substrate. Furthermore, stiffener 202 can also spread heat from IC die 102. For example, stiffener 202 can spread heat from IC die 102 to the PCB to which package 200 is mounted. In doing so, stiffener 202 can effectively cool package 200.
Thus, in some BGA packages, a die is attached to the substrate of the package (e.g., using an adhesive), and signals of the die are interfaced with electrical features (e.g., bond fingers) of the substrate using wire bonds. In such a BGA package, wire bonds are connected between signal pads/terminals of the die and electrical features of the substrate. In another type of BGA package, which may be referred to as a “flip chip package,” a die may be attached to the substrate of the package in a “flip chip” orientation. In such a BGA package, solder bumps are foamed on the signal pads/terminals of the die, and the die is inverted (“flipped”) and attached to the substrate by reflowing the solder bumps so that they attach to corresponding pads on the surface of the substrate.
The dies in integrated circuit packages, such as BGA packages, typically generate a great amount of heat during operation. Thus, BGA packages are frequently configured to disperse the generated heat so that their operation is not adversely affected by the generated heat. For example, an external heat sink may be attached to a BGA package to disperse heat from the BGA package. External heat sinks are effective solutions to improving the thermal performance of a package. However, in the case of die-down flip chip BGA packages, the package geometry creates additional complexities in the mounting of such heat sinks. For example, phase array antennas are typically designed on a surface of the substrate. Mounting an external heat sink or heat sinking devices to this surface will interfere with antenna operation.
Although IC device 200 provides for heat spreading from IC die 202, IC device 200 can only be used in die up configurations. In embodiments described herein, IC devices are provided that allow for heat spreading in die down configurations. For example a thermal connector may be provided that couples an IC die to a PCB, thereby spreading heat from the IC die to the PCB.
IC die 304 can be any one of a variety of types of IC dies. For example, IC die 304 can be an ASIC. In another embodiment, IC die 304 is a memory. Adhesive 308 couples thermal connector 306 to a first surface 305a of IC die 304. Adhesive 308 can be one of a variety of adhesives known to those skilled in the art. For example, adhesive 308 can be a thermally conductive adhesive, e.g., a thermally conductive epoxy. Thermal connector 306 will be described in greater detail below.
Substrate 302 is coupled to a second surface 305b of IC die 304 through bumps 310 and underfill material 312. Substrate 302 can be similar to substrate 104 described with reference to
Bumps 310 couple conductive regions on IC die 304 to conductive regions on substrate 302 and attach IC die 304 to substrate 302. Bumps 310 can be formed out of an electrically conductive material such as solder. Solder balls 316 are configured to couple substrate 302 to a PCB. Underfill material 312 physically fills the spaces in between IC die 304, solder bumps 310, and substrate 302. Underfill material 312 can be an encapsulation material, such as an epoxy.
Solder balls 316 are configured couple substrate 302 to a PCB. In alternate embodiments, other coupling elements can be used to couple substrate 302 to a PCB. For example, pins can be used to couple substrate 302 to a PCB.
Thermal connector 306 can be formed out a thermally conductive material. For example thermal connector 306 can be formed out of copper or silicon. In another embodiment, thermal connector 306 and adhesive 308 together can be implemented as a metal tape (e.g., a copper tape).
The thermal conductivity of air is approximately 0.026 W/° K/m. Compared to the thermal conductivity of silicon (in the approximate range of 130-150 W/m·K), air is not an effective conductor of heat from IC die 304. Furthermore, the thermal path between IC die 304 and a PCB through substrate 302 and solder balls 316 is a relatively long path (e.g., compared to the distance between first surface 305a and the PCB) and includes a variety of different materials, some of which do not have high thermal conductivities (e.g., the insulators included in substrate 302).
To provide an effective thermal path between IC die 304 and the PCB, thermal connector 306 is configured to couple IC die 304 to a PCB. In doing so, thermal connector 306 can conduct heat from IC die 304 to the PCB. The thermal conductivities of copper and silicon are approximately 390 W/m·K and 130 W/m·K, respectively. Thus, both silicon and copper have thermal conductivities that are approximately 1,000 times higher than air. Therefore, thermal connector 306 is much more effective at conducting heat away from IC die 304 than the air gap between IC die 304 and the PCB.
In a further embodiment, thermal connector 306 can be coated with a coating material 314. Coating material 314 can be used to enhance the coupling between thermal connector 306 and the PCB. For example, coating material 314 can facilitate the soldering of thermal connector 306 onto the PCB. Coating material 314 can be, for example, solder, tin, silver, or gold.
Thermal connector 306 of IC device 300 (not numerically referenced in
Signal planes 406 and 408 can be electrically conductive layers (e.g., copper layers) that are formed within insulator 418. One of signal planes 406 and 408 can be a ground plane. In another embodiment, neither of signal planes 406 and 408 is a ground plane.
Insulator 418 can be one of variety of different insulators used in printed circuit boards known to those skilled in the art. For example, insulator 418 can include a glass epoxy sheet such as FR-4. Although
Thermal and/or ground vias 412 couple thermal land 410 to backside thermal land 414. Vias 412 can function as thermal vias that conduct heat away from thermal land 410. For example, vias 412 can be filled with a thermally conductive material (e.g., copper) to enhance the thermal coupling between thermal land 410 and backside thermal land 414. Vias 412 can also be configured to carry a ground potential to thermal land 410. For example, one or more of vias 412 can be coupled to signal plane 404, which can be coupled to a ground potential.
Thermal connector 502 has a surface 504 that is coupled to surface 305a of IC die 304. As shown in
In one embodiment, first and second thermal connectors 902 and 904 can be located at hotspots of IC die 304. For example, IC die 304 can be analyzed to determine the location of one or more hotspots, i.e., location(s) on first surface 305a of IC die 304 that are relatively warmer during operation compared with the rest of first surface 305. For example, the analysis can include mapping functional blocks of die 304 to determine the location of the one or more hotspots. In another embodiment, the analysis includes performing a thermal analysis/measurement of the die during operation to determine the locations of the one or more hotspots.
By locating first and second thermal connectors 902 and 904 at hotspots of IC die 304, heat can be conducted from the hotspots, while conducting less heat from the cooler spots/areas (because thermal connectors are not coupled to the cooler spots/areas). In this manner, a thermal signature of IC die 304 surface can be made more uniform (cooling the hotspots to be closer in temperature to the cooler spots/areas).
In IC device 300, underfill material 312 can be a capillary underfill material that fills the gap between IC die 304 and substrate 302. In IC device 1100, on the other hand, underfill material 1102 can be a molded underfill material that is forced under IC die 304 and couples IC die 304. For example, the shape of molded underfill material 1102 can be set using a mold cavity or chase. Specifically, the mold cavity or chase can be filled with the underfill material, thus setting the shape of the underfill material based on the shape of the mold cavity or chase.
As shown in
In an embodiment, the devices shown in
Molded underfill material 1202 encapsulates both IC die 304 and thermal connector 1204. In doing so, underfill material 1202 effectively locks thermal connector 1204 on first surface 305a of IC die 304. That is, underfill material 1202 presses thermal connector 1204 against first surface 305a of IC die 304. Thus, an adhesive may not be needed to couple thermal connector 1204 to first surface 305a of IC die 304. In alternate embodiments, IC device 1200 can include an adhesive that further strengthens the coupling between thermal connector 1204 and IC die 304.
Underfill material 1202 can be molded using a mold chase or cavity. Thermal connector 1204 can be placed inside of the mold chase or cavity before the underfill material is applied. Once the underfill material is injected into the mold chase or cavity, thermal connector 1204 can be locked into place.
As shown in
Thermal connector 1302 can be created using a wafer backside metallization process, as would be understood by those skilled in the art based on the description herein. The wafer (which includes multiple IC dies) can be processed to create thermal connector 1302 before the assembly process for IC device 1300 begins. Thus, thermal connector 1302 can be provided without adding steps to the package assembly process for IC device 1300.
Thermal connector 1402 is a patterned thermal connector in which some regions of first surface 305a of IC die 304 are left exposed, while other regions of first surface 305a are covered by thermal connector 1402. One or more regions of first surface 305a that can be covered by thermal connector 1402 can be hotspots of IC die 304.
Thermal connector 1402 can be created by coating a wafer with a thermally conductive material and etching the coated material to form a desired pattern (e.g., the pattern shown in
Thermal connectors 1302 and 1402 can be formed out of one of a variety of different thermally conductive materials that can be coated to the surface of a wafer. For example, thermal connectors 1302 and 1402 can be formed out of gold, aluminum, tin, or silver-tin, or aluminum-tin alloys.
As shown in
Second IC die 1604 is mounted onto substrate 302 in a die up configuration. Electrical connections between second IC die 1604 and substrate 302 are provided by wirebonds 1608. Mold compound 1610 encapsulates second IC die 1604 and wirebonds 1608.
First IC die 304 can be coupled to second IC die 1604 through substrate 302. First IC die 304 can be an ASIC and second IC die 1604 can be a corresponding memory coupled to first IC die 304. Including an ASIC and a corresponding memory in the same device can optimize memory to ASIC interconnections and reduce the length of the connections between the two elements. Moreover, when an ASIC and a memory are included in separate packages, the resulting system can suffer from performance variations both due to the ASIC and memory being assembled by different parties and due to variations caused by the interconnections between the ASIC and memory (e.g., the interconnections on a PCB). By including the ASIC and memory in the same package, each of these types of performance variation can be reduced or eliminated. In other embodiments, second IC die 1604 can also be other types devices, e.g., RF devices.
Antenna plane 1702 is coupled to second surface 1602b of substrate 302. As shown in
Antenna 1802 is shown as a patch antenna in
Second IC die 190, second thermal connector 1904, second adhesive 1906, second bumps 1908, and second underfill material 1910 can be substantially similar to first IC die 304, first thermal connector 306, first adhesive 308, first bumps 1310, and first underfill material 312. Thus, in IC device 1900, multiple IC dies can be coupled to first surface 1602a of substrate 302. In the embodiment shown in
Including multiple IC dies in a single device can reduce the size of the overall component (e.g., because packaging is provided for the dies as a whole rather than each individual die). For example, in the embodiment in which an IC device is to be included in a mobile device, such as a cellular phone, by including multiple IC dies in single device (e.g., as shown in
As described above, a thermal land is an area on a PCB that receives a thermal connector. The thermal land has thermally conductive material that conducts heat away from the thermal connector.
Thermal/ground vias 2004 can be similar to thermal/ground vias 412 described with reference to
A distance 2006 between the center of adjacent thermal/ground vias 2004 can be approximately 1 mm. A distance 2008 between the center of an outer one of thermal/ground vias 2004 and the outer edge of thermal land 2000 can be approximately 100 μm. A distance 2010 between edges of adjacent thermal/ground vias 2004 can be approximately 1 mm. A distance 2014 between opposite edges of adjacent thermal/ground vias 2004 can be approximately 0.9 mm. As noted above, a diameter 2012 of thermal/ground vias 2004 can be approximately 225 μm.
Exemplary Methods of Assembly
In step 2202, a thermal connector is coupled to a first surface of an IC die. For example, in
The thermal connector can be coupled to the first surface of the IC die before or after wafer singulation. Before wafer singulation, the thermal connectors can be coupled as a group to the first surface of each IC die in the wafer. After singulation, the thermal connectors can be coupled to the first surface of each IC die individually.
In step 2204, the second surface of the IC die is coupled to a substrate. For example, in
In step 2206, an underfill material is injected between the IC die and the substrate. For example, in
In optional step 2208, additional elements are coupled to the substrate. For example, in the embodiments of
In step 2210, an array of connection elements can be coupled to the substrate. For example, in
Once the IC device has been manufactured, the IC device can be coupled to a PCB. For example, the IC device can be mounted on a PCB that includes a thermal land for receiving the thermal connector.
As noted above, the steps of flowchart 2200 do not have to occur in the order shown. For example, step 2204 can occur before step 2202 (e.g., the second surface of the IC die can be coupled to the substrate before the thermal connector is coupled to the first surface of the IC die). In a further embodiment, the step 2206 can occur before step 2202 (e.g., the underfill material can be injected between the substrate and the IC die before the thermal connector is coupled the first surface of the IC die).
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in fowl and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
