Interconnect substrate, semiconductor device, and method of manufacturing the same

Abstract

An interconnect substrate includes an interconnect, an insulating layer, a non-photosensitive resin layer, a photosensitive resin layer, a first electrode pad, and a second electrode pad. The non-photosensitive resin layer is constructed with a non-photosensitive insulating material. Also, the non-photosensitive resin layer has a first opening. The photosensitive resin layer is constructed with a photosensitive insulating material. Also, the photosensitive resin layer has a second opening. The opening area of the second opening is larger than that of the first opening. The first electrode pad is disposed on the first surface side of the insulating layer. The first electrode pad is exposed to the first opening. The second electrode pad is disposed on the second surface side of the insulating layer. The second electrode pad is exposed to the second opening.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view illustrating the first embodiment of an interconnect substrate and a semiconductor device according to the present invention;

FIGS. 2A and 2B are cross-sectional views illustrating a part of the semiconductor device of FIG. 1;

FIGS. 3A to 3C are process views illustrating one example of a method of manufacturing the semiconductor device of FIG. 1;

FIGS. 4A to 4C are process views illustrating one example of a method of manufacturing the semiconductor device of FIG. 1;

FIGS. 5A to 5C are process views illustrating one example of a method of manufacturing the semiconductor device of FIG. 1;

FIGS. 6A to 6C are process views illustrating one example of a method of manufacturing the semiconductor device of FIG. 1;

FIGS. 7A to 7C are process views illustrating one example of a method of manufacturing the semiconductor device of FIG. 1;

FIGS. 8A to 8C are process views illustrating one example of a method of manufacturing the semiconductor device of FIG. 1;

FIGS. 9A to 9C are process views illustrating one example of a method of manufacturing the semiconductor device of FIG. 1;

FIG. 10 is a cross-sectional view for describing a modified example of the embodiment;

FIG. 11 is a cross-sectional view for describing a modified example of the embodiment;

FIGS. 12A and 12B are cross-sectional views for describing a modified example of the embodiment;

FIG. 13 is a cross-sectional view for describing a modified example of the embodiment;

FIGS. 14A and 14B are cross-sectional views for describing one example of a conventional flip-chip type semiconductor device;

FIGS. 15A to 15C are process views illustrating a method of manufacturing a conventional build-up substrate; and

FIGS. 16A to 16C are process views illustrating a method of manufacturing the conventional build-up substrate.

Claims

1. An interconnect substrate comprising: an interconnect;an insulating layer covering said interconnect;a first layer provided on a first surface of said insulating layer and constructed with a non-photosensitive insulating material, said first layer having a first opening;a second layer provided on a second surface of said insulating layer, which is a surface opposite to said first surface, and constructed with a photosensitive insulating material, said second layer having a second opening with an opening area larger than that of said first opening;a first electrode pad provided on said first surface side of said insulating layer and exposed to said first opening; anda second electrode pad provided on said second surface side of said insulating layer and exposed to said second opening.

2. The interconnect substrate as set forth in claim 1, wherein said interconnect has a multi-layer interconnect structure.

3. The interconnect substrate as set forth in claim 1, wherein an area of said second electrode pad is larger than an area of said first electrode pad.

4. The interconnect substrate as set forth in claim 1, wherein opening areas of said first and second openings are smaller than areas of said first and second electrode pads, respectively.

5. The interconnect substrate as set forth in claim 1, wherein a material constituting said first electrode pad is a single element Cu.

6. The interconnect substrate asset forth in claim 1, wherein a multi-layer film of Ni and Au is provided on a part of said first electrode pad exposed to said first opening and on a part of said second electrode pad exposed to said second opening.

7. The interconnect substrate as set forth in claim 1, wherein said first electrode pad is an electrode pad to which a semiconductor chip is connected, andsaid second electrode pad is an electrode pad that is connected to a printed interconnect substrate.

8. The interconnect substrate as set forth in claim 1, wherein said first layer is a non-photosensitive insulating film.

9. A semiconductor device comprising: said interconnect substrate as set forth in claim 1; anda semiconductor chip connected to said first electrode pad.

10. The semiconductor device as set forth in claim 9, further comprising a second semiconductor chip provided on said semiconductor chip, wherein said second semiconductor chip is connected to said first electrode pad via a bonding wire.

11. The semiconductor device as set forth in claim 9, further comprising a heat sink provided on said semiconductor chip.

12. The semiconductor device as set forth in claim 11, wherein said heat sink is provided on an area from said semiconductor chip over to said first layer, and a part of said heat sink provided on said semiconductor chip protrudes relative to a part of said heat sink provided on said first layer.

13. A method of manufacturing an interconnect substrate, comprising: forming a first layer constructed with a non-photosensitive insulating material on a supporting substrate;forming a first electrode pad on said first layer;forming an interconnect and an insulating layer covering said interconnect on said first electrode pad;forming a second electrode pad on said insulating layer;forming a second layer constructed with a photosensitive insulating material so as to cover said second electrode pad;forming a second opening in said second layer so that said second electrode pad is exposed;removing said supporting substrate after forming said second opening; andforming a first opening in said first layer after removing said supporting substrate so that said first electrode pad is exposed, said first opening having an opening area smaller than that of said second opening.

14. The method of manufacturing an interconnect substrate as set forth in claim 13, wherein in said forming of said second opening, said second opening is formed by photolithography method, andin said forming of said first opening, said first opening is formed by laser processing.

15. The method of manufacturing an interconnect substrate as set forth in claim 13, wherein, in said forming of said first layer, a non-photosensitive insulating film is bonded, as said first layer, onto said supporting substrate through an intermediary of an insulating adhesive.

16. A method of manufacturing a semiconductor device, comprising: forming a first layer constructed with a non-photosensitive insulating material on a supporting substrate;forming a first electrode pad on said first layer;forming an interconnect and an insulating layer covering said interconnect on said first electrode pad;forming a second electrode pad on said insulating layer;forming a second layer constructed with a photosensitive insulating material so as to cover said second electrode pad;forming a second opening in said second layer so that said second electrode pad is exposed;removing said supporting substrate after forming said second opening;forming a first opening in said first layer after removing said supporting substrate so that said first electrode pad is exposed, said first opening having an opening area smaller than that of said second opening; andconnecting a semiconductor chip to said first electrode pad that is exposed to said first opening.