Patent Application
20130105329
The invention relates to the formation of solder deposits by electroplating, particularly to flip chip packages, more particularly to flip chip joints and board to board solder joints formed by electroplated metal or metal alloys.
Since the introduction of the flip chip technology by IBM in the early 1960s, the flip chip devices have been mounted on an expensive ceramic substrate where the thermal expansion mismatch between the silicon chip and the ceramic substrate is less critical. In comparison with wire bonding technology, the flip chip technology is better able to offer higher packaging density (lower device profile) and higher electrical performance (shorter possible leads and lower inductance). On this basis, the flip chip technology has been industrially practiced for the past 40 years using high-temperature solder (controlled-collapse chip connection, C4) on ceramic substrates. However, in recent years, driven by the demand of high-density, high-speed and low-cost semiconductor devices for the trend of miniaturization of modern electronic products, the flip chip devices mounted on a low-cost organic circuit board (e.g. printed circuit board or substrate) with an epoxy underfill to mitigate the thermal stress induced by the thermal expansion mismatch between the silicon chip and organic board structure have experienced an obviously explosive growth. This notable advent of low-temperature flip chip joints and organic-based circuit board has enabled the current industry to obtain inexpensive solutions for fabrication of flip chip devices.
In the current low-cost flip chip technology, the top surface of the semiconductor integrated circuit (IC) chip has an array of electrical contact pads. The organic circuit board has also a corresponding grid of contacts. The low-temperature solder bumps or other conductive adhesive material are placed and properly aligned in between the chip and circuit board. The chip is flipped upside down and mounted on the circuit board, in which the solder bumps or conductive adhesive material provide electrical input/output (I/O) and mechanical interconnects between the chip and circuit board. For solder bump joints, an organic underfill encapsulant may be further dispensed into the gap between the chip and circuit board to constrain the thermal mismatch and lower the stress on the solder joints.
In general, for achieving a flip chip assembly by solder joints, the metal bumps, such as solder bumps, gold bumps or copper bumps, are commonly pre-formed on the pad electrode surface of the chip, in which the bumps can be any shape, such as stud bumps, ball bumps, columnar bumps, or others. The corresponding solder bumps (or say presolder bumps), typically using a low-temperature solder, are also formed on the contact areas of the circuit board. At a reflow temperature, the chip is bonded to the circuit board by means of the solder joints. After dispensing of an underfill encapsulant, the flip chip device is thus constructed. Such methods are well known in the art and typical examples of the flip chip devices using solder joints are for example described in U.S. Pat. No. 7,098,126.
Currently, the most common method for formation of presolder bumps on the circuit board is the stencil printing method. Some prior proposals in relation to the stencil printing method can be referred to U.S. Pat. No. 5,203,075, U.S. Pat. No. 5,492,266 and U.S. Pat. No. 5,828,128. Solder bumping technique for flip chip assemblies requires design considerations regarding both bump pitch and size miniaturization. According to practical experiences, the stencil printing will become infeasible once the bump pitch is decreased below 0.15 millimeter. In contrast, the solder bumps deposited by electroplating offer the ability to further reduce bump pitch down to below 0.15 millimeter. The prior proposals in relation to electroplate bumps on the circuit board for flip chip bonding can be found in U.S. Pat. No. 5,391,514 and U.S. Pat. No. 5,480,835. Although electroplate solder bumping on the circuit board offers finer bump pitch over stencil printing, it presents several challenges for initial implementation.
A multi-step process to form solder on an organic substrate is described in U.S. Pat. No. 7,098,126. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact area. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer is formed over the metal seed layer and then patterned. A solder material is then formed in the opening by electroplating. Finally, the resist and the metal seed layer beneath the resist are removed. To apply this method various patterning steps are required which is not desired from the overall standpoint of process efficiency. Each patterning step is a potential cause of mismatched patterns. Furthermore the method has its limitations if the distance between adjacent contact areas (pitch) is very small as a result of the miniaturization of electronic devices.
A fabrication method of conductive bump structures of circuit boards is disclosed in US 2006/0219567 A1. A solder material is electroplated onto the substrate which is partially protected by a patterned solder mask. Next, an etch resist is deposited onto the layer of solder material. The etch resist is then patterned in a way that the solder material coated connecting pads are protected during the following etching step. Solder material which is not needed for the solder depots is then etched away leaving only the etch resist protected solder depot above the connecting pads. Next, the etch resist is removed.
The European patent application EP 2 180 770 A1 discloses a method formation of solder deposit layers wherein a solder resin layer is deposited onto a substrate having contact areas. Said solder resin layer is patterned in order to expose said contact areas. Next, an additional resin layer is deposited onto the patterned solder resin layer and again patterned. This method can lead to a misalignment of the individually patterned solder resin layer and additional resin layer in case of small contact area size and narrow pitch distance.
It is therefore an objective of the present invention to adopt an electroplating method of tin and tin alloys to produce a uniform layer of a solder deposit on a substrate and a tin plating bath composition suitable therefore. Such plating methods should be suitable to fill recess structures possessing high aspect ratios without leaving voids or dimples.
Another object of the present invention is to provide non-melting bump structures.
Another object of the present invention is to provide a method for solder deposition and formation of non-melting bump structures having a reduced number of plating steps and which is universally applicable even when the solder resist openings have different dimensions.
Another object of the present invention is to provide a method for solder deposit and non-melting bump structure formation which avoids pattern misalignment.
In summary, a method of fabricating electroplate solder deposits and non-melting bump structures on a substrate for forming flip chip joints and board to board solder joints is disclosed. According to the present invention, there is provided a non-conductive substrate like a circuit board including at least one contact area.
A substrate having at least one contact area which is covered by a permanent resin layer are coated with a temporary resin layer. Contact area openings are generated in the substrate by methods such as laser drilling, plasma etching, spark erosion and mechanical drilling in order to expose the at least one contact area.
Next, a layer containing a metal or metal alloy is then plated on the conductive areas of the substrate to form a solder deposit or a non-melting bump structure.
The invention provides a method of forming a metal layer on a substrate by electroplating a metal or metal alloy layer. The process is particularly suitable for fabricating solder bumps and non-melting bump structures on a circuit board having a good plating uniformity. The method is in more detail described below. The figures shown herein are simply illustrative of the process. The figures are not drawn to scale, i.e. they do not reflect the actual dimensions or features of the various layers in the chip package structure. Like numbers refer to like elements throughout the description.
Now referring to
The at least one contact area (101) is typically formed from a metal material, such as copper. Optionally, a first barrier layer is formed on the at least one contact area (101) and can e.g. be an adhesive layer of nickel, nickel alloys or a protective layer of gold. Said first barrier layer may also be made of nickel, chromium, titanium, silver, gold, palladium, alloys thereof and multi layers thereof which can be made by electroplating, electroless plating, physical vapor deposition or chemical vapour deposition.
The at least one contact area (101) is covered by at least one permanent resin layer (103) which is preferably made of organic material or a fiber-reinforced organic material or a particle-reinforced organic material, etc., for example, epoxy resin, polyimide, bismeleimide triazine, cyanate ester, polybenzocyclobutene, or glass fiber composite thereof, etc.
In one embodiment of the present invention the permanent resin layer (103) is a solder resin layer.
Next, at least one temporary resin layer (104) is deposited onto the at least one permanent resin layer (103) (
The temporary resin layer (104) may be selected from a polymer material selected from one or more of acrylates, ethylene/ethylacrylate copolymer (EEAC), ethylene/methacrylate copolymer (EMA), ethylene/acrylic acid copolymer (EAA), ethylene/butylacrylate copolymer (EBA), polymethylpentene (PMP) and polymethylmethacrylate (PMMA).
More preferred polymer materials for the temporary resin layer (104) are selected from the group consisting of acrylates, and polymethylpentene.
Most preferred polymer material for the temporary resin layer (104) are acrylates with a molecular weight Mw of 20000-200000, more preferred 25000-15000, and most preferred 30000-100000. The Tg of the polymer shall be in the range of 20-130° C., more preferred 30-120° C., and most preferred 40-110° C., as measured according to ISO11357-1.
A molecular weight too high will lead to reduced solubility in the chosen solvent. With a molecular weight too low, the sensitivity to the process solutions (alkaline, oxidizing, acidic) tends to be insufficient. The Tg must also not be too low because in this case the sensitivity to the polymer film is insufficient at the elevated temperature of the processing chemicals.
Optionally, fillers can be incorporated into the polymeric material of the temporary resin layer (104). Suitable fillers are selected from the group consisting of, aluminium borate, aluminium oxide, aluminiumtrihydroxide, anthracite, sodium antimonate, antimony pentoxide, antimony trioxide, apatite, attapulgite, barium metaborate, barium sulfate, strontium sulfate, barium titanate, bentonite, beryllium oxide, boron nitride, calcium carbonate, calcium hydroxide, calcium sulfate, carbon black, clay, cristobalite, diatomaceous earth, dolomite, ferrites, feldspar, glass beads, graphite, hydrous calcium silicate, iron oxide, kaolin, lithopone, magnesium oxide, mica, molybdenum disulfide, perlite, polymeric fillers such as PTFE, PE, polyimide, pumice, pyrophyllite, rubber particles, fumed silica, fused silica, precipitated silica, sepiolite, quartz, sand, slate flour, talc, titanium dioxide, vermiculite, wood flour, wollastonite, zeolithes, zinc borate, zinc oxide, zinc stannate, zinc sulfide, aramid fibers, carbon fibers, cellulose fibers, and glass fibers and mixtures thereof.
Preferred optional filler materials for the temporary resin layer (104) are selected from the group consisting of fused silica, fumed silica, precipitated silica, dolomite, kaolinite, talc, calcium carbonate, mica, feldspar, vermiculite, and pumice.
Most preferred optional filler materials for the temporary resin layer (104) are selected from the group consisting of kaolinite, talc, mica, and feldspar.
The amount of filler in the overall formulation after removal of the solvent is in the range of 1-70% by weight, more preferably 2-65% by weight, most preferably 3-60% by weight.
The temporary resin layer (104) can be deposited onto the permanent resin layer (103) in form of a liquid by methods such as dip coating, spin coating, bar coating, spraying, screen printing, and roller coating. In another embodiment a dry film on a carrier foil is first made from the liquid resin and this dry film is then laminated on the permanent resin layer (103). Such a carrier foil is required because the polymer materials used later on as the temporary resin layer (104) can not be manufactured as a foil. The preferred method for depositing the temporary resin layer (104) onto the permanent resin layer (103) are roller coating of the liquid resin, screen printing of the liquid resin, dipping of the substrate, or lamination of the respective dry film (consisting of the dry dilm and a carrier foil) onto the substrate. Most preferred are screen printing of the liquid resin, roller coating of the liquid resin, and lamination of a respective dry film (consisting of the dry dilm and a carrier foil) onto the substrate.
Depending on the solvent which was employed for formulating the lacquer, the oven temperature and the drying time have to be adjusted. Important is the resulting hardness of the dried coating. Measurement of the hardness according to Koenig should be in the range of 20 seconds to 200 seconds, more preferred 40 seconds to 180 seconds, most preferred 60 seconds to 160 seconds.
The temporary resin layer (104) can be removed (stripped) from the permanent resin layer (103) by contacting the temporary resin layer (104) with a solvent without damaging the permanent resin layer (103), the solvent selected from the group comprising acetone, n-amylalcohol, n-amylacetate, benzyl alcohol, 1,4-butanediol, methoxybutyl acetate, n-butylacetate, sec-butyl acetate, n-butanol, 2-butanol, butyldiglycol, butyldiglycol acetate, diethyleneglycol dibutylether, butylglycol, butylglycol acetate, n-butyltriglycol, chloroform, cyclohexane, cyclohexanol, cyclohexanone, cyclohexylamine, n-decane, decahydro naphthalene, diacetone alcohol, 1,2-dichloroethane, 1,2-dichlorobenzene, 1,2-dichloropropane, diethanolamine, diethylene glycol, diethyleneglycol dibutylether, diethyleneglycol diethylether, diethyleneglycol dimethylether, diethyleneglycol monobutylether, diethyleneglycol monobutylether acetate, diethyleneglycol monoethylether, diethyleneglycol monomethylether, diethyleneglycol momethylether acetate, diethylether, diethylketone, diethyleneglycol dimethylether, diisobutylketone, diisopropylamine, diisopropanolamine, diisopropylether, dimethylacetamide, dimethylformamide, dimethylsulfoxide, 1,4-dioxane, dipentene, dipropyleneglycol, dipropyleneglycol monobutylether, dipropyleneglycol monomethylether, n-dodecane, propyleneglycol diacetate, propyleneglycol monomethylether, propyleneglycol monomethylether acetate, propyleneglycol monobutylether, propyleneglycol monobutylether acaetate, tripropyleneglycol monomethylether, tripropyleneglycol monobutylether, ethyl-3-ethoxypropionate, ethanolamine, propyleneglycol monoethylether, ethoxypropyl acetate, ethylacetate, ethaylamylketone, ethylbenzene, 2-ethylbutanol, ethylbutyl ketone, ethyldiglycol, ethyldiglycol acetate, 1,2-dichloroethane, ethyleneglycol, ethyleneglycol dietheylether, ethyleneglycol dimethylether, ethyleneglycol monobutylether, ethyleneglycol monobutylether acetate, ethyleneglycol monoethylether, ethyleneglycol monoethylether acetate, ethyleneglycol monoisopropylether, ethyleneglycolmonomethylether, ethyleneglycol monomethylether acetate, ethyleneglycol monopropylether, ethylformiate, ethylglycol, ethylglycol acetate, ethyleneglycol dietehylether, 2-ethoxyethanol, 2-ethylhexyl acetate, ethyllactate, ethylmethylketone, formic acid, ethylmethylketoxime, ethyltriglycol, furfurol, furfurylalcohol, furfurylaldehyde, glycerol, glycerol triacetate, n-heptane, n-hexadecane, n-hexane, hexylene glycol, isoamylacetate, isoamylalcohol, isobutylacetate, isobutylalcohol, isoheptane, isooctane, isopentane, isophorone, isopropanolamine, isopropylacetate, isopropylalcohol, isopropylchloride, isopropylether, isopropylglycol, methoxypropyl acetate, methylacetate, methyl alcohol, methylamylketone, methylbutylketone, methylcyclohexane, methylcyclohexanol, methylcyclohexanone, methylcyclopentane, methyldiglycol, methyldiglycol acetate, methylenechloride, acetic acid, methylethylketone, methylethyl ketoxime, methylglycol, methylglycol acetate, methylisoamylalcohol, methylisoamylketone, methylisobutylcarbinol, methylisobutylketone, methylisopropylketone, methylpropylketone, N-methylpyrrolidone, methyl-t-butylether, monochlorobenzene, monoethanolamine, monoisopropanolamine, nitroethane, nitromethane, 1-nitropropane, 2-ntropropane, n-nonane, n-octane, n-octylalcohol, n-pentadecane, pentylpropionate, perchloroethylene, n-propylacetate, n-propanol, propylenedichloride, propyleneglycol, propyleneglycol diacetate, propyleneglycol monobutylether, propyleneglycol monobutyletheracetate, propyleneglycol monoethylether, propyleneglycol monomethylether, propyleneglycol monomethylether acetate, propylglycol, pyridine, sec-butylacetate, n-tetradecane, tetraethyleneglycol, tetraethyleneglycol dimethylether, tetrahydrofurane, tetrahydrofurfurylalcohol, tetrahydro naphthalene, toluene, trichloroethane, trichloroethylene, n-tridecane, triethanolamine, triethyleneglycol, triethethyleneglycol monoethylether, triethyleneglycol dimethylether, tripropyleneglycol, hydrogenperoxide, tripropylengylcol monobutylether, tripropyleneglycol monomethylether, n-undecane, xylene, mesitylene, acetophenone, acetaldehyde, butyrolactone, ethylenecarbonate, propylenecarbonate, acetonitrle, butyronitrile, N-ethylpyrrolidone, and mixtures thereof. Mixtures of the aforementioned solvents may further comprise water.
More preferably, the solvent is selected from the group consisting of benzyl alcohol, formic acid, dimethylacetamide, dimethylformamide, cyclohexanone, ethanolamine, triethanolamine, ethyleneglycol monobutylether acetate, ethyleneglycol monoethylether, and mixtures thereof.
Most preferably, the solvent is selected from the group consisting of formic acid, benzyl alcohol, ethyleneglycol monobutylether acetate, ethyleneglycol monoethylether and mixtures thereof.
The temporary resin layer (104) is contacted with the solvent by immersion, spraying, or dipping. For stripping purpose, the solvent is held at a temperature in the range of 5 to 100° C., more preferably 10 to 90° C. and most preferably 15 to 80° C. The contact time during stripping ranges from 1 to 600 seconds, more preferably from 10 to 540 seconds and most preferably from 20 to 480 seconds. During stripping, the permanent resin layer (104) is not damaged.
At least one contact area opening (105) is formed in the next step (
The main advantage of said “multi layer drilling” method is that no misalignment of the openings in the permanent resin layer (103) and the temporary resin layer (104) can occur. Such misalignment of openings is a severe problem, especially for opening diameters of ≦150 μm, when applying methods known on the art. In known methods the contact pad openings are formed in two separate steps (
In order to fabricate a metal or metal alloy layer (107) by electroplating on a non-conductive surface (102), a conductive seed layer formed on the non-conductive surface is required to initiate the electroplating. Such a first conductive seed layer (106) is depicted in
According to the present invention the first conductive seed layer (106) is deposited over the entire surface of the non-conductive substrate (102) including the at least one contact area (101), the permanent resin layer (103) and the temporary resin layer (104) (
The non-conductive substrates can be activated by various methods which are described, for example, in Printed Circuits Handbook, C. F. Coombs Jr. (Ed.), 6th Edition, McGraw Hill, pages 28.5 to 28.9 and 30.1 to 30.11. These processes involve the formation of a conductive layer comprising carbon particles, Pd colloids or conductive polymers.
Some of these processes are described in the patent literature and examples are given below:
European patent EP 0 616 053 describes a process for applying a metal coating to a non-conductive substrate (without an electroless coating) comprising:
This process results in a thin conductive layer which can be used for subsequent electroplating. This process is known in the art as the “Connect” process.
U.S. Pat. No. 5,503,877 describes the metallisation of non-conductive substrates involving the use of complex compounds for the generation of metal seeds on a non-metallic substrate. These metal seeds provide for sufficient conductivity for subsequent electroplating. This process is known in the art as the so-called “Neoganth” process.
U.S. Pat. No. 5,693,209 relates to a process for metallisation of a non-conductive substrate involving the use of conductive pyrrole polymers. The process is known in the art as the “Compact CP” process.
EP 1 390 568 B1 also relates to direct electrolytic metallisation of non-conductive substrates. It involves the use of conductive polymers to obtain a conductive layer for subsequent electrocoating. The conductive polymers have thiophene units. The process is known in the art as the “Seleo CP” process.
Finally, the non-conductive substrate can also be activated with a colloidal or an ionogenic palladium ion containing solution, methods for which are described, for example, in Printed Circuits Handbook, C. F. Coombs Jr. (Ed.), 6th Edition, McGraw Hill, pages 28.9 and 30.2 to 30.3.
Subsequent electroless plating of a thin intermediate metal coating can optionally been carried out in order to enhance the first conductive seed layer (106). With assistance of the seed layer, electroplating of the metal or metal alloy layer (107) according to the present invention can then be carried out.
According to the present invention, said first conductive seed layer (106) may be made of a single metal layer, a single metal alloy layer or made of multilayer of at least two distinct single layers. Metals and metal alloys suitable as conductive seed layer are selected from the group consisting of copper, tin, cobalt, nickel, silver, tin-lead alloy, tin-silver alloy, copper-nickel alloy, copper-chromium alloy, copper-ruthenium alloy, copper-rhodium alloy, copper-silver alloy, copper-iridium alloy, copper-palladium alloy, copper-platinum alloy, copper-gold alloy and copper-rare earth alloy, copper-nickel-silver alloy, copper-nickel-rare earth metal alloy. Copper and copper alloys selected from the group consisting of copper-nickel alloys, copper-ruthenium alloys and copper-rhodium alloys are most preferred as a first conductive seed layer (106).
In accordance with a preferred embodiment of the present invention, said first conductive seed layer (106) can also be formed by an electroless plating method, wherein the catalytic metal does not use noble metal but uses copper as the catalytic metal. The typical examples for forming such a catalytic copper on a non-conductive surface can be found in the U.S. Pat. No. 3,993,491 and U.S. Pat. No. 3,993,848.
The thickness of said first conductive seed layer (106) preferably is less than 0.1 millimeter and more preferably between 0.0001 millimeter and 0.005 millimeter. Depending on the solubility of said first conductive seed layer (106) in the metal or metal alloy layer (107), said first seed layer (106) can either completely dissolve into the metal or metal alloy layer (107) or still at least partially exist after the reflow process.
Optionally, a layer of silver or a silver alloy is plated onto the metal or metal alloy layer (107) as a protection layer (117).
In case the metal or metal alloy layer (107) is a tin or tin alloy layer, a reflowed solder deposit (108) or a non-melting bump structure (112) can be obtained from layer (107) depending on the thickness of the first conductive seed layer (106) and the amount of first conductive seed layer (106) dissolved in the metal or metal alloy layer (107) when reflowing.
A reflowed solder deposit (108) is obtained from a metal or metal alloy layer (107) consisting of tin or a tin alloy having a melting point of less than 250° C. when reflowing.
A non-melting bump structure (112) is obtained from either a metal or metal alloy layer (107) consisting of a tin alloy layer having a melting point of more than 250° C. when reflowing or from a copper or a copper alloy deposited as the metal or metal alloy layer (107).
A thinner first conductive seed layer (106) is preferred, since a thinner seed layer can be removed sooner in the etching solution, the time required for said non-conductive substrate (102) immersed in an etching solution could be shortened. In such a case, the damages to said temporary resin layer (104) by said etching solution will be lowered down to an acceptable low level.
Referring now to
In accordance with a preferred embodiment of the present invention, said metal or metal alloy layer (107) is selected from the group consisting of tin, copper, a tin alloy made by the mixture of tin and the elements selected from the group consisting of lead, silver, copper, bismuth, antimony, zinc, nickel, aluminium, magnesium, indium, tellurium, gallium and rare earth elements, and a copper alloy with the at least one alloying element selected from the group consisting of vanadium, chromium, manganese, iron, cobalt, nickel, zink, germanium, selenium, rhodium, palladium, silver, cadmium, indium, tin, antimony, tungsten, rhenium, iridium, platinum, gold, lead, bismuth, thallium and rare earth elements
Tin and tin alloy plating baths are known in the art. Commonly used tin or tin alloy plating bath compositions and process parameters for plating are described in the following.
Among other components of the tin or tin alloy bath may be added a source of Sn2+ ions, an anti-oxidant, and a surfactant.
The source of Sn2+ ions may be a soluble tin-containing anode, or, where an insoluble anode is used, a soluble Sn2+ ion source. Tin methane sulfonic acid, Sn(MSA)2, is a preferred source of Sn2+ ions because of its high solubility. Typically, the concentration of the source of Sn2+ ions is sufficient to provide between about 10 g/l and about 100 g/l of Sn2+ ions into the bath, preferably between about 15 g/l and about 95 g/l, more preferably between about 40 g/l and about 60 g/l. For example, Sn(MSA)2 may be added to provide between about 30 g/l and about 60 g/l Sn2+ ions to the plating bath.
A preferred tin alloy is tin silver alloy. In such case the plating bath additionally contains a soluble silver salt, commonly used are nitrate, acetate, and preferably methane sulfonate. Typically, the concentration of the source of Ag+ ions is sufficient to provide between about 0.1 g/l and about 1.5 g/l of Ag+ ions into the bath, preferably between about 0.3 g/l and about 0.7 g/l, more preferably between about 0.4 g/l and about 0.6 g/l. For example, Ag(MSA) may be added to provide between about 0.2 g/l and about 1.0 g/l Ag+ ions to the plating bath.
Anti-oxidants may be added to the baths of the present invention to stabilize the bath against oxidation of Sn2+ ions in solution. Preferred anti-oxidants such as hydroquinone, catechol, and any of the hydroxyl, dihydroxyl, or trihydroxyl benzoic acids may be added in a concentration between about 0.1 g/l and about 10 g/l, preferably between about 0.5 g/l and about 3 g/l. For example, hydroquinone may be added to the bath at a concentration of about 2 g/l.
Surfactants may be added to promote wetting of the substrate. The surfactant seems to serve as a mild deposition inhibitor which can suppress three-dimensional growth to an extent, thereby improving morphology and topography of the film. It can also help to refine the grain size, which yields a more uniform bump. Exemplary anionic surfactants include alkyl phosphonates, alkyl ether phosphates, alkyl sulfates, alkyl ether sulfates, alkyl sulfonates, alkyl ether sulfonates, carboxylic acid ethers, carboxylic acid esters, alkyl aryl sulfonates, aryl alkylether sulfonates, aryl sulfonates, and sulfosuccinates.
The electrolytic tin or tin alloy plating bath of the present invention preferably has an acidic pH to inhibit anodic passivation, achieve better cathodic efficiency, and achieve a more ductile deposit. Accordingly, the bath pH is preferably between about 0 and about 3. In the preferred embodiment the pH of the bath is 0. Accordingly, the preferred acidic pH can be achieved using nitric acid, acetic acid, and methane sulfonic acid. In one preferred embodiment, the acid is methane sulfonic acid. The concentration of the acid is preferably between about 50 g/l and about 200 g/l, more preferably between about 70 g/l and about 120 g/l. For example, between about 50 g/l and about 160 g/l methane sulfonic acid can be added to the electroplating bath to achieve a bath of pH 0 and act as the conductive electrolyte.
Typical tin or tin alloy bath compositions are for example disclosed in: Jordan: The Electrodeposition of Tin and its Alloys, 1995, p. 71-84.
The plating of tin and tin alloys for solder depot plating can be performed by direct current (DC) or pulse plating. The advantages of pulse plating are better surface distribution uniformity and improved crystal structures with tin deposits possessing finer grain sizes and therefore better solderability properties. Also, higher applicable current density and therefore higher throughput can be obtained by pulse plating compared to DC plating.
Generally, current pulses at an effective current density of 1-20 A/dm2 can be applied. Alternatively, operating of the bath with DC at a current density of 1-3 A/dm2 can be performed.
For example, applying a tin pulse plating with a current density of 3 A/dm2 yields an average thickness of the tin deposit of 40 μm within 30 min, plating time. The thickness variation on the surface is only +/−15%. Applying DC plating a maximum current density of only 1 A/dm2 can be obtained. Plating time to obtain a thickness of the tin deposit of 40 μm is 86 min. The variation on the surface is +/−33%, thus much higher than for pulse plating.
Preferred pulse parameters are as follows:
The ratio of the duration of the at least one forward current pulse to the duration of the at least one reverse current pulse is adjusted to at least 1:0-1:7, preferably to at least 1:0.5-1:4 and more preferably to at least 1:1-1:2.5.
The duration of the at least one forward current pulse can be adjusted to preferably at least 5 ms to 1000 ms.
The duration of the at least one reverse current pulse is preferably adjusted to 0.2-5 ms at most and most preferably to 0.5-1.5 ms.
The peak current density of the at least one forward current pulse at the workpiece is preferably adjusted to a value of 1-30 A/dm2 at most. Particularly preferable is a peak current density of the at least one forward current pulse at the workpiece of about 2-8 A/dm2 in horizontal processes. In vertical processes the most preferred peak current density of the at least one forward current pulse at the workpiece is 1-5 A/dm2 at most.
The peak current density of the at least one reverse current pulse at the work piece will preferably be adjusted to a value of 0-60 A/dm2. Particularly preferred is a peak current density of the at least one reverse current pulse at the workpiece of about 0-20 A/dm2 in horizontal processes. In vertical processes the most preferred peak current density of the at least one forward current pulse at the workpiece is 0-12 A/dm2 at most.
Copper and copper alloy plating baths are known in the art. Commonly used copper or copper alloy plating bath compositions and process parameters for plating can be applied.
In a preferred embodiment of the present invention said first conductive seed layer (106) is made of copper and the metal or metal alloy layer (107) consists of tin or a tin alloy. During reflow operations said first conductive seed layer (106) is completely dissolved into the tin layer (107) forming a reflowed solder deposit layer (108) which consists of a homogeneous tin-copper alloy (
In case of a higher thickness of a first conductive seed layer (106) made of copper, dissolution of said conductive seed layer into the tin layer (107) leads to a tin-copper alloy having a melting point above 250° C. Such a tin-copper alloy is a non-melting bump structure (112) (
In another preferred embodiment of the present invention said first conductive seed layer (106) consists of copper or a copper alloy and the metal or metal alloy layer (107) consists of copper. This combination also leads to a non-melting bump structure (112) (melting point above 250° C.).
The openings in the structures according to the
The height of the contact area openings (105) varies between 5-250 μm, preferably of about 10-60 μm. The distance of the center points of adjacent contacts areas is denoted as pitch and ranges from 20-150 μm for IC substrates, and from 150-1.000 μm for printed circuits.
Since also the temporary resin layer (104) is covered by a first conductive seed layer (106) plating of the metal or metal alloy layer (107) is also on this layer. The thickness of such a metal or metal alloy layer (107) should preferably not exceed 10 μm and more preferred not exceed 6 μm on top of the temporary resin layer (104).
While this process sequence has been described in detail for a substrate according to
One method for depositing a solderable cap layer (113) or a barrier layer onto the top of the metal or metal alloy layer (107) comprises deposition of a solderable cap layer (113) or a barrier layer directly after removal of the temporary resin layer (104) (
Another method for depositing a solderable cap layer (113) or a barrier layer onto the top surface of a non-melting bump structure (112) is shown in
A substrate obtained by the method according to claim 1 is provided (
A resist layer (114) is deposited onto the surface of the substrate and patterned. The top surface of the metal or metal alloy layer (107) is then exposed (
Next, a layer of a metal or metal alloy selected from the group consisting of tin, nickel, chromium, titanium, silver, gold, palladium, alloys thereof and multi layers thereof is deposited into the openings formed by the patterned resist layer (114) (
The patterned resist layer (114) is stripped by methods known in the art. The conductive seed layer (106) on top of the temporary resin layer (104) and the metal or metal alloy layer (107) are removed from the first conductive seed layer (106) (
The term “etch resist” is defined herein as any kind of patterned barrier, e.g., photo imageable or screen printed organic resists and metal etch resists which prevents undesired removal of material beneath said etch resist during etching.
The removal preferably is performed by chemical etching an amount of the metal or metal alloy layer (107) sufficient to remove the metal or metal alloy layer (107) from the first conductive seed layer (106) leaving a metal or metal alloy layer (107) on the at least one contact area (101) in the openings (105).
In case the metal or metal alloy layer (107) consists of tin and tin alloys the etching can be performed electrolytically or chemically. Also, mechanical polishing may be applied alone or in combination with electrolytical or chemical stripping to remove the metal or metal alloy layer (107).
Typical etching or stripping compositions for metal or metal alloy layers (107) consisting of tin or tin alloys are for example disclosed in: Jordan: The Electro-deposition of Tin and its Alloys, 1995, p. 373-377.
During electrolytic stripping methods tin or its alloys are anodically dissolved in a 10 wt-% NaOH solution at 70-90° C.
Chemical stripping generally is performed in solutions containing a strong base like NaOH (about 10 wt-%) at elevated temperatures of 70-90° C. Organic additives, particularly, nitroaromtic compounds like p-nitrophenol, may be added to the solution.
Alternatively, chemical stripping can be performed in the following solutions:
In case the metal or metal alloy layer (107) consists of copper and copper alloys the etching can be performed electrolytically or chemically. Also, mechanical polishing may be applied alone or in combination with electrolytical or chemical stripping to remove the metal or metal alloy layer (107).
Typical etching or stripping compositions for metal or metal alloy layers (107) consisting of copper or copper alloys and a first conductive seed layer (106) consisting of copper or a copper alloy are for example disclosed in: C. F. Coombs, Jr, “Printed Circuits Handbook”, 5th Ed. 2001, McGraw-Hill, Chapter 33.4.
Suitable etching solutions and etching conditions are chosen in routing experiments.
Optionally, a layer of silver or a silver alloy is plated onto the solderable cap layer (113) as a protection layer (117).
Still another method for depositing a solderable cap layer (113) or a barrier layer (115) onto the top surface of a non-melting bump structure (112) is shown in
A substrate obtained by the method according to claim 1 is provided (
The metal or metal alloy layer (107) is removed from the first conductive seed layer (106) by etching without use of an etch resist (
A resist layer (114) is deposited onto the surface of the substrate and patterned. The top surface of the metal or metal alloy layer (107) is exposed (
Next, a layer of a metal or metal alloy selected from the group consisting of tin, nickel, chromium, titanium, silver, gold, palladium, alloys thereof and multi layers thereof is deposited into the openings formed by the patterned resist layer (114) (
The patterned resist layer (114) is stripped by methods known in the art. The conductive seed layer (106) on top of the temporary resin layer (104) is removed as described above, followed by stripping of the temporary resin layer (104) (
The non-melting bump structure (112) has now a solderable cap layer (113) or a barrier layer on the top surface.
Still another method for depositing a solderable cap layer (113) onto the top surface of a non-melting bump structure (112) is shown in
Provided is a substrate according to
The first conductive seed layer (106) is removed by etching (
Next, a barrier layer (115) is deposited onto the top of the metal or metal alloy layer (107) (
A second conductive seed layer (116) is deposited onto the outer surface of the temporary resin layer (104) and the barrier layer (115) (
Next, a layer of tin or a tin alloy serving later as the solderable cap layer (113) is deposited onto the second conductive seed layer (116) (
Thereafter, the solderable cap layer (113) is removed from those portions of the second conductive seed layer (116) which are on top of the temporary resin layer (104). No additional etch resist is applied onto the solderable cap layer (113) above the at least one contact area (101) prior to removal of the solderable cap layer (113) and from the outer surface of the second conductive seed layer (116). Also removed are the second conductive seed layer (116) and the temporary resin layer (104) leaving the bump structures comprising a non-melding bump, a barrier layer (115) and the solderable cap layer (113) (
Optionally a layer of silver or a silver alloy is plated onto the solderable cap layer (113) as a protection layer (117). The following example further illustrates the present invention.
At a reflow temperature, either a reflowed solder deposit (108) (
In accordance with a preferred embodiment of the present invention, reflowed solder deposits (108) can be formed by further removing the first conductive seed layer (106) from the temporary resin layer (104) and stripping the temporary resin layer (104). Such reflowed solder deposits (
The reflowed solder deposits (108) can be any shape, such as stud bumps, ball bumps, columnar bumps, or others.
Non-melting bump structures (112) are manufactured with the same method as applied for the manufacture of reflowed solder deposits (108). During reflowing the conductive seed layer can be dissolved partially or completely in the non-melting bump structure (112) (
Non-melting bump structures (112) can be used for forming flip chip joints and board to board solder joints with or without depositing a solderable cap layer (113). In case of a solderable cap layer this would be done preferably by electroplating a solderable cap layer (113) on the top surface of said non-melting bump structure (112).
A barrier layer on top of a non-melting bump structure (112) prevents solder material from diffusing into the non-melting bump structure (112) during soldering and thereby maintains the thermal and mechanical properties of the non-melting bump structure (112).
An IC substrate is used having a contact pad structure according to
The non-conductive substrate (102) consists of GX-13 material (manufacturer: Ajinomoto Fine-Techno Co., Inc.), the permanent resin layer (103) consists of GX-92 material (manufacturer: Ajinomoto Fine-Techno Co., Inc., height of the layer: 25 μm) and the contact pads consist of copper.
A temporary resin layer (104) (DuPont PM 200, height: 50 μm) was laminated onto the permanent resin layer (103).
Next, contact area openings (105) are formed through the temporary resin layer (104) and the permanent resin layer (103) with a UV laser in one step. The diameter of the contact area openings (105) is 100 μm.
The plating sequence is according to
Thereafter, a tin layer (107) is plated on the conductive layer from a bath containing:
45 g/L Sn2+ as Sn(MSA)2, 60 mL/L MSA (70% solution), 2 g/L Hydroquinone and 100 mg/L benzal acetone.
The pH of the bath is 0, the temperature 25° C. Plating is for 15 min. Standard DC plating with a current density of 1 A/dm2 is applied.
The contact area openings (105) according to
The tin layer (107) on the temporary resin layer (104) area as well as the first conductive seed layer (106) are directly thereafter removed by treatment in a solution containing 30 vol.-% nitric acid at a temperature of 40° C. for 1 min.
After the etching process tin layer (107) only remains in the opening, while the tin layer (107) as well as the first conductive seed layer of copper (106) on the temporary resin layer (104) area have been entirely removed. Next, the temporary resin layer (104) is removed by immersing the substrate in an aqueous solution of 2 wt.-% potassium carbonate. The tin layer, i.e. the solder deposit shows a very homogenous surface distribution and is whisker free. It is suited to be soldered to a chip or circuit.
A non-melting bump structure (112) consisting of a tin-copper alloy with a solderable cap layer (113) made of tin was manufactured. An IC substrate is used having at least one contact area structure according to
The non-conducting substrate (102) consists of GX-13 material (manufacturer: Ajinomoto Fine-Techno Co., Inc.), the permanent resin layer (103) consists of GX-92 material (manufacturer: Ajinomoto Fine-Techno Co., Inc., height of the layer: 25 μm) and the contact pads (101) consist of copper.
A temporary resin layer (104) (DuPont PM 200, height: 50 μm) was laminated onto the permanent resin layer (103).
Next, contact area openings (105) are formed through the temporary resin layer (104) and the permanent resin layer (103) with a UV laser in one step. The diameter of the contact area openings (105) is 100 μm.
The plating sequence is according to
Thereafter, a tin layer (107) is plated on the first conductive seed layer (106) from a bath containing:
45 g/l Sn2+ as Sn(MSA)2, 60 ml/l MSA (70 wt.-% solution), 2 g/l Hydroquinone, a surfactant based on co-polymers and 100 mg/l benzal acetone.
The pH of the bath is 0, the temperature 25° C. Plating is for 15 min. Standard DC plating with a current density of 1 A/dm2 is applied.
The contact area openings (105) according to
The tin layer (107) on the first conductive seed layer (106) is thereafter removed by treatment in a solution containing 30 vol.-% nitric acid at a temperature of 40° C. for 1 min. No etch resist is applied. After the etching process the tin layer (107) only remains in the opening (105).
The resist layer (114) is removed in a stripping solution followed by etching away of the first conductive seed layer (106).
Next, the temporary resin layer (104) is removed by immersing the substrate in a stripping solution. The tin solder deposit shows a very homogenous surface distribution and is whisker free. R is suited to be soldered to a chip or circuit.
A non-melting bump structure (112) consisting of copper with a solderable cap layer (113) made of tin was manufactured.
An IC substrate comprising a non-conductive substrate (102), contact areas (101), a permanent resin layer (103) and a temporary resin layer (104) as used in Example 1 is provided.
Contact area openings (105) are formed through the temporary resin layer (104) and the permanent resin layer (103) with a UV laser in one step. The diameter of the contact area openings (105) is 100 μm. The plating sequence is according to
Thereafter, a copper layer (107) is electroplated onto the first conductive seed layer (106) from a bath containing: 45 g/l Cu2+ as CuSO4, 50 ml/l H2SO4, 1 ml/l brightener and 20 ml/l leveler additive. The pH of the bath is 0, the temperature 25° C. Plating is for 45 min. Standard pulse parameters with a average current density of 4 A/dm2 is applied.
The contact area openings (105) according to
Thereafter a resist layer (114) (DuPont PM 200) is laminated onto the copper layer (107) and patterned
Next, tin is electroplated from a plating bath composition comprising 45 g/l Sn2+ as Sn(MSA)2, 60 ml/l MSA (70 wt.-% solution), 2 g/l Hydroquinone, a surfactant based on co-polymers and 100 mg/benzal acetone to form a solderable low melting cap layer (113).
The resist layer (114) is stripped off in a standard dry film resist stripping solution.
The first conductive seed layer (106) and the copper layer (107) deposited onto the surface of the temporary resin layer (104) are thereafter removed from the surface of the temporary resin layer (104) by treatment in a solution containing 30 vol.-% nitric acid at a temperature of 40° C. for 1 min.
Next, the temporary resin layer (104) is removed by immersing the substrate in a stripping solution again.
The non melting pump and the solder cap deposit shows a very homogenous surface distribution and is whisker free. It is suited to be soldered to a chip or circuit with a sufficient stand off height.
An amount of 32 g of an acrylic resin with a Tg of 53° C. as measured according to ISO11357-1 and a viscosity number of 33 measured according to ISO1628-1 is dissolved in 45 g of a solvent which is suitable for screen printing formulations and having a boiling point of 180-200° C., under stirring (500-700 rpm) and heating at 80° C. When the solution has reached 80° C., 15 g of a layered filler and silicon containing additives are added which are needed to make the liquid formulation thixotropic and therefore suitable for screen printing applications. The mixture is stirred for 10 min and milled over a triple roll mill. The formulation thus obtained is screen printed on the permanent resin layer (103) and dried in a convection oven (Koenig hardness after drying: 100 s). The coating thus obtained can be dipped into an acidic solution (2.5% hydrochloric acid at 50° C., pH<1) for 5 minutes without damages. In the same way, it can be dipped into an alkaline solution (3% sodium hydroxide, 50° C., pH<13) with no damages. After both treatment in acid or base, the coating can be fully removed from the substrate by treatment with dimethylacetamide (50° C., 4 minutes). The permanent resin layer (103) beneath is not attacked under those conditions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10171612.4 | Aug 2010 | EP | regional |
| 11160014.4 | Mar 2011 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP11/63141 | 7/29/2011 | WO | 00 | 1/7/2013 |
