Semiconductor device and a method of manufacturing the same

Abstract

Wire connection failure in semiconductor device is prevented.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating one example of the structure of a semiconductor device according to Embodiment 1 of the present invention, which is illustrated through a sealing body;

FIG. 2 is a cross-sectional view illustrating one example of the structure of the semiconductor device illustrated in FIG. 1;

FIG. 3 is an enlarged fragmentary cross-sectional view illustrating the structure of the position A illustrated in FIG. 2;

FIG. 4 is an enlarged fragmentary cross-sectional view illustrating one example of the structure of a wire bonded portion illustrated in FIG. 3;

FIG. 5 is a cross-sectional view illustrating one example of the movement locus of the capillary at the time of wiring illustrated in FIG. 4;

FIG. 6 is a cross-sectional view illustrating one example of the movement locus of the capillary at the time of wiring illustrated in FIG. 4;

FIG. 7 is a cross-sectional view illustrating one example of the movement locus of the capillary at the time of wiring illustrated in FIG. 4;

FIG. 8 is a cross-sectional view illustrating one example of the movement locus of the capillary at the time of wiring illustrated in FIG. 4;

FIG. 9 is a plan view illustrating one example of a wiring pattern on the main surface side of a wiring substrate to be incorporated in the semiconductor device illustrated in FIG. 1;

FIG. 10 is a back side view illustrating one example of a wiring pattern on the back surface side of the wiring substrate illustrated in FIG. 9;

FIG. 11 is a cross-sectional view illustrating one example of the structure of the wiring substrate illustrated in FIG. 9;

FIG. 12 is an enlarged fragmentary cross-sectional view illustrating the structure of the position A illustrated in FIG. 11.

FIG. 13 is a flow chart of a manufacturing process illustrating one example of the fabrication steps up to resin molding in the fabrication of the semiconductor device illustrated in FIG. 1;

FIG. 14 is a flow chart of a manufacturing process illustrating one example of the fabrication steps after resin molding in the fabrication of the semiconductor device shown in FIG. 1;

FIG. 15 is a flow chart of a manufacturing process illustrating a modification example of the fabrication steps after resin molding in the fabrication of the semiconductor device illustrated in FIG. 1;

FIG. 16 is a plan view illustrating a wiring pattern on the main surface side of a wiring substrate in the modification example of Embodiment 1 of the present invention;

FIG. 17 is a back side view illustrating a wiring pattern on the back surface side of the wiring substrate illustrated in FIG. 16;

FIG. 18 is a cross-sectional view illustrating the structure of the wiring substrate illustrated in FIG. 16;

FIG. 19 is an enlarged fragmentary view illustrating the structure of the position A illustrated in FIG. 18;

FIG. 20 is a plan view illustrating a wiring pattern on the main surface side of a wiring substrate of another modification example of Embodiment 1 of the present invention;

FIG. 21 is a cross-sectional view illustrating the structure of the wiring substrate illustrated in FIG. 20;

FIG. 22 is an enlarged fragmentary cross-sectional view illustrating the structure of the portion A illustrated in FIG. 21;

FIG. 23 is a plan view illustrating, through a sealing body, one example of the structure of a semiconductor device according to Embodiment 2 of the present invention;

FIG. 24 is a cross-sectional view illustrating one example of the structure of the semiconductor device illustrated in FIG. 23;

FIG. 25 is an enlarged fragmentary cross-sectional view illustrating the structure of the position A shown in FIG. 24;

FIG. 26 is an enlarged fragmentary cross-sectional view illustrating the structure of the position B shown in FIG. 24.

FIG. 27 is an enlarged fragmentary cross-sectional view illustrating one example of a capillary pressed against a bonding lead during wire bonding in Comparative Example; and

FIG. 28 is a cross-sectional view illustrating the connection failure after wire bonding in Comparative Example.

Claims

1. A semiconductor device, comprising: a wiring substrate having a main surface, a back surface opposite thereto, and a plurality of terminals disposed on the main surface along the periphery thereof;a semiconductor chip mounted inside of a row of the terminals on the main surface of the wiring substrate;a plurality of wires for electrically connecting electrodes of the semiconductor chip and the terminals of the wiring substrate, respectively, the terminals of the wiring substrate being connected as a first bond and the electrodes of the semiconductor chip being connected as a second bond; anda plurality of external connection terminals disposed on the back surface of the wiring substrate,wherein a portion of each of the wires is disposed on the side closer to the periphery than a wire connecting portion of the terminal.

2. A semiconductor device according to claim 1, wherein the top of the loop of each of the wires is disposed on the side closer to the periphery than the wire connecting portion of the first bond.

3. A semiconductor device according to claim 1, wherein a solder resist film covering therewith an interconnect on the main surface of the wiring substrate is disposed on the side inner than the wire connecting portion of the first bond.

4. A semiconductor device according to claim 1, wherein an interconnect disposed on the side closer to the periphery than the terminal of the wiring substrate is exposed.

5. A semiconductor device according to claim 1, further comprising: another semiconductor chip stacked over the semiconductor chip; andanother plurality of wires for connecting the electrodes of the semiconductor chip and the electrodes of the another semiconductor chip, the electrodes of the lower-level semiconductor chip being connected as a first bond and the electrodes of the upper-level another semiconductor chip being connected as a second bond,wherein a portion of each of the another plurality of wires is disposed on the side closer to the periphery than the wire connecting portion of the first bond.

6. A manufacturing method of a semiconductor device, comprising the steps of: (a) preparing a wiring substrate having a main surface, a back surface opposite thereto, and a plurality of terminals disposed on the main surface along the periphery thereof;(b) connecting a semiconductor chip to the inside of a row of the terminals on the main surface of the wiring substrate;(c) connecting tip portions of wires in the ball form to the terminals of the wiring substrate, transferring a capillary to a direction distant from the semiconductor chip to pull the wire from the terminal, disposing the capillary on electrodes of the semiconductor chip, and crushing portions of the wires to connect the portions to the electrodes of the semiconductor chip; and(d) sealing the semiconductor chip and the wires,wherein in the step (c), the wires are connected so that a portion of each of the wires is disposed on a side closer to the periphery than a wire connecting portion at the terminal of the wiring substrate.

7. A manufacturing method of a semiconductor device according to claim 6, wherein in the step (c), the wires are connected so that the top of the loop of each of the wires is disposed on a side closer to the periphery than the wire connecting portion at the terminal of the wiring substrate.